An Improved VLSI Test Economics Analysis System - Laboratory for ...
An Improved VLSI Test Economics Analysis System - Laboratory for ... An Improved VLSI Test Economics Analysis System - Laboratory for ...
where N(t 2 , (t 1 + nt)) is number of time intervals between time t 1:n and t 2 . In aboveequation, n substitutes for N(t 2 , (t 1 + nt)) because their summation is equal.In general, continuous costs are not large, so type I cost model is used asC = NU (2.21)2.4.2 Impact of VolumeVolume means number of chips which we attempt delivering to market. This value is decidedby user from market factors such as price, demand, supply, life cycle and peers. Some costsare one time costs, so they are volume independent. We call these costs non-recurring costdenoted as C nrec . Thus, cost per chip Xcan be described XasC chip = (C nrec =N v )+ C rec ; (2.22)per nercper recwhere N v is volume, and C rec is recurring cost. Therefore, lower volume increase eect ofnon-recurring costs, but if volume is high, recurring costs dominate chip cost.Minimal cost test strategy is strongly aected by the volume as we found in our experience.Many test methodologies, such as scan, greatly reduce non-recurring costs butincrease recurring costs. Thus, to use or not to use such test methodologies is according tothe threshold volume. Similar result is also obtained by Wei [6].2.4.3 Development CostThere are a lot of cost issues during development process, including man-power, equipment,space, prototyping, etc. For clarity, the development cost is further divided into the designcost (C dsgn ) and design management cost (Cd mang ):Cd = C dsgn + Cd mang + Kd; (2.23)where Kd is the user dened development cost.Design CostThe design cost, including man-power cost, equipment cost, space cost, and prototype cost,is given byC dsgn = Cd mp + Cd equip + Cd space + C proto + K dsgn ; (2.24)20
where K dsgn is user dened design cost. Each item cost will be evaluated in follow, respectively.Design Man-power (Cd mp ): Let Ud mang be the average salary of engineers and Nd eng be thenumber of design engineers. Also, T degn denotes the design time and Kd mp representsother man-power related costs dened by user, such asbonus or other fringe. Then,the man-power cost is given byCd mp = Ud eng Nd eng T dsgn + Kd mp : (2.25)Design Equipment (Cd equip ): Design equipments include hardware and software in R&D department.Main hardware is computers. Software includes tools and libraries. Eachequipment has three cost: price cost, maintenance cost, and training cost.Generally, these equipments will keep on being used in the following projects, so theprice cost is considered as depreciate dierence of this equipment during design timeof current project.Maintenance cost includes cost to keep the equipment working, such as cost of equipmentpower. It also includes the cost of xing failure part of the equipments and theupgrade cost. Although the older the equipment, the higher the maintenance cost,maintenance cost is xed to a constant for simplicity.Training cost occurs when we buy new equipments for this project. But this costis relative to the quality of trainees. If trainees are familiar to similar equipments,training cost will greatly reduced. Although these well trained engineers maykeep onoperating these equipments in following projects, the whole training cost is accountedin current project for simplicity.When type III model is used for price cost estimation, as Equation 2.14. Our costequation can be expressed asC =(1, (1 + R f ) N t) U: (2.26)In this equation, revenue from bank is ignored, i.e., R int = 0, for simplicity.21
- Page 1 and 2: An Improved VLSI Test Economics Ana
- Page 3 and 4: Contents1 Introduction 11.1 Economi
- Page 5 and 6: List of Figures2.1 Area relation be
- Page 7 and 8: Chapter 1IntroductionFrom business
- Page 9 and 10: costs are summed as the total cost.
- Page 11 and 12: TEEM)" for VLSI test strategy plann
- Page 13 and 14: Chapter 2Economic ModelsIn this cha
- Page 15 and 16: 2.2 Circuit DescriptionThis section
- Page 17 and 18: Gate Area Ratio (gar): Average gate
- Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
- Page 21 and 22: The proposed economic models consis
- Page 23 and 24: However, cost is greatly impacted b
- Page 25: Type II: C = UR f N tThis equation
- Page 29 and 30: where U space is price of the build
- Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
- Page 33 and 34: is aected by gate count, complexity
- Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
- Page 37 and 38: In our study, we run ATPG for ISCAS
- Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
- Page 41 and 42: Chapter 3System DevelopmentIn our s
- Page 43 and 44: the browser.3.2 Analysis FlowConnec
- Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
- Page 47 and 48: If this equation is a function, for
- Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
- Page 51 and 52: Table 4.2: Fault coverage parameter
- Page 53 and 54: Table 4.3: Fault coverage and test
- Page 55 and 56: 4.3 Case StudyIn this section, a re
- Page 57 and 58: Table 4.8: Parameters of time model
- Page 59 and 60: Table 4.12: Cost of dierent volume.
- Page 61 and 62: in Figure 4.4 for 2K volume and Fig
- Page 63 and 64: circuits were translated to Verilog
- Page 65 and 66: Design space cost for rent building
- Page 67 and 68: Revenue with DFT design:R dft = 1 2
- Page 69 and 70: 1s298s344Fault Coverage (FC)0.90.80
- Page 71 and 72: Fault Coverage (FC)10.90.80.70.60.5
- Page 73 and 74: Fault Coverage (FC)10.90.80.70.60.5
- Page 75 and 76: 1*s38584.10.90.80.7Fault Coverage (
where N(t 2 , (t 1 + nt)) is number of time intervals between time t 1:n and t 2 . In aboveequation, n substitutes <strong>for</strong> N(t 2 , (t 1 + nt)) because their summation is equal.In general, continuous costs are not large, so type I cost model is used asC = NU (2.21)2.4.2 Impact of VolumeVolume means number of chips which we attempt delivering to market. This value is decidedby user from market factors such as price, demand, supply, life cycle and peers. Some costsare one time costs, so they are volume independent. We call these costs non-recurring costdenoted as C nrec . Thus, cost per chip Xcan be described XasC chip = (C nrec =N v )+ C rec ; (2.22)per nercper recwhere N v is volume, and C rec is recurring cost. There<strong>for</strong>e, lower volume increase eect ofnon-recurring costs, but if volume is high, recurring costs dominate chip cost.Minimal cost test strategy is strongly aected by the volume as we found in our experience.Many test methodologies, such as scan, greatly reduce non-recurring costs butincrease recurring costs. Thus, to use or not to use such test methodologies is according tothe threshold volume. Similar result is also obtained by Wei [6].2.4.3 Development CostThere are a lot of cost issues during development process, including man-power, equipment,space, prototyping, etc. For clarity, the development cost is further divided into the designcost (C dsgn ) and design management cost (Cd mang ):Cd = C dsgn + Cd mang + Kd; (2.23)where Kd is the user dened development cost.Design CostThe design cost, including man-power cost, equipment cost, space cost, and prototype cost,is given byC dsgn = Cd mp + Cd equip + Cd space + C proto + K dsgn ; (2.24)20
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