An Improved VLSI Test Economics Analysis System - Laboratory for ...

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Market Life Model receives both DFT and no DFT development time from Time Model,than, substrates them to nd development saving time for estimation of extra prot of DFTstrategy.As a result, we compare defect level and prot of DFT with no DFT design to judge ifwe get benet from this DFT strategies. The proposed models describe only a single teststrategy estimation, so optimal test strategy can be obtained by re-evaluating the modelsfor all available strategies. Next section discusses our Cost Model in detail.2.4 Cost ModelCost Model hierarchically analyzes various costs. Therefore, total cost is divided into threeparts: developmental cost, manufacturing cost, and testing cost according to their stages.Estimation equation is given byC = Cd + Cm + Ct + K; (2.9)where K denotes the unmodeled cost. The user can modify this equation using K. Forexample, he can assign K to ,Ct+120 if testing cost is xed to $120 in our model. Moreover,each stage consists of various detailed items, as shown in Figure 2.3.C(overall cost)Cd(development)Cm(manufacture)Ct(test)CdieCpackage CmaskCdmp(men power)Cdsgn(design)Cdequip(equipment)Cdmang(mangement)Cdspace(space)Cw(wafer test) Cp(pre-burn-in test)Cproto(prototyping)Cb(final test)Figure 2.3: Hierarchical structure of Cost Model.16
However, cost is greatly impacted by time and volume as we found in our analysis. Theway how time impacts cost is therefore performed in rst subsection. Second subsectionconsiders the relation between cost and volume. Finally, the later three subsections describedetailed item costs in each stage respectively.2.4.1 Impact of Timef 2bf 2bf 1C=f 2b -f 2af 2af 2a1t t 2Figure 2.4: How is cost impacted by time?We consider the capital cost rst. As shown in Figure 2.4 in time t 1 ,acapital of f 1 waspurchased. This capital depreciated to f 2a at time t 2 . If the same money was invested toother project, the estimated revenue is f 2b . The exact cost of this capital should beC f1 = f 2b , f 2a t 1 ,t 2: (2.10)For example, a cost of tester U tester was invested in time t 1 . We used this tester until time t 2in the project. Depreciative ratio per time interval of this tester is assumed R d . Then, thevalue of this tester in time t 2 isf 2a =(1, R d ) N t U tester ; (2.11)where N t is number of depreciation time intervals between t 1 with t 2 . Moreover, if thosemoney was deposed into bank instead of investing tester, nal revenue, including interest, isf 2b =(1+R int ) N t U tester ; (2.12)17
Page 1 and 2: An Improved VLSI Test Economics Ana
Page 3 and 4: Contents1 Introduction 11.1 Economi
Page 5 and 6: List of Figures2.1 Area relation be
Page 7 and 8: Chapter 1IntroductionFrom business
Page 9 and 10: costs are summed as the total cost.
Page 11 and 12: TEEM)" for VLSI test strategy plann
Page 13 and 14: Chapter 2Economic ModelsIn this cha
Page 15 and 16: 2.2 Circuit DescriptionThis section
Page 17 and 18: Gate Area Ratio (gar): Average gate
Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
Page 21: The proposed economic models consis
Page 25 and 26: Type II: C = UR f N tThis equation
Page 27 and 28: where K dsgn is user dened design c
Page 29 and 30: where U space is price of the build
Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
Page 33 and 34: is aected by gate count, complexity
Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
Page 37 and 38: In our study, we run ATPG for ISCAS
Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
Page 41 and 42: Chapter 3System DevelopmentIn our s
Page 43 and 44: the browser.3.2 Analysis FlowConnec
Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
Page 47 and 48: If this equation is a function, for
Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
Page 51 and 52: Table 4.2: Fault coverage parameter
Page 53 and 54: Table 4.3: Fault coverage and test
Page 55 and 56: 4.3 Case StudyIn this section, a re
Page 57 and 58: Table 4.8: Parameters of time model
Page 59 and 60: Table 4.12: Cost of dierent volume.
Page 61 and 62: in Figure 4.4 for 2K volume and Fig
Page 63 and 64: circuits were translated to Verilog
Page 65 and 66: Design space cost for rent building
Page 67 and 68: Revenue with DFT design:R dft = 1 2
Page 69 and 70: 1s298s344Fault Coverage (FC)0.90.80
Page 71 and 72: Fault Coverage (FC)10.90.80.70.60.5
Page 73 and 74:
Fault Coverage (FC)10.90.80.70.60.5
Page 75 and 76:
1*s38584.10.90.80.7Fault Coverage (
Page 77 and 78:
Kd mp : user-dened man-power cost .
Page 79:
[13] R. G. Bennetts, C. M. Maunder,
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