An Improved VLSI Test Economics Analysis System - Laboratory for ...
An Improved VLSI Test Economics Analysis System - Laboratory for ... An Improved VLSI Test Economics Analysis System - Laboratory for ...
predictability. All these keys strongly depend on structure of circuit such as I/Os,sequential depth, internal loop length, etc. We suggest user to estimate its valuefrom similar functional block design cases which had done before, because they usuallyhave similar circuit structure except design methodologies had been changed.Testability impacts defect level, diagnosis, verication and test eort which will bediscussed in later section. In general, we use DFT to increase block testability.Chip Testability (TB): Chip Testability, similar to testability of block, is dened as the easeto transfer test vectors into blocks (controllability) and fetch results (observability)from chip I/Os. Its value depends on the depth of blocks from chip I/Os, andtestability of blocks in chip. Some DFT methodologies also increase chip testability.The impact of DFT in chip and block testability will be estimated in Section 2.8 .Test Vector Length (v w ;v p ;v f ;V w ;V p ;V f ): They are test lengths of block and chip while thechip is in wafer test, production test, and burn-in test stages. We will describe detailin Section 2.6, Quality Model.In the next section, we introduce our economic models.2.3 Introduction to Economic ModelTest MethodologiesCircuit DescriptionQuality ModelsTime ModelsCost ModelsMarket LifeModelsDefect Level EstimationProfit EstimationFigure 2.2: Relation of models.14
The proposed economic models consists of four models: Cost Model, Time Model, MarketLife Model and Quality Model. Besides, we propose a test methodology library to describewhat and how circuit parameters are modied by various Test methodologies. Figure 2.2shows relations among circuit description, test methodologies and our four models. Finalresult is prot estimation, which can be given byProf = R , C; (2.8)where C is total cost which is estimated in Cost Model and R is revenue which comes fromMarket Life Model. Another result is defect level estimation, which is calculated in QualityModel. Complete estimation need two passes to each model. For the rst pass, we targetestimation on the condition of no DFT applied, and more detailed action of each model isdescribed bellow:Quality Model: It estimates test-related parameters, such as yield, fault coverage, defect level,and test length, from area, gate count, testability, etc., which get from circuit description.The defect level is an important pointer of production quality, and otherresults are transfered to time and cost models.Time Model: This model estimates parameters about time. It receives circuit descriptionand Quality Model parameters, than, estimates design and verication time in development,and test time in wafer test, pre-burn-in test, and nal test. Finally, theresults are transfered to cost model.Cost Model: This model collects parameters from circuit description, Time Model, and QualityModel to calculate total costs for prot estimation. Total cost merges three stagecost which are development cost, manufacturing cost, and test cost.Market Life Model: This model uses only its local parameters to estimate revenue, becausewe assume that revenue only comes from market.In the second pass, some circuit parameters and equations in models, such as area, and gatecount, are modied according to the test strategy. All modication rules are listed in testmethodology library. Continue the similar processes of each model as rst pass, except that15
- Page 1 and 2: An Improved VLSI Test Economics Ana
- Page 3 and 4: Contents1 Introduction 11.1 Economi
- Page 5 and 6: List of Figures2.1 Area relation be
- Page 7 and 8: Chapter 1IntroductionFrom business
- Page 9 and 10: costs are summed as the total cost.
- Page 11 and 12: TEEM)" for VLSI test strategy plann
- Page 13 and 14: Chapter 2Economic ModelsIn this cha
- Page 15 and 16: 2.2 Circuit DescriptionThis section
- Page 17 and 18: Gate Area Ratio (gar): Average gate
- Page 19: (a) (b) (c)Figure 2.1: Area relatio
- Page 23 and 24: However, cost is greatly impacted b
- Page 25 and 26: Type II: C = UR f N tThis equation
- Page 27 and 28: where K dsgn is user dened design c
- Page 29 and 30: where U space is price of the build
- Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
- Page 33 and 34: is aected by gate count, complexity
- Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
- Page 37 and 38: In our study, we run ATPG for ISCAS
- Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
- Page 41 and 42: Chapter 3System DevelopmentIn our s
- Page 43 and 44: the browser.3.2 Analysis FlowConnec
- Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
- Page 47 and 48: If this equation is a function, for
- Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
- Page 51 and 52: Table 4.2: Fault coverage parameter
- Page 53 and 54: Table 4.3: Fault coverage and test
- Page 55 and 56: 4.3 Case StudyIn this section, a re
- Page 57 and 58: Table 4.8: Parameters of time model
- Page 59 and 60: Table 4.12: Cost of dierent volume.
- Page 61 and 62: in Figure 4.4 for 2K volume and Fig
- Page 63 and 64: circuits were translated to Verilog
- Page 65 and 66: Design space cost for rent building
- Page 67 and 68: Revenue with DFT design:R dft = 1 2
- Page 69 and 70: 1s298s344Fault Coverage (FC)0.90.80
predictability. All these keys strongly depend on structure of circuit such as I/Os,sequential depth, internal loop length, etc. We suggest user to estimate its valuefrom similar functional block design cases which had done be<strong>for</strong>e, because they usuallyhave similar circuit structure except design methodologies had been changed.<strong>Test</strong>ability impacts defect level, diagnosis, verication and test eort which will bediscussed in later section. In general, we use DFT to increase block testability.Chip <strong>Test</strong>ability (TB): Chip <strong>Test</strong>ability, similar to testability of block, is dened as the easeto transfer test vectors into blocks (controllability) and fetch results (observability)from chip I/Os. Its value depends on the depth of blocks from chip I/Os, andtestability of blocks in chip. Some DFT methodologies also increase chip testability.The impact of DFT in chip and block testability will be estimated in Section 2.8 .<strong>Test</strong> Vector Length (v w ;v p ;v f ;V w ;V p ;V f ): They are test lengths of block and chip while thechip is in wafer test, production test, and burn-in test stages. We will describe detailin Section 2.6, Quality Model.In the next section, we introduce our economic models.2.3 Introduction to Economic Model<strong>Test</strong> MethodologiesCircuit DescriptionQuality ModelsTime ModelsCost ModelsMarket LifeModelsDefect Level EstimationProfit EstimationFigure 2.2: Relation of models.14
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