An Improved VLSI Test Economics Analysis System - Laboratory for ...
An Improved VLSI Test Economics Analysis System - Laboratory for ... An Improved VLSI Test Economics Analysis System - Laboratory for ...
AbstractManagers used to consider design for testability (DFT) as an overhead in development andproduction rather than an aid. We take a full consideration on the relation between DFTmethodologies and cost/revenue models, and show that DFT may actually help engineers toshorten the total time needed in product development, which leads to lower man-power costand shorter time to market, and therefore results in more revenue through out the product'slife time. Production cost may also be reduced due to lower testing cost.Base on this, economic models are developed to model the cost and revenue of a VLSIproduct. Our system consists of a set of circuit parameters, four models, and a test methodologylibrary. The circuit parameters are normally available or easy to estimate early inthe design phase. The four models are Cost Model, Market Life Model, Time Model, andQuality Model, respectively Cost Model estimates cost, and Market Life Model estimatesrevenue. The other two models estimate parameters used by the previous two. Time Modelestimates all time related parameters, and Quality Model estimates test related parameters.Moreover, the test methodology library describes the eect of DFT on all parameters.A WWW-based VLSI test strategy planning system|the Evaluation System for TEstEngineering Methodologies (ESTEEM)|has been developed. It is an improved version ofthe system that we have developed over the past two years. The system is realized by awebbase program with secure, friendly graphic user interface and exible analysis engine.Test length and test generation time of ISCAS'89 benchmark circuits and the scanmodiedcircuits were evaluated to compare the dierence between normal and scan design.Finally, an IEEE 1149.5 MTM-Bus slave module chip is analyzed by our system. The resultshows the prot will greatly increase if DFT is used, since it saves the development timeand shortens time to market. Besides, by comparing dierent volumes for the same case, wefound a threshold volume. The total cost with DFT is lower than that without DFT underthis threshold volume.
Contents1 Introduction 11.1 Economic Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2 Analysis System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 Previous Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Economic Models 72.1 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.2 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.3 Introduction to Economic Model . . . . . . . . . . . . . . . . . . . . . . . . . 142.4 Cost Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.4.1 Impact of Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.4.2 Impact of Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202.4.3 Development Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202.4.4 Manufacturing Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.4.5 Testing Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.5 Time Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262.6 Quality Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272.6.1 Defect Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282.6.2 Yield . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282.6.3 Fault Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292.7 Market Life Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322.8 Impact of Design for Testability . . . . . . . . . . . . . . . . . . . . . . . . . 33i
- Page 1: An Improved VLSI Test Economics Ana
- Page 5 and 6: List of Figures2.1 Area relation be
- Page 7 and 8: Chapter 1IntroductionFrom business
- Page 9 and 10: costs are summed as the total cost.
- Page 11 and 12: TEEM)" for VLSI test strategy plann
- Page 13 and 14: Chapter 2Economic ModelsIn this cha
- Page 15 and 16: 2.2 Circuit DescriptionThis section
- Page 17 and 18: Gate Area Ratio (gar): Average gate
- Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
- Page 21 and 22: The proposed economic models consis
- Page 23 and 24: However, cost is greatly impacted b
- Page 25 and 26: Type II: C = UR f N tThis equation
- Page 27 and 28: where K dsgn is user dened design c
- Page 29 and 30: where U space is price of the build
- Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
- Page 33 and 34: is aected by gate count, complexity
- Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
- Page 37 and 38: In our study, we run ATPG for ISCAS
- Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
- Page 41 and 42: Chapter 3System DevelopmentIn our s
- Page 43 and 44: the browser.3.2 Analysis FlowConnec
- Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
- Page 47 and 48: If this equation is a function, for
- Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
- Page 51 and 52: Table 4.2: Fault coverage parameter
AbstractManagers used to consider design <strong>for</strong> testability (DFT) as an overhead in development andproduction rather than an aid. We take a full consideration on the relation between DFTmethodologies and cost/revenue models, and show that DFT may actually help engineers toshorten the total time needed in product development, which leads to lower man-power costand shorter time to market, and there<strong>for</strong>e results in more revenue through out the product'slife time. Production cost may also be reduced due to lower testing cost.Base on this, economic models are developed to model the cost and revenue of a <strong>VLSI</strong>product. Our system consists of a set of circuit parameters, four models, and a test methodologylibrary. The circuit parameters are normally available or easy to estimate early inthe design phase. The four models are Cost Model, Market Life Model, Time Model, andQuality Model, respectively Cost Model estimates cost, and Market Life Model estimatesrevenue. The other two models estimate parameters used by the previous two. Time Modelestimates all time related parameters, and Quality Model estimates test related parameters.Moreover, the test methodology library describes the eect of DFT on all parameters.A WWW-based <strong>VLSI</strong> test strategy planning system|the Evaluation <strong>System</strong> <strong>for</strong> TEstEngineering Methodologies (ESTEEM)|has been developed. It is an improved version ofthe system that we have developed over the past two years. The system is realized by awebbase program with secure, friendly graphic user interface and exible analysis engine.<strong>Test</strong> length and test generation time of ISCAS'89 benchmark circuits and the scanmodiedcircuits were evaluated to compare the dierence between normal and scan design.Finally, an IEEE 1149.5 MTM-Bus slave module chip is analyzed by our system. The resultshows the prot will greatly increase if DFT is used, since it saves the development timeand shortens time to market. Besides, by comparing dierent volumes <strong>for</strong> the same case, wefound a threshold volume. The total cost with DFT is lower than that without DFT underthis threshold volume.
Change language