An Improved VLSI Test Economics Analysis System - Laboratory for ...

Area per Pad (A p ): Area of pad which takes advantages of bounding technology, can be moreand more small. It's value is in range of 80 80mm 2 to 38 38mm 2 , and typicalvalue is 50 50mm 2 . The size of pad also depends on the frequency of the chip.Higher frequency chips need larger pad area.Area and Pins of Chip (A; P ): As shown in Figure 2.1, Chip die consists of a core in centerand pads around it. Number of pads, which is equal to pin count, depends on chipfunction. In idea condition, the relation of area between core and pads is shown inFigure 2.1(a), all pads compact around the core to gain maximal utilization of chiparea. In the condition of maximal utilization, relation between pins and area isp AcoreP =4 p +1Apad: (2.5)Sometimes, a design needs not much I/Os but has very complex inner function whoseimplementation needs large area, or implementation of core uses too much area thanthe area allocated in oor planning. The result, called core bounded design, mayseem as Figure 2.1(b), some area around core wasted. To increase area utilization,additional pins can be added for test and diagnosis to increase testability of circuitif package cost allows. Alternatively, if pad bounded condition occurs, as shown inFigure 2.1(c), extra area can be used for DFT circuit such as scan. However, it isassumed that the design is always in maximal utilization condition in our analysis.Therefore, any extra area and pins due to DFT are regarded overhead which needto be estimated as cost in our models.Core area (A core ), similar to chip gate count, includes block and interface circuitarea, is given byA core =Xfor all blocksa + A ,; (2.6)where A is a parameter which transfers chip complexity to interface circuit area.The total chip area therefore isA = A core + PA p=Xfor all blocksa + A ,+PA p :(2.7)12