An Improved VLSI Test Economics Analysis System - Laboratory for ...

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Table 2.4: Types of block.TypesLogicMemoryCoreDetailed TypesData Path, Control, PLA, ILARAM, ROM, CAM, Register FileEmbedded coreTable 2.5: Test methodologies for each type of block.TypesLogicMemoryCoreTest MethodologiesFull Scan, Partial Scan, BIST, Custom DFTScan, Memory BIST, Direct I/O access, Custom Array DFTScan, BIST, Direct I/O access, Custom DFTTest Methodology of Block (tm): Traditional testing methodologies for each type of functionalblock are listed in table 2.5.Gate Count of Block (g): Gate count represents the area quantity of functional blocks. It isexpressed as the number of two-input nand gates needed to ll up this amount ofarea. Its value depends on the functions of blocks, the algorithm, the implementationmethodologies, and the performance-area or the power-area trade o.Number of Nets in Block (n): The exact value of the number of nets in block depends ongate count and routing complexity. We oer an easy way to estimate this parameter:assume that the circuit consists of 2-input nand gates only, and is fanout free, then,each gate will connect to three nets and each net will connect two gates.estimation function can be derived asOurn = 3 g: (2.1)2I/Os of Block (p): General types of I/O include input, output and in-out. The complexityof interface circuits and the testability of block are aected not only by the numberof block I/Os but also by their types. In our study, we neglect the eect of dierentI/O types for simplicity.10
Gate Area Ratio (gar): Average gate area ratio is used for conversion of gate count intogate area. The exact value of gar depends on the manufacturing process and theimplementation methodologies. For examples: the gar of :6 process has higherthan that of :8 process. Also, full custom, cell base, gate array, PAL, and FPGAdesign have dierent gate area ratios.Net Area Ratio (nar): Average net area ratio is used for conversion of the member of netsinto routing area. It means the average area of each net in block. The nar dependson the manufacturing process, implementation methodologies and the eciency ofrouting tools.Block Area (a): Block area including gate area and net area can be expressed as:a = g gar + n nar: (2.2)Chip Complexity (,): Chip complexity represents the eort to integrate blocks into chip.Consider a graph consist of n nodes, if all nodes must connect to each other, themaximal links is (n,1)!. The upper bound of connection complexity is proportionalto it. However, not all nodes need to connect to each other, since some interfacestructures such as bus greatly reduce the complexity. Block's I/O count and howsignals transmit among blocks also aect complexity.Gate Count of Chip (G): Gate count of chip includes block gates and interface circuits betweenblocks. The gate count of interface circuit is proportional to chip complexity(,). Thus, this parameters can be given byG =Xfor all blocksg + G ,; (2.3)where G is the parameters which converts chip complexity into interface circuitsgate count. If estimation omits interface circuits, gate count can be calculated asG =Xeach blockg: (2.4)11
Page 1 and 2: An Improved VLSI Test Economics Ana
Page 3 and 4: Contents1 Introduction 11.1 Economi
Page 5 and 6: List of Figures2.1 Area relation be
Page 7 and 8: Chapter 1IntroductionFrom business
Page 9 and 10: costs are summed as the total cost.
Page 11 and 12: TEEM)" for VLSI test strategy plann
Page 13 and 14: Chapter 2Economic ModelsIn this cha
Page 15: 2.2 Circuit DescriptionThis section
Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
Page 21 and 22: The proposed economic models consis
Page 23 and 24: However, cost is greatly impacted b
Page 25 and 26: Type II: C = UR f N tThis equation
Page 27 and 28: where K dsgn is user dened design c
Page 29 and 30: where U space is price of the build
Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
Page 33 and 34: is aected by gate count, complexity
Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
Page 37 and 38: In our study, we run ATPG for ISCAS
Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
Page 41 and 42: Chapter 3System DevelopmentIn our s
Page 43 and 44: the browser.3.2 Analysis FlowConnec
Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
Page 47 and 48: If this equation is a function, for
Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
Page 51 and 52: Table 4.2: Fault coverage parameter
Page 53 and 54: Table 4.3: Fault coverage and test
Page 55 and 56: 4.3 Case StudyIn this section, a re
Page 57 and 58: Table 4.8: Parameters of time model
Page 59 and 60: Table 4.12: Cost of dierent volume.
Page 61 and 62: in Figure 4.4 for 2K volume and Fig
Page 63 and 64: circuits were translated to Verilog
Page 65 and 66: Design space cost for rent building
Page 67 and 68:
Revenue with DFT design:R dft = 1 2
Page 69 and 70:
1s298s344Fault Coverage (FC)0.90.80
Page 71 and 72:
Fault Coverage (FC)10.90.80.70.60.5
Page 73 and 74:
Fault Coverage (FC)10.90.80.70.60.5
Page 75 and 76:
1*s38584.10.90.80.7Fault Coverage (
Page 77 and 78:
Kd mp : user-dened man-power cost .
Page 79:
[13] R. G. Bennetts, C. M. Maunder,
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