An Improved VLSI Test Economics Analysis System - Laboratory for ...

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DFT methodologies will be shown in the last section.2.1 NotationIn this section, we dene notation of the variables used in this paper. The variables aredesigned by the following two rules.Rule 1: A Capital letter represents a chip-level parameter and a small letter represents ablock-level one.For example: g is the gate count of a block and G is the gate count of a chip.Rule 2: Three parts compose a variable.A variable has the following basic form: Ts i , where the capital letter T , the smallletter s, and the subscript i represent the Type, the Stage, and the Item of theparameter, respectively. Examples of the notation are listed in Table 2.1. Sometimes,the stage can be implied by the item. For example, U wafer (cost per wafer) is obviouslyin manufacture stage, so we do not need to include this part in the notation. However,Cd mang(design management cost) must indicate the development stage explicitly,because management cost may occur during development and manufacturing stages.Table 2.2 lists some general types of parameters and their notation.Table 2.1: Examples of notation.Notation Type Stage Item DescriptionCd mang Cost Development Management Development management costTt f Time Test Final Final test timeU wafer Unit Cost Manufacturing Wafer Productive cost per waferTable 2.2: Type and notation of parameters in models.Notation Type ExampleC Cost Cd Development costR Ratio Rd mang Development management time ratioK User Dene Kd User dene development costT Time Td Development timeN Number Nv Volume to deliverU Unit Cost Ud eng Salary per design engineer8
2.2 Circuit DescriptionThis section denes parameters to specify circuit. Because DFT strategies must be appliedbefore detailed design, the circuit specication need to be targeted at the oor-planningstage. In this stage, designs are partitioned into several functional blocks, so we divide ourparameters into two groups: block parameters and chip parameters. As shown in Table 2.3,parameters with similar attribute are listed in the same row.The functional blocks can be IP cores from vender, previously designed blocks, or bareblocks designed from scratch.If this block is an IP core, the exact value of block mostparameters is available from the data sheet. As to redesign blocks, these parameters canbe estimated from previous designs. Unfortunately, if the block designed from scratch, theyneeds to be predicted by the block function, the block spec, and the user's experiences.Table 2.3: Parameters of circuit description.Block ParametersChip ParametersN B number of blocks in chipt type of blocka area of block A area of chipg number of gates in block G number of gates in chipgar gate area ratio of blockn number of nets in block N number of nets in chipnar net area ration of blockp number of I/Os of block P number of pinsA P pad area complexity of block , complexity ofchip re-usability ofblocktb testability of block TB testability ofchipv test length of block V test length of chiptm test methodologies used in block TM test methodologies used for whole chipThe subsequent discussions provide more details of each parameter:Type of Block (t): According to Sematech DFT workshop report [10], there are three typesof functional blocks: Logic, Memory, and Core. Each type needs dierent testingmethodologies. Moreover, each type contains some kinds of functional blocks. asshown in table 2.4.9
Page 1 and 2: An Improved VLSI Test Economics Ana
Page 3 and 4: Contents1 Introduction 11.1 Economi
Page 5 and 6: List of Figures2.1 Area relation be
Page 7 and 8: Chapter 1IntroductionFrom business
Page 9 and 10: costs are summed as the total cost.
Page 11 and 12: TEEM)" for VLSI test strategy plann
Page 13: Chapter 2Economic ModelsIn this cha
Page 17 and 18: Gate Area Ratio (gar): Average gate
Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
Page 21 and 22: The proposed economic models consis
Page 23 and 24: However, cost is greatly impacted b
Page 25 and 26: Type II: C = UR f N tThis equation
Page 27 and 28: where K dsgn is user dened design c
Page 29 and 30: where U space is price of the build
Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
Page 33 and 34: is aected by gate count, complexity
Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
Page 37 and 38: In our study, we run ATPG for ISCAS
Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
Page 41 and 42: Chapter 3System DevelopmentIn our s
Page 43 and 44: the browser.3.2 Analysis FlowConnec
Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
Page 47 and 48: If this equation is a function, for
Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
Page 51 and 52: Table 4.2: Fault coverage parameter
Page 53 and 54: Table 4.3: Fault coverage and test
Page 55 and 56: 4.3 Case StudyIn this section, a re
Page 57 and 58: Table 4.8: Parameters of time model
Page 59 and 60: Table 4.12: Cost of dierent volume.
Page 61 and 62: in Figure 4.4 for 2K volume and Fig
Page 63 and 64: circuits were translated to Verilog
Page 65 and 66:
Design space cost for rent building
Page 67 and 68:
Revenue with DFT design:R dft = 1 2
Page 69 and 70:
1s298s344Fault Coverage (FC)0.90.80
Page 71 and 72:
Fault Coverage (FC)10.90.80.70.60.5
Page 73 and 74:
Fault Coverage (FC)10.90.80.70.60.5
Page 75 and 76:
1*s38584.10.90.80.7Fault Coverage (
Page 77 and 78:
Kd mp : user-dened man-power cost .
Page 79:
[13] R. G. Bennetts, C. M. Maunder,
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