An Improved VLSI Test Economics Analysis System - Laboratory for ...
An Improved VLSI Test Economics Analysis System - Laboratory for ... An Improved VLSI Test Economics Analysis System - Laboratory for ...
ogy incorporating structural, behavioral, qualitative and quantitative aspects of known DFTtechniques.The successor of TDES is TIGER (Testability Insertion Guidance ExpeRt [2]), whichis now an industrial tool. It handles gate level descriptions, and uses a more sophisticatedpartitioning process than TDES. It uses a similar weighting system to evaluate embedding,mainly in terms of area overhead, estimated test pattern generation (TPG) eort, and estimatedtest time.Brendan Davis proposed EVALUATE [3] which is a decision support tool mainly forthe manufacturing test strategy part of the overall test strategy in 1994. It also includesthe design to test strategy and the eld-service strategy. Since EVALUATE produces anindication of the likely number of defects that will `escape' to the eld for each dierentstrategy analyzed, it eectively provides a measure of the eld-service workload also.1995, Dislis et al. proposed test strategy planners called ECOtest and ECOvbs [4]. TheECOvbs applied the same principles of economics to board designs as ECOtest did to ASICdesigns. It fully calculated the economic and technical eects of test method and also oerssome design optimization and a range of dierent test strategy planning algorithms.All of above papers estimate test cost of well-designed circuits. However, many DFTmethods must be applied before detailed design. Models should not use the parameterswhich is dicult to obtain or estimate in the oor-planning stage. Kim [5] proposed a testcost prediction model which estimates the cost of IC testing in a manufacturing environment.This model predicts chip testing cost and quality of test using a set of circuit manufacturingparameters. Those parameters are available at the early stage of the design cycle. But, theirmodel did not consider the condition of DFT.In [6], another cost model called CMU Test Cost model was proposed. Then, this modelwas used with a range of parameters representing typical industrial conditions to nd athreshold volume. This volume indicates if we get benet from DFT. They found thatcost and benet of DFT is strongly aected by the volume. Similar result was obtained byWei [7]. This paper just found the relation among DFT related parameters, cost and volume.However, they did not describe how DFT methodologies aects these parameters.In our research group, the "Evaluation System for TEst Engineering methodologies (ES-4
TEEM)" for VLSI test strategy planning [7,8], has been developed to accomplish the analysisprocess of test strategy planning. This system uses cost models to calculate the overall costand a test methodologies library to oer suitable test methods for various circuits. However,the original version [8] used some parameters that can only be obtained after the design wasdone.The web-based version of ESTEEM [7] used Java to provide a cross-platform standardgraphic user interface (GUI) environment, and users can perform analysis by web browservia the Internet. Besides, it integrates a Standard Query Language (SQL) database serverto handle the user's data. However, the pure Java system is not stable enough while it itaccessed on the browser. We propose a more stable system in our study.Base on the previous works, we add a quality model to calculate more precise values oftest related parameters, such as fault coverage, yield and defect level. The whole system nowincludes four models: Cost Model, Time Model, Quality Model and Market Life Model. Inthe Cost Model, we propose three basic cost types to estimate costs, and divide test cost intothree stages: wafer test, pre-burn-in test and nal test. Besides, in the circuit description,we propose many suggestion and heuristic to help the user estimate circuit parameters whichare hard to obtain. The economic models will be detailed in Chapter 2 and summarized inAppendix A.The new version of ESTEEM provides more security to user data. The system uses Perl,Java and Javascript languages and integrates web server, SQL server, and CGI programs.This system provides more friendly user interface, such as le manager, model editor, andresult display. Besides, a more powerful analysis engine is developed, so user can easily addnew equations or modify proposed models to t the condition of their companies. Moredetails will be discussed in Chapter 3.Moreover, the ISCAS'89 were applied to sequential ATPG and random pattern fault simulator.Then, ISCAS'89 SCAN were applied to combinational ATPG. Test length and testgeneration time of normal circuits and its scan-modied circuits were evaluated to comparethe dierence between them. Then, ISCAS'89 circuits were translated to verilog format tosynthesis. The synthesized area of ISCAS'89 and its scan version were compared.Finally, an IEEE 1149.5 MTM-Bus slave module chip is analyzed by our system [9].5
- Page 1 and 2: An Improved VLSI Test Economics Ana
- Page 3 and 4: Contents1 Introduction 11.1 Economi
- Page 5 and 6: List of Figures2.1 Area relation be
- Page 7 and 8: Chapter 1IntroductionFrom business
- Page 9: costs are summed as the total cost.
- Page 13 and 14: Chapter 2Economic ModelsIn this cha
- Page 15 and 16: 2.2 Circuit DescriptionThis section
- Page 17 and 18: Gate Area Ratio (gar): Average gate
- Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
- Page 21 and 22: The proposed economic models consis
- Page 23 and 24: However, cost is greatly impacted b
- Page 25 and 26: Type II: C = UR f N tThis equation
- Page 27 and 28: where K dsgn is user dened design c
- Page 29 and 30: where U space is price of the build
- Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
- Page 33 and 34: is aected by gate count, complexity
- Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
- Page 37 and 38: In our study, we run ATPG for ISCAS
- Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
- Page 41 and 42: Chapter 3System DevelopmentIn our s
- Page 43 and 44: the browser.3.2 Analysis FlowConnec
- Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
- Page 47 and 48: If this equation is a function, for
- Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
- Page 51 and 52: Table 4.2: Fault coverage parameter
- Page 53 and 54: Table 4.3: Fault coverage and test
- Page 55 and 56: 4.3 Case StudyIn this section, a re
- Page 57 and 58: Table 4.8: Parameters of time model
- Page 59 and 60: Table 4.12: Cost of dierent volume.
TEEM)" <strong>for</strong> <strong>VLSI</strong> test strategy planning [7,8], has been developed to accomplish the analysisprocess of test strategy planning. This system uses cost models to calculate the overall costand a test methodologies library to oer suitable test methods <strong>for</strong> various circuits. However,the original version [8] used some parameters that can only be obtained after the design wasdone.The web-based version of ESTEEM [7] used Java to provide a cross-plat<strong>for</strong>m standardgraphic user interface (GUI) environment, and users can per<strong>for</strong>m analysis by web browservia the Internet. Besides, it integrates a Standard Query Language (SQL) database serverto handle the user's data. However, the pure Java system is not stable enough while it itaccessed on the browser. We propose a more stable system in our study.Base on the previous works, we add a quality model to calculate more precise values oftest related parameters, such as fault coverage, yield and defect level. The whole system nowincludes four models: Cost Model, Time Model, Quality Model and Market Life Model. Inthe Cost Model, we propose three basic cost types to estimate costs, and divide test cost intothree stages: wafer test, pre-burn-in test and nal test. Besides, in the circuit description,we propose many suggestion and heuristic to help the user estimate circuit parameters whichare hard to obtain. The economic models will be detailed in Chapter 2 and summarized inAppendix A.The new version of ESTEEM provides more security to user data. The system uses Perl,Java and Javascript languages and integrates web server, SQL server, and CGI programs.This system provides more friendly user interface, such as le manager, model editor, andresult display. Besides, a more powerful analysis engine is developed, so user can easily addnew equations or modify proposed models to t the condition of their companies. Moredetails will be discussed in Chapter 3.Moreover, the ISCAS'89 were applied to sequential ATPG and random pattern fault simulator.Then, ISCAS'89 SCAN were applied to combinational ATPG. <strong>Test</strong> length and testgeneration time of normal circuits and its scan-modied circuits were evaluated to comparethe dierence between them. Then, ISCAS'89 circuits were translated to verilog <strong>for</strong>mat tosynthesis. The synthesized area of ISCAS'89 and its scan version were compared.Finally, an IEEE 1149.5 MTM-Bus slave module chip is analyzed by our system [9].5
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