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Fig. 1 scaling guideline as a function of gate length2007), (Ruangphanit, Hansoongnoen, Phongphanchanthra, Klunngien, Niemcharoen, & Muanghlua,Drain Induced Barrier Lowering in Buried Channel PMOS Devices, 2007) also. For isolation, the fieldoxide thickness is 650 nm. The N-field implantation beneath the field oxide is implanted for increasingthe field threshold voltage. To reduce the hot carriers, phosphorus and boron with low energy isimplemented to form LDD of NMOS and PMOS structure (Wolf, The Submicron MOSFET, 1995),(Niemcharoen, Phongphachanthra, Ruangphanit, Klunngien, Meesapawong, & Sonboonton, 2007). Asand BF 2 are implemented to produce source/drain of NMOS and PMOS respectively. From simulationresults, X j was approximately 0.4 µm for both devices and the effective channel length wasapproximately 0.6 µm of both MOSFETs.V TH(V)1.00.90.80.70.60.50.40.30.2L g= 0.8 µm7x10 11 8x10 11 9x10 11 1x10 12Channel Doping (cm -2 )V TH(V)-0.2-0.4-0.6-0.8-1.0-1.2-1.4L g= 0.8 µm3.6E12 cm -24.0E12 cm -24.5E12 cm -25.0E12 cm -26.0E12 cm -27.00E+011 8.00E+011 9.00E+011 1.00E+012Channel Doping (cm -2 )(a)(b)Fig. 2 Simulated threshold voltage of (a) NMOS versus channel doping dose and (b) PMOS versuschannel doping dose with N-well doping dose as a parameterV TH(V)0.800.750.700.650.600.55Channel Doping cm -30.500.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5L g(µm)1E129E118E117E11V TH(V)-0.2 Nwell Dose =3.6E12 cm -2 1E12 cm -2-0.3-0.4-0.5-0.6-0.7-0.8-0.9-1.00.0 0.5 1.0 1.5 2.0 2.5 3.0L g(µm)9E11 cm -28E11 cm -27E11 cm -2(a)(b)118

Fig. 3 Simulated threshold voltage versus design gate length with a channel doping dose as a parameterof (a) NMOS and (b) PMOS with n-well dose = 3.6×10 12 cm -2V TH(v)1.2 1E12 cm- 21.19E11 cm- 21.08E11 cm- 20.90.80.70.60.50.40.30.20.10.012 14 16 18 20 22 24t ox(nm)V TH(V)-0.5-0.6-0.7-0.8-0.9-1.01E12 cm -29E11 cm -28E11 cm -212 14 16 18 20 22 24t ox(nm)(a)(b)Fig. 4 Simulated threshold voltage versus gate oxide thickness with a channel doping dose as aparameter of (a) NMOS and (b) PMOSMATERIALS AND METHODSIn fabrication, the processes were done on 150 mm p-type silicon wafers with resistivity of 5ohm-cm. The process fabrication included 8 lithography steps for front end of line (FEOL) and 5lithography steps for back end of line (BEOL) levels which were exposed on a Nikon NSR-2500i8A 5xreduction stepper with i-line photo resist. The cross section of 0.8 µm CMOS process was shown in Fig.5. Fully scaled 0.8 µm design rules as well as non-fully scaled custom design rules were included in anew test chip. The N-well and the P-well were fabricated by phosphorus with dose in order of 10 12 cm -2and boron implantation with dose in order of 10 11 cm -2 , respectively. For LOCOS isolation, the fieldoxide thickness was 650 nm. The operation voltage should not be more than 15 V because of thisdesigned field oxide thickness. The N-field implantation beneath the field oxide was implanted forincreasing the field oxide threshold voltage.However, the bird’s break encroachment must be controlled because it affects the source/drainformation. Besides this effect, the bird’s beak encroachment into the active area must be determined inorder to know the minimum designed gate width which has an enough active area will be formed. A 25nm gate oxide was grown in a thermal furnace at 900°C in dry ambience. A 350 nm polysilicon withphosphorus implantation was fabricated for gate electrode. A boron ion implantation for thresholdvoltages adjustment in a channel was implemented in order to match the threshold voltage of the NMOSand PMOS device. As a result, a surface channel and a buried channel were formed in NMOS andPMOS, respectively. Low energy implants are required to form shallow junctions self-aligned to thepoly gate. Phosphorus and BF 2 implants formed the lightly doped drain (LDD) of NMOS and PMOSstructure. Oxide sidewall spacers were used as an implant mass for the source/drain region self-alignedto the shallow LDDs. An SEM micrograph of the spacers is shown in Fig. 6. As and BF 2 wereimplemented to produce the NMOS and PMOS, respectively. The doping activation of the shallowsource/drain extensions was performed with a rapid thermal process. The wafers were heated to 900°Cfor 40 minutes in an N 2 ambient. In back end process, the oxide, SOG and oxide dielectric layer wasdeposited and reflowed at 750 o C. The contact windows were opened and Ti/TiN layer was depositedand followed by metal1, and TiN deposition and patterning. After an IMD layer was deposited followingby via, and windows were opened. The metal2 and TiN were deposited and patterned. The nextdeposition layer was nitride to act as a passivation layer. After passivation layer, the pad window wasopened for measurement (Ruangphanit, Phongphanchanthra, Meesapawong, Hruanan, Niemcharoen, &Muanghlua, 2007).119

Fig. 5 Simulated final CMOS Cross sectionFig. 6 Silicon dioxide sidewall spacerRESULTS AND DISCUSSIONTesting devices, shown in Fig. 7, on a test chip were measured and extracted. The dimensions of testingdevices in this figure were W/L= 40/40, 40/1.0, 40/0.8 and 1.2/40 respectively. Some performance suchas threshold voltage, saturation drain current, leakage current and punchthrough voltage weredetermined. All I-V characteristics measurements have been done at the room temperature. Themeasurement system is consisted of probe station Cascade ALESSI REL-6100 model, semiconductorparameter analyzer HP4156B, Precision LCR meter HP4184A, low leakage switch E5250A and ICSsoftware for measurement through PC computer as a controller. The device parameters with N-well doseof 3.6×10 12 cm -2 and VTA with dose of 9×10 11 cm -2 are illustrated in table1Table 1 Device parametersParameter NMOS PMOS UnitsThreshold Voltage 0.77 -0.68 VBody Factor 0.6 0.64 V 1/2Process Transconductance 74.6 26.3 µA/V 2Effective Channel Length 0.57 0.78 µmWidth Encroachment 0.18 0.2 µmPunchthrough Voltage 12 -13 VLeakage Current 1 1.5 pA/µmMaximum Drain Current 328 148 µA/µmField Oxide Threshold Voltage 10 -12 V120

Fig. 7 CMOS test chip layout design for electrical measurementsI DS(A)1E-31E-41E-51E-61E-71E-81E-91E-101E-111E-12V5.0 DS 0.1V DS5V.V DS4V.V DS3V.V DS2V.V DS1V.V DS0.1V.1E-130.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4V GS(V)V DS1E-31E-4-0.1 -5.01E-51E-6V DS5V.V DS4V.V DS3V.V DS2V.V DS1V.V DS0.1V.1E-71E-81E-91E-101E-111E-121E-13-1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0V GS(V)I DS(A)(a)(b)Fig. 8 Measured Log I DS &V GS with different V DS (1 V/step) of (a) NMOS and (b) PMOSFig. 8 shows the I DS &V GS characteristics of NMOS as the gate voltage V GS was swept from 0 V to 1.5 Vat different drain voltage V DS and grounded source and substrate together. The off stage current is inorder of pA/µm. The measured subthreshold swing is approximately 100mV/dec. The measured curveindicated that there was no punchthrough effect on testing devices. The punchthrough effect is measuredon I DS &V DS curve by sweeping the drain voltage from 0 V to 20 V. The punchthrough voltage obtainedat drain current of 1nA/µm (Cham & Chiang, 1984) is 12 V for NMOS and -13 V for PMOS. Fig. 9shows the I DS &V DS characteristics of NMOS. The saturation current per width of NMOS and PMOS is328 and 148 µA/µm, respectively. The DIBL effect is observed by a shift of threshold voltage as afunction of drain voltage. The threshold voltage measurement for testing devices was performed bymeasuring a set of I DS & V GS with increasing V DS value as a parameter. The gate voltage at the draincurrent of 0.1µA/µm is defined as the threshold voltage. The measured DIBL is 40 and 50 mV/V ofNMOS and PMOS, respectively. Since the PMOS was a buried channel transistor, their current wasmore leakage.121

1.4x10 -2 W/L=40/0.81.2x10 -2I DS(A)1.0x10 -28.0x10 -36.0x10 -34.0x10 -32.0x10 -30.00 1 2 3 4 5V DS(V)W/L =40/0.86.0x10 -35.0x10 -34.0x10 -33.0x10 -32.0x10 -31.0x10 -3I DS(A)-5 -4 -3 -2 -1 0V DS(V)0.0(a)(b)Fig. 9 Measured I DS &V DS with different V GS (0 → 5 V, 1 V/step) of (a) NMOS and (b) PMOSCONCLUSIONThe 0.8 µm CMOS technology fabrication has been designed and developed at Thai Micro electronicsCenter (TMEC). A single Voltage Threshold Adjust (VTA), Anti Punthrough (APT) process and n +polysilicon gate electrode are fabricated to minimize the complexity of fabrication process can beachieved. The I-V curve show that the MOSFET is a good turn off rate in subthreshold region and nopunchthrough problems. The surface DIBL investigation shows no surface leakage current.REFERENCESRuangphanit, A., Phongphanchanthra, N., Meesapawong, P., Hruanan, C., Niemcharoen, S., &Muanghlua, R. (2007). Device Design, Fabrication and Characterizations of 0.8 m CMOSTechnology. ECTI-CON 2007, I, pp. 137-140. Chiang Rai.Phongphanchanthra, N., Ruangphanit, A., Klunngien, N., Yamwong, W., Niemcharoen, S., &Khunkhao, S. (2008). Twin-Well 0.8 micron CMOS Technology Design and Simulation.Smartmat-'08, (p. 288). Chiang Mai.Wolf, S. (1995). The Submicron MOSFET. In Silicon Processing for VLSI Era (Vol. III, p. 208).California: Lattice Press.(1994). The National Technology Roadmap for Semiconductor. Semiconductor Industry Assoc., SanJose, CA.Wolf, S. (1995). The Submicron MOSFET. In Silicon Processing for the VLSI Era (Vol. III, p. 196).California: Lattice Press.Ruangphanit, A., Hansoongnoen, S., Phongphanchanthra, N., Meesapawong, P., & Muanghlua, R.(2007). Drain Induced Barrier Lowering for Submicrometer MOSFET from Process and DeviceSimulations. ANSCSE 11, (pp. 194-195). Phuket.Ruangphanit, A., Hansoongnoen, S., Phongphanchanthra, N., Klunngien, N., Niemcharoen, S., &Muanghlua, R. (2007). Drain Induced Barrier Lowering in Buried Channel PMOS Devices.MJISAT 2007, (pp. MJISAT-42). KL.Synopsys. (2007). Sentaurus TCAD User's Manual.122

Wolf, S. (1995). The Submicron MOSFET. In Silicon Processing for the VLSI Era (Vol. III, pp. 591-598). California: Lattice Press.Niemcharoen, S., Phongphachanthra, N., Ruangphanit, A., Klunngien, N., Meesapawong, P., &Sonboonton, R. (2007). The Study of Impact of LDD on Short Channel NMOS Performance.MJISAT 2007, (pp. MJISAT-91). KL.Wolf, S. (1995). The Submicron MOSFET. In Silicon Processing for VLSI Era (Vol. III, pp. 232-240).California: Lattice Press.Cham, K., & Chiang, S. (1984). Device Design for the Submicrometer P-channel FET with n+ Polisicongate. IEEE Tran. Electron Devices , ED-31, 964.123