MAXQ Core Assembly Guide - Maxim

MAXQ Core Assembly GuideName Conditions Function@BP[Offs++].B@BP[Offs++].W@BP[Offs++].LWrites or returns the value stored in memory location BP[Offs / Offs * 2 / Offs * 4], thenincrements Offs.DP[0] Data Pointer 0.@DP[0].B@DP[0].WReads from or writes to the memory location (byte / word / long) at DP[0].@DP[0].L@DP[0].B++@DP[0].W++Reads from or writes to the memory location at DP[0], then increments DP[0] by 1 (.B),@DP[0].L++2 (.W) or 4 (.L).@DP[0].B--@DP[0].W--@DP[0].L--Reads from or writes to memory location at DP[0], then decrements DP[0] by 1 (.B), 2(.W) or 4 (.L).DP[1] Data Pointer 1.@DP[1].B@DP[1].WReads from or writes to memory location (byte / word / long) at DP[1].@DP[1].L@DP[1].B++@DP[1].W++Reads from or writes to memory location at DP[1], then increments DP[1] by 1 (.B), 2@DP[1].L++(.W) or 4 (.L).@DP[1].B--@DP[1].W--@DP[1].L--Reads from or writes to memory location at DP[1], then decrements DP[1] by 1 (.B), 2(.W) or 4 (.L).Note that for registers with indexes such as the prefixes, accumulators, loop counters or data pointers, the indexmay be specified in any constant numeric format. So the eleventh accumulator may be referred to as A[10],A[0Ah], or even A[01010b].Predefined Register BitsAlthough registers in module 8 (AP, APC, PSF, IC, IMR, SC, IIR, IPR0, IPR1, CKCN and WDCN) are bitaddressable, names of the bits in these registers are not predefined in MaxQAsm. Except where these bits areexplicitly defined as part of an opcode (such as “move C, #0”), they must be referred to in terms of their parentregister.So while the Carry bit may be cleared by the instructionmove C, #0the Equal bit must be cleared by the instructionmove PSF.0, #0Version 1.2 14 of 43 March 7, 2007