Development of a Low Temperature N and P Type TFT's ... - LSI - USP

The polysilicon layers were deposited in a conventionalhot-wall LPCVD reactor. Silane was used for theundoped silicon film depositions. A mixture of silane andphosphine or diborane was used to obtain the in-situdoped N and P polysilicon layers [6] .A 150 nm thick amorphous silicon layer was depositedby LPCVD at a pressure and temperature of 90 Pa and550°C, respectively.(a)(b)(c)(d)(e)(f)(g)P + poly SiPPPS G Dundoped poly SiAPCVD gate silicon oxidealuminum electrodesisolation: SiO2S G DN + poly SiNNNglass substrateFigure 1: Low temperature N and P types TFT's fabricationprocess using LPCVD and SPC techniques. (a) APCVDsilicon oxide and poly-Si depositions and patterning;(b) silicon oxide P side isolation layer; (c) N+poly-Sideposition and patterning; (d) P+poly-Si deposition andpatterning; (e) source, gate and drain patterning; (f) gateoxide deposition, annealing and patterning; (g) aluminumdeposition, patterning and annealing.amorphous silicon films (undoped, N type and P type)structure were solid phase crystallized for 8 hours, at600°C and 10 -3 Pa.After SPC process, we performed the patterning of the Nand P type polysilicon layers to define the channel,source and drain regions (e). The samples were cleanedusing the standard RCA procedure followed by a dip indiluted HF, to prepare the surface of gate region toreceive the insulator layer. The gate insulator layer is anAPCVD silicon oxide film, 90 nm thick, deposited at450°C. This rather high thickness compared to theprevious studies was chosen to insure electrical results(mainly low leakage current) for the both transistor typesof this first run. This film was annealed in a conventionalfurnace, at 600°C in nitrogen ambient for 1 hour.The gate insulator layer was patterned and the source anddrain contact regions were opened using buffered oxideetch (BOE) solution (f).Then, a thermal evaporated aluminum layer, 300 nmthick, was deposited and patterned by wet etching toform the electrode contacts and interconnections. Finally,the aluminum layer was annealed, in forming-gas, at390°C, during 30 min (g).The electrical characteristics of the N and P type TFT’sNMOS and PMOS inverters were done using aHP 4155B parameter analyzer at room temperature.a. N Type TFT’s3. Experimental ResultsFigure 2 shows the transfer characteristics of the N typeTFT's, with width and length ratio (W/L) of60 µm/23 µm.The drain current, I DS , as a function of the gate voltage,V GS , was measured for drain voltage, V DS , of 1 V. TheON current, I ON , is due to drain current at a gate voltageof 25 V and the OFF current, I OFF , is the smallest draincurrent. The threshold voltage was measured by thelinear extrapolation on the gate voltage axis of the draincurrent versus the gate voltage I DS (V GS ) transfercharacteristics curve.Table 1 presents the values obtained by the thresholdvoltage (V T ), field effect mobility (µ N ), sub-thresholdslope (S) and I ON /I OFF ratio of the N type TFT.The undoped amorphous silicon film was patterned andplasma etched to define the active layer (a). We used aNextral NE 110 plasma etching system with SF 6 .An APCVD silicon oxide isolation layer, 250 nm thick,was deposited and patterned to protect the P side activeregion (b).An in-situ phosphorous doped layer, 150 nm thick, wasdeposited to form the N type TFT's (c). The samesequence was used to form the P type TFT's (d). These

Table 2: P type TFT’s properties extracted from thetransfer characteristics plots from Figure 3.V T (V) µ P (cm 2 /V.s) S I ON/OFF-13.5 32 -1.3 4 x 10 6Similarly to the N type TFT’s, the threshold voltage ofthe P type TFT's are higher than the expected one, due tothe thickness of the gate oxide, 90 nm.Figure 2: IDS-VGS characteristics of N type TFT's(W/L=60µm/23µm) with VDS of 1 V.Table 1: N channel TFT's properties extracted from thetransfer characteristics plots (Figure 2).V T (V) µ N (cm 2 /V.s) S I ON /I OFF9.6 40 1.3 3 x 10 6c. NMOS InvertersThe measured channel dimensions for the NMOS andPMOS inverters were W/L = 15 µm/30 µm andW/L = 12 µm/40 µm, for the load and drive TFT's,respectively.Figure 4 shows transfer characteristics of the NMOSinverters, with the power supply voltage (V DD ), as aparameter. The x-axis indicates the input voltage, V IN ,varied from 0 to 20 V and the y-axis indicates the outputvoltage, V OUT . The circuit configuration and definitionsof V IN , V OUT and V DD are shown in the figure.The high value of the threshold voltage obtained can bereduced using a thinner gate oxide [2,9] .b. P type TFT’sFigure 3 shows the transfer characteristics of the P typeTFT with width and length ratio (W/L) of 60 µm/23 µm.The drain current, I DS , as a function of the gate voltage,V GS , was measured for drain voltage, V DS, of -1 V. TheON current, I ON , due to the drain current at a gate voltageof -25 V and the OFF current, I OFF , is the smallest draincurrent. An I ON /I OFF ratio higher than 5 x10 6 is suitablefor several types of applications in electronic circuits.Table 2 present the values obtained to the thresholdvoltage (V T ), field effect mobility (µ N ), sub-thresholdslope (S) and I ON /I OFF ratio of the P type TFT.Figure 4: Transfer characteristics of NMOS inverters. TheTFT’s dimensions were W/L LOAD = 15 µm/30 µm andW/L DRIVE = 12 µm/40 µm.Table 3 shows the inverters properties values extractedfrom Figure 4.Table 3: Output voltage amplitude and gain of the NMOSinverters.NMOS TFT's V DD = 20V V DD = 30VAmplitude (V) 10 V 16.5 VS 1.4 1.7Figure 3: I DS -V GS characteristics of P type TFT's with V DS asa parameter.To V DD = 20 V, the V OUT value is 11 V to V IN = 0 V, andV OUT is 1 V to V IN = 20 V. It means that the outputvoltage amplitude is 10 V or 50 % of the applied voltageand from the V DD of 30 V, the output voltage amplitudeis 16.5 V or 55 %.

The inverters have a practically full rail-to-rail swing,and a well-defined voltage transfer characteristics. Thegain presented in Table 3 was measured from the slope ofthe voltage transfer curve in the transition region.Due to the high absolute value of threshold voltages ofthe TFT’s, the slopes of the transfer characteristics plotare lower than expected.d. PMOS InvertersFigure 5 shows the transfer characteristics of the PMOSinverters, with the power supply voltage V SS , as aparameter. The input voltage, V IN , varies from 0 to -25 Vand is plotted in function of the output voltage, V OUT .The circuit configuration and definitions of V IN , V OUTand V SS are shown in the figure.To V SS = -20 V, the V OUT value is -7 V to V IN = 0 V, andV OUT is 1 V to V IN = 20 V, which indicates that theoutput voltage amplitude is 6.5 V or 32.5 % of theapplied voltage and from the V SS of -30 V, the outputvoltage amplitude is 13.5 V or 45 %.N and P type TFT's through the use of in situ dopedsource and drain polysilicon films. The first run wasprocessed on a silicon substrate with a depositedAPCVD oxide in order to get the same physicalconditions than a glass one. The electricalcharacterizations show the possibility to get N-type andP-type inverters. The transfer characteristics, showed inthis paper, are not so good as expected than expected.This is due to the absolute value of the threshold voltagesof the both transistor types that are presently too high.This can be explained by the absence of optimization ofthe gate oxide, especially the thickness, which should bedone. A new 6-mask process is currently in progress tofabricate basic electrical circuits on glass substrate.Notice that this technology is solid phase crystallizationbased, that means no temperature higher than 600°C,even during crystallization step and as publishedpreviously, presents a very high potentialreproducibility [2,7] .AcknowledgmentsThe authors are grateful to Ph. Cullerier and R. Rogel,for polycrystalline silicon deposition and for their help inthe fabrication process. The authors want also to thankDr. Y. Helen and Prof. T. Mohammed-Brahim for helpfuldiscussions and advice about the fabrication process.Financial support from CNRS, ALFA program, FAPESP,CAPES/COFECUB, CNPq and FINEP are gratefullyacknowledged.ReferencesFigure 5: Transfer characteristics of PMOS inverters. TheTFT’s dimensions were W/L LOAD = 15 µm/30 µm andW/L DRIVE = 12 µm/40 µm.Table 4 presents the amplitude and the subtreshold slopeextracted from Figure 5.Table 4: Output voltage amplitude and gain of the PMOSinverters.PMOS TFT's V SS = -20V V SS = -30VAmplitude (V) 6.5 V 13.5 VS -1.2 -2.0Let us notice that we observed the similar behavior to theN type inverters.4. Discussion and ConclusionWe have developed a low temperature process (< 600°C)to fabricate simultaneously, on the same glass substrate,[1] C. T. Angelis, C. A. Dimitriadis, M. Miyasaka, F. V.Farmakis, G. Kamarinos, J. Brini, J. Stoemenos, " Effect ofexcimer laser annealing on the structural and electricalproperties of polycrystalline silicon thin-film transistors".Journal of applied physics, vol. 86, n.8, October, 1999,pp. 4600-4606.[2] K. Mourgues, F. Raoult, T. Mohammed-Brahim, D. Briand,O. Bonnaud, "Performance of thin film transistors onunhydrogenated in-situ doped polysilicon films obtainedby solid phase crystallization", Mat. Res. Soc. Symp. Proc.,vol. 471, 1997, pp. 155-160.[3] K. J. Nieuwesteeg, A. H. van Ommen, "AM-LCD's bringsolid-state devices to the display". Proceedings of the 27thEuropean Solid-State Device Research Conference,ESSDERC'97, Stuttgart, Germany, 22-24 Sept, pp. 88-100,1997.[4] S. D. Brotherton, J. R. Ayres, M. J. Edwards, C. A. Fisher,C. Glaiser, J. P. Gowers, D. J. McCulloch, M. Trainor"Laser crystallized poly-Si TFT's for AMLCD's". ThinFilms for Large Area Electronics, European MaterialsResearch Society, E-MRS, Thin Solid Films, SymposiaProceedings, vol. 80, pp. 188-195, 1999.

[5] S. Chopra, R. S. Gupta, " Subthreshold conduction inshort-channel polycrystalline-silicon thin-film transistors".Semicond. Sci. Technol, vol. 15, pp. 197–202, 2000.[6] D. Briand, M. Sarret, P. Duverneuil, T.Mohammed-Brahim and K. Kis-Sion, "Influence of thedoping gas on the axial uniformity of the growth rate andthe electrical properties of LPCVD in-situ dopedpolysilicon layers", J. Phys. IV, vol. 5, pp. 887, 1995.[7] A. Rahal, T. Mohammed-Brahim, H. Toutah, B. Tala-Ighil,Y. Helen, C. Prat, F. Raoult, "Ageing of laser crystallizedand Unhydrogenated polysilicon thin film transistors".Elsevier Science, Microelectronics Reliability, vol. 39,pp. 851-855, 1999.[8] O. Bonnaud, "Polycrystalline silicon thin film transistors:state of the art and improvement of electricalcharacteristics". Solid state Phenomena, vol. 67-68,pp. 529-540, Scitec Publications, Switzerland, 1999.[9] Y. Helen, R. Dassow, K. Mourgues, O. Bonnaud, T.Mohammed-Brahim, F. Raoult, J. R. Koehler, J. H.Werner, D. Lemoine, "Reproducible high field effectmobility polysilicon thin film transistors involving pulsedNd:YVO 4 laser crystallization". IEDM, InternationalElectron Devices Meeting 1999, Washington D. C.,pp. 297, 1999.