Scalable RTL in Design and Verification
Scalable RTL in Design and Verification
Scalable RTL in Design and Verification
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Prior <strong>Design</strong> Work<strong>Verification</strong> Hardships• Deep design state• Large testbench snapshots– Slower– Many testbenches do not fit <strong>in</strong> 32-bit simulators• Inefficient accelerator usage– Large buffers use up expensive space– Many testbenches do not fit <strong>in</strong>to box<strong>Scalable</strong> <strong>RTL</strong> <strong>in</strong> <strong>Design</strong> <strong>and</strong> <strong>Verification</strong> 9/17/2007 Page 6