Scalable RTL in Design and Verification

Scalable RTL in Design and Verification Scalable RTL in Design and Verification

12.07.2015 Views

Prior Design WorkCM CM CMRU RU RUIMIUPUPMImplementation andVerification StrategiesIMIMIUIUXBUPUPUPMPM• Quick unit development– Verification advantages– Physical advantagesKeyIM- I/O ModelCM- Common ModelPM- Processor ModelMM- Memory ModelRU- Remote UnitMU- Memory UnitPU- Processor UnitXBU- Crossbar UnitMU MU MUMM MM MM• Limited model developmentCM• Workhorse unit testbenches• System testbenchesCMPUPM• Formal usage• Fully synthesizabletestbenchesXBUCMKeyCM- Common ModelPM- Processor ModelPU- Processor UnitXBU- Crossbar UnitCMScalable RTL in Design and Verification 9/17/2007 Page 4

Prior Design WorkRN RN RNRU RU RUI/OIUPUPDetailed DescriptionI/OIUXBUPUP• FIFOsI/OIUPUP• Trackers• CountersKeyI/O- I/O BridgeRN- Remote NodeM- MemoryP- ProcessorIU- I/O UnitRU- Remote UnitMU- Memory UnitPU- Processor UnitXBU- Crossbar UnitMU MU MUM M MI/O IU MU M PU PKeyI/O- I/O BridgeIU- I/O UnitMU- Memory UnitM- MemoryPU- Processor UnitP- ProcessorScalable RTL in Design and Verification 9/17/2007 Page 5

Prior <strong>Design</strong> WorkRN RN RNRU RU RUI/OIUPUPDetailed DescriptionI/OIUXBUPUP• FIFOsI/OIUPUP• Trackers• CountersKeyI/O- I/O BridgeRN- Remote NodeM- MemoryP- ProcessorIU- I/O UnitRU- Remote UnitMU- Memory UnitPU- Processor UnitXBU- Crossbar UnitMU MU MUM M MI/O IU MU M PU PKeyI/O- I/O BridgeIU- I/O UnitMU- Memory UnitM- MemoryPU- Processor UnitP- Processor<strong>Scalable</strong> <strong>RTL</strong> <strong>in</strong> <strong>Design</strong> <strong>and</strong> <strong>Verification</strong> 9/17/2007 Page 5

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