Scalable RTL in Design and Verification
Scalable RTL in Design and Verification Scalable RTL in Design and Verification
IntroductionOverview• Prior Design Work• Current and Future Design Work• Application of Scalable RTL Strategy• Results• ConclusionsScalable RTL in Design and Verification 9/17/2007 Page 2
MMMMMMPrior Design WorkI/OI/ONCPPI/OI/ONCPPGeneral DescriptionKeyNC- Node ControllerM- MemoryI/O- I/O BridgeP- ProcessorI/OI/OPPI/OI/OPP• Scalable ServersI/ONCPI/ONCP• Node Controller ASICs– Processor Interfaces– Memory Interfaces– I/O Interfaces– Scale-up Interfaces– CrossbarI/OMI/OI/OMMIUIUPI/OMRN RN RNRU RU RUXBUMPUPUMPPPI/OIUPUPKeyI/O- I/O BridgeRN- Remote NodeM- MemoryP- ProcessorIU- I/O UnitRU- Remote UnitMU- Memory UnitPU- Processor UnitXBU- Crossbar UnitMU MU MUM M MScalable RTL in Design and Verification 9/17/2007 Page 3
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- Page 7 and 8: Prior Design WorkPhysical Design Ha
- Page 9 and 10: Current & Future DesignsValid1 Pack
- Page 11 and 12: Application of Scalable RTL Strateg
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- Page 17 and 18: ResultsImplementation• 19 logical
- Page 19 and 20: ResultsVerification• More focused
- Page 21 and 22: ResultsFormal Analysis• More typi
- Page 23 and 24: ConclusionsIntroducing RTL Scalabil
MMMMMMPrior <strong>Design</strong> WorkI/OI/ONCPPI/OI/ONCPPGeneral DescriptionKeyNC- Node ControllerM- MemoryI/O- I/O BridgeP- ProcessorI/OI/OPPI/OI/OPP• <strong>Scalable</strong> ServersI/ONCPI/ONCP• Node Controller ASICs– Processor Interfaces– Memory Interfaces– I/O Interfaces– Scale-up Interfaces– CrossbarI/OMI/OI/OMMIUIUPI/OMRN RN RNRU RU RUXBUMPUPUMPPPI/OIUPUPKeyI/O- I/O BridgeRN- Remote NodeM- MemoryP- ProcessorIU- I/O UnitRU- Remote UnitMU- Memory UnitPU- Processor UnitXBU- Crossbar UnitMU MU MUM M M<strong>Scalable</strong> <strong>RTL</strong> <strong>in</strong> <strong>Design</strong> <strong>and</strong> <strong>Verification</strong> 9/17/2007 Page 3
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