Scalable RTL in Design and Verification

Scalable RTL in Design and Verification Scalable RTL in Design and Verification

12.07.2015 Views

ResultsPhysical• Easier integration of architectural changes– Adapting to fluctuating buffer size requirements– Adjusting interfaces to alleviate routing congestion– Resizing structures as performance considerations arerevisited• Changes made with confidence because of previousverification of scaled versions• Physical memory flexibility allowed for easy exploration ofbuffer structure trade-offsScalable RTL in Design and Verification 9/17/2007 Page 18

ResultsVerification• More focused verification– Smaller sizes used when targeting boundary condition logic– Specified sizes used when targeting throughput andbandwidth functioning• Large testbenches able to fit in more simulators• More effective use of accelerator• More design blocks made tractable for formal analysisScalable RTL in Design and Verification 9/17/2007 Page 19

Results<strong>Verification</strong>• More focused verification– Smaller sizes used when target<strong>in</strong>g boundary condition logic– Specified sizes used when target<strong>in</strong>g throughput <strong>and</strong>b<strong>and</strong>width function<strong>in</strong>g• Large testbenches able to fit <strong>in</strong> more simulators• More effective use of accelerator• More design blocks made tractable for formal analysis<strong>Scalable</strong> <strong>RTL</strong> <strong>in</strong> <strong>Design</strong> <strong>and</strong> <strong>Verification</strong> 9/17/2007 Page 19

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