Scalable RTL in Design and Verification
Scalable RTL in Design and Verification
Scalable RTL in Design and Verification
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ResultsPhysical• Easier <strong>in</strong>tegration of architectural changes– Adapt<strong>in</strong>g to fluctuat<strong>in</strong>g buffer size requirements– Adjust<strong>in</strong>g <strong>in</strong>terfaces to alleviate rout<strong>in</strong>g congestion– Resiz<strong>in</strong>g structures as performance considerations arerevisited• Changes made with confidence because of previousverification of scaled versions• Physical memory flexibility allowed for easy exploration ofbuffer structure trade-offs<strong>Scalable</strong> <strong>RTL</strong> <strong>in</strong> <strong>Design</strong> <strong>and</strong> <strong>Verification</strong> 9/17/2007 Page 18
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