Scalable RTL in Design and Verification
Scalable RTL in Design and Verification
Scalable RTL in Design and Verification
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ResultsImplementation• 19 logical buffers madescalable• 7 of 14 output transactionbuffers <strong>and</strong> <strong>in</strong>terfaces couldbe entirely removed based ona parameterOutputOutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactionsTransactions...RetransmissionMessag<strong>in</strong>gInitializationMessag<strong>in</strong>gInputTransactions InputTransactions InputTransactionsInputTransactions2• Adjustable packet counts onevery <strong>in</strong>terface222Physical LayerDecode• Selectable physical memorycounts of logical buffers<strong>Scalable</strong> <strong>RTL</strong> <strong>in</strong> <strong>Design</strong> <strong>and</strong> <strong>Verification</strong> 9/17/2007 Page 17
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