Scalable RTL in Design and Verification

Scalable RTL in Design and VerificationRoss Weber

IntroductionOverview• Prior Design Work• Current and Future Design Work• Application of Scalable RTL Strategy• Results• ConclusionsScalable RTL in Design and Verification 9/17/2007 Page 2

MMMMMMPrior Design WorkI/OI/ONCPPI/OI/ONCPPGeneral DescriptionKeyNC- Node ControllerM- MemoryI/O- I/O BridgeP- ProcessorI/OI/OPPI/OI/OPP• Scalable ServersI/ONCPI/ONCP• Node Controller ASICs– Processor Interfaces– Memory Interfaces– I/O Interfaces– Scale-up Interfaces– CrossbarI/OMI/OI/OMMIUIUPI/OMRN RN RNRU RU RUXBUMPUPUMPPPI/OIUPUPKeyI/O- I/O BridgeRN- Remote NodeM- MemoryP- ProcessorIU- I/O UnitRU- Remote UnitMU- Memory UnitPU- Processor UnitXBU- Crossbar UnitMU MU MUM M MScalable RTL in Design and Verification 9/17/2007 Page 3

Prior Design WorkCM CM CMRU RU RUIMIUPUPMImplementation andVerification StrategiesIMIMIUIUXBUPUPUPMPM• Quick unit development– Verification advantages– Physical advantagesKeyIM- I/O ModelCM- Common ModelPM- Processor ModelMM- Memory ModelRU- Remote UnitMU- Memory UnitPU- Processor UnitXBU- Crossbar UnitMU MU MUMM MM MM• Limited model developmentCM• Workhorse unit testbenches• System testbenchesCMPUPM• Formal usage• Fully synthesizabletestbenchesXBUCMKeyCM- Common ModelPM- Processor ModelPU- Processor UnitXBU- Crossbar UnitCMScalable RTL in Design and Verification 9/17/2007 Page 4

Prior Design WorkRN RN RNRU RU RUI/OIUPUPDetailed DescriptionI/OIUXBUPUP• FIFOsI/OIUPUP• Trackers• CountersKeyI/O- I/O BridgeRN- Remote NodeM- MemoryP- ProcessorIU- I/O UnitRU- Remote UnitMU- Memory UnitPU- Processor UnitXBU- Crossbar UnitMU MU MUM M MI/O IU MU M PU PKeyI/O- I/O BridgeIU- I/O UnitMU- Memory UnitM- MemoryPU- Processor UnitP- ProcessorScalable RTL in Design and Verification 9/17/2007 Page 5

Prior Design WorkVerification Hardships• Deep design state• Large testbench snapshots– Slower– Many testbenches do not fit in 32-bit simulators• Inefficient accelerator usage– Large buffers use up expensive space– Many testbenches do not fit into boxScalable RTL in Design and Verification 9/17/2007 Page 6

Prior Design WorkPhysical Design Hardships• Early sizing estimates not accurate• Design reductions needed– Large structures shrunk– Features removed– Bugs introduced• Parameterization– Reductions made easier– Incomplete– Unverified– Limited usageScalable RTL in Design and Verification 9/17/2007 Page 7

Current & Future DesignsGeneral DescriptionRNRNRN• New Processor and I/Ointerfaces• Common protocol• More crossbars• Focus on CIU designKeyCIU- Common InterfaceUnitPTU- ProcessorTransaction UnitITU- I/O Transaction UnitIXBU- I/O Crossbar UnitPXBU- Processor CrossbarUnitI/O- I/O BridgeRN- Remote NodeM- MemoryP- ProcessorIU- I/O UnitRU- Remote UnitMU- Memory UnitPU- Processor UnitXBU- Crossbar UnitI/OI/OI/OCIUCIUCIUIXBUITUITUITURU RU RUXBUPTUPTUPTUPXBUCIUCIUCIUPPPMU MU MUM M MScalable RTL in Design and Verification 9/17/2007 Page 8

Current & Future DesignsValid1 PacketCredit1 PacketCredit1 PacketCreditValid1 PacketCredit4 PacketsCredit4 PacketsCredit3 PacketsCredit1 PacketReady1 PacketReady2 PacketsReady7 PacketsReadyFocus BlockDescription• Physical layer• Link layer– Initialization– RetransmissionOutputOutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactionsTransactionsInputTransactions InputTransactions InputTransactionsInputTransactions• Buffering andflow control22RetransmissionMessaging2InitializationMessaging2DecodePhysical Layer2 Packets2 PacketsValidValidValidsValidsValidsValid1 PacketCreditValid1 PacketCreditValid1 PacketCreditValid1 PacketCreditValids4 PacketsCreditValids4 PacketsCreditValids3 PacketsCreditScalable RTL in Design and Verification 9/17/2007 Page 9

Application of Scalable RTL StrategyFocus Block• Input and output transaction buffers• Retry buffer• Interface counts• Packet counts on interfacesScalable RTL in Design and Verification 9/17/2007 Page 10

Application of Scalable RTL StrategyImplementation• New skills needed for some designers• Designers need to generalize specification instead ofimplementing in a straight-forward manner• FIFO exampleScalable RTL in Design and Verification 9/17/2007 Page 11

Application of Scalable RTL StrategyLanguage Constructs• For loops• Index part-select• Multidimensional nets• Generate blocks• Constant functionsScalable RTL in Design and Verification 9/17/2007 Page 12

Application of Scalable RTL StrategyLanguage Constructs• For loops• Multidimensional nets• Constant functions• Index part-select• Generate blocksScalable RTL in Design and Verification 9/17/2007 Page 13

Application of Scalable RTL StrategyFormal Analysis• Scalability enables more formal analysis• Significant advantages of formal over simulation– Exhaustive– Easier testbench creation• Clocks• No RNGs needed• Assumptions as drivers– Locates bugs difficult or impossible for simulation• Focus block is a good candidateScalable RTL in Design and Verification 9/17/2007 Page 14

Application of Scalable RTL StrategyImplementation Hardships• Changing a designer’s coding style• Readability• Not a straight-forward implementation of specification• Longer code entry time prolongs unit verification start timeScalable RTL in Design and Verification 9/17/2007 Page 15

Application of Scalable RTL StrategyVerification Hardships• Generalized names causemisunderstandings• Procedural code harder todebug• Early deep formal analysisaffects scheduleScalable RTL in Design and Verification 9/17/2007 Page 16

ResultsImplementation• 19 logical buffers madescalable• 7 of 14 output transactionbuffers and interfaces couldbe entirely removed based ona parameterOutputOutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactions OutputTransactionsTransactions...RetransmissionMessagingInitializationMessagingInputTransactions InputTransactions InputTransactionsInputTransactions2• Adjustable packet counts onevery interface222Physical LayerDecode• Selectable physical memorycounts of logical buffersScalable RTL in Design and Verification 9/17/2007 Page 17

ResultsPhysical• Easier integration of architectural changes– Adapting to fluctuating buffer size requirements– Adjusting interfaces to alleviate routing congestion– Resizing structures as performance considerations arerevisited• Changes made with confidence because of previousverification of scaled versions• Physical memory flexibility allowed for easy exploration ofbuffer structure trade-offsScalable RTL in Design and Verification 9/17/2007 Page 18

ResultsVerification• More focused verification– Smaller sizes used when targeting boundary condition logic– Specified sizes used when targeting throughput andbandwidth functioning• Large testbenches able to fit in more simulators• More effective use of accelerator• More design blocks made tractable for formal analysisScalable RTL in Design and Verification 9/17/2007 Page 19

ResultsFormal Analysis• Small baseline exampleproves quickly• Increasing depth, width, ornumber of ports increasesproof time• Depth most significantlyaffects “state explosion”Scalable RTL in Design and Verification 9/17/2007 Page 20

ResultsFormal Analysis• More typical FIFO sizes are32, 64, or 128• Many properties andsequences still completequickly• End-to-end properties needscalabilityScalable RTL in Design and Verification 9/17/2007 Page 21

ResultsVerification• Scaling can cause coverage to not be hit• Highlights importance of pairing coverage sequences with designproperties in verification plan• Example below shows a coverage problem in IFV when the FIFOdepth parameter was set less than the number of write portsparameterScalable RTL in Design and Verification 9/17/2007 Page 22

ConclusionsIntroducing RTL Scalability• Combined implementation and verification strategy needed• Learning curve• Robust design• Tool, training, and methodology advancements needed• Appropriate timing of formal analysis application isnecessary• Proceed with cautionScalable RTL in Design and Verification 9/17/2007 Page 23

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