ASIC Design Flow State-of-the-Art

State-of-the-ArtASIC Design Flowpart 2David SmolaVladimír StrakošSCG Czech Design Center

Goals of this presentation:• to understand what “ASIC” means• to understand how an ASIC is developedidea… …chip realization… …chip applicationOUTLINE:IntroductionASIC design flowASIC design exampleConclusion

OUTLINE: IntroductionASIC design flowASIC design exampleConclusionIntroductionWhat is “ASIC”?Application Specific Integrated Circuit?

IntroductionASIC is actually an integrated circuit (IC),so let’s talk about it’s history a bit…Introduction - historyIBM 1996, 180 000transistors, few grams,70mm 2 , 200mWENIAC 1946, 17 500vacuum tubes, 27 tons,167m 2 , 150kW50years

Introduction – key milestonesThe first transistor: 1947John BardeenWalter BrattainWilliam ShockleyIntroduction – key milestonesIntegrated circuit invention:Geoffrey DummerIn1952camewithanideato fabricate multiple circuitsin one substrate.Jack KilbyIn February 1959 he appliedfor a patent for actually thefirst integrated circuit.Robert NoyceIn April 1961 he was awardeda patent for the first multitransistorintegrated circuit.

Introduction – key milestonesThe first IC: 1959One transistor and few passive components on ONE Germaniumsubstrate. The first usage was in military application.Ref: Texas InstrumentsIntroductionWhy are actually nowadays ASICs widely used in highlyspecialized applications as well as in mass production?Let’s demonstrate the benefits of ASIC’s

Introduction – exampleExample: we want to implement a battery control system17V 12VBlackboxIntroduction – exampleMethod #1:Implement the function with passive componentsmanysupportingdevicescomparator

Introduction – exampleMethod #2:Implement the function with an ASICfewsupportingdevicesASICIntroduction – exampleWhat method is more perspective for a customer in thefollowing cases:10 FUNCTIONAL CIRCUITS10 000 000 FUNCTIONAL CIRCUITS? ? ? ? ? ? ? ?? ? ? ?

Introduction – exampleMethod #1: suppose we use one IC for 1$, 5 caps for 0.5$,LM317 for 1$ and PCB for 3$ total =7.5$ per 1PCB-10 FUNCTIONAL CIRCUITS: 75$-10 000 000 FUNCTIONAL CIRCUITS: 75Mil $Method #2: suppose the design work expenses are 1Mil $,1 set of masks for chip manufacturing 1Mil $, testinginstruments 1Mil $ total = 3Mil $ per 1 designed ASICs-10 FUNCTIONAL CIRCUITS: 3Mil $-10 000 000 FUNCTIONAL CIRCUITS: 3Mil +/- 3Mil $General advantage of ASICs: much cheaperfor a mass productionIntroduction – exampleASIC circuits in highly specialized fields of engineering:In all these fields there is just “few”IC’s needed, but very advanced,robust and immune.

Introduction – advantagesAdvantages of ASICs:• An ASIC solution gives better functionality and betterperformance than a corresponding discrete solution,especially for systems requiring low power consumption.• The weight and volume of the final product are oftenreduced significantly with ASICs.• An ASIC solution means perfect product economy if theproduct is manufactured in a given minimum volume.• An ASIC provides excellent protection against copying ofa product….Introduction – applicationsWhere do we use ASIC’s?In any field of nowadays human activity you can think of:• Any industry• Ecology• Aeronautics• Astronomy• Medical• Militaryetc…

OUTLINE:IntroductionASIC design flowASIC design exampleConclusionASIC design flow• When talking about ASICs, we talk aboutdigital or mixed-mode integrated circuits• The following part will show steps that are followed duringdesign of an ASIC in AMIS: from initial contact with thecustomer to release of the product into production

ASIC design flowProductphasesoverview:PreStudy startProduct phases overview:Phase 0 – feasibility and quotingPhase 1 – PreStudyPhase 2 – developmentPhase 3 – Limited productionPreStudy endProject plan specifiedDesign startDesign Tape OutTesting prototypesCustomer prototype approvalLimited transfer to productionASIC design flow – Phase 0Phase 0 – feasibility and quotingCustomer expectations enter the appropriatebusiness unit through the Sales DepartmentThe goal:• to evaluate commercial interest of the project• to evaluate the technical feasibility, which• means technology capability, library availability,• test capability, CAD tool, human resources (all• by system architect)• to determine the need for ESD testing

ASIC design flow – Phase 1Phase 1 – PreStudyCustomer design requirements are analysed indetail. Preliminary design activity starts in orderto arrive at Project SpecificationsThe goal:• to construct a Project Plan• to start a hybrid design (behavioural modelling)• to identify the complete design team members• to sign the Project Specifications and Test• Plan by both customer and the ASIC developerASIC design flow – Phase 1Quality level:• determined at the end of prestudyQuality level measures:• ppm400… consumer electronics, telecom(commercial), industrial, computer peripherals

ASIC design flow – Phase 2Phase 2 – DevelopmentThe Product Specifications must be signedbefore entering this phase. Practical designingof the ASICThe goal:• to execute design and layout tasks to fulfilparameters according to the Product Specifications• to manufacture the prototype and to test it• to receive customer’s prototype approvalASIC design flow – Phase 2Actual chip designTOP-DOWNTop-level schematic isconstructed beforeindividual cells aredesigned. Behaviouralmodels of cells are usedBOTTOM-UPThe individual cell aredesigned at the transistorlevel before or in parallelwith the construction oftop-level schematic•Top-down design methodology is preferred whenever practical

ASIC design flow – Phase 2Top-down development sub-phases:• Chip level design• Cell / block design• Cell layout• Chip-level layout• Chip-level post-layout• Tech transfer• Fabrication and characterisation• Product reliability qualification• Transfer to productionChip level designCell/block designCell layoutChip-level layoutChip-level post-layoutTech transferFab,characterisationProduct reliability q.Limited transfer to pr.ASIC design flow – Phase 2Chip level designChip level designCell/block design12V 3V 1.2VREGBGrefBUSCell layoutChip-level layoutChip-level post-layoutsensor 1OAanalogMemory bankdigitalTech transferFab,characterisationrefOAADCCProduct reliability q.Limited transfer to pr.sensor 2OAOSCref• includes top-level floor-planning and top-level simulations

ASIC design flow – Phase 2Cell / block designanalogdigitalChip level designCell/block designCell layoutChip-level layoutChip-level post-layoutTech transferFab,characterisationProduct reliability q.Limited transfer to pr.OA• Manual circuit design• Schematic creationC• Logic synthesis• Logic simulation• Automated / manualschematic creation• Schematic simulation• Schematic simulationASIC design flow – Phase 2Manual analog cell / block designAnalog blockOpAmpCircuit topologyOA2-stage folded cascode OpAmpDevice parameters2-stage folded cascode OpAmpSystem-level kind ofspecifications:WL = 100.5- DC gain- unity gain frequency- supply voltage- maximal powerconsumption- noise specifications- THD specificationsAppropriate circuittopology selectionDevice sizingoptimisation, biasingcurrents setting,threshold voltagessettingSimulations(DC, TR, AC, Noise)iterativeprocessesCorner simulations(slow, fast, high/low temp)Verified schematic

ASIC design flow – Phase 2Cell / block layout – analog or digital• Manual or automatedlayout designChip level designCell/block designCell layoutChip-level layoutChip-level post-layout• Parasitic extractionTech transferFab,characterisationProduct reliability q.Limited transfer to pr.• schematic update,simulation withparasitic devices• LVS, DRCASIC design flow – Phase 2LVS – Layout Versus Schematic• Device count and device sizes must equal

ASIC design flow – Phase 2DRC – Design Rule Check• layouted devices and metalor silicon tracks must musthave allowed dimensions,overlapping and spacingASIC design flow – Phase 2Chip-level layout• Completion of the chip from cells/blocks into a top-level systemChip level designCell/block designCell layoutChip-level layoutChip-level post-layoutTech transferFab,characterisationProduct reliability q.Limited transfer to pr.• Parasitic extraction, update, simulation with parasitic devices• LVS, DRC

ASIC design flow – Phase 2Chip-level post-layout• Bonding diagram creationChip level designCell/block designCell layoutChip-level layoutChip-level post-layoutTech transferFab,characterisationProduct reliability q.Limited transfer to pr.• Where applicable, DRCASIC design flow – Phase 2Tech transfer• Generating reticle informationChip level designCell/block designCell layoutChip-level layoutChip-level post-layoutTech transferFab,characterisation• Creating masks for lithographyProduct reliability q.Limited transfer to pr.

ASIC design flow – Phase 2FabricationChip level designCell/block designCell layoutChip-level layout• Wafer fabricationChip-level post-layoutTech transferFab,characterisation• PackagingProduct reliability q.Limited transfer to pr.ASIC design flow – Phase 2Testing, characterisation• Prototype evaluation and characterisationChip level designCell/block designCell layoutChip-level layoutChip-level post-layoutTech transferFab,characterisationProduct reliability q.Limited transfer to pr.

ASIC design flow – Phase 2Product reliability qualification• ESD and latch-up testingChip level designCell/block designCell layoutChip-level layoutChip-level post-layoutTech transferFab,characterisationOBR. ESD testingProduct reliability q.Limited transfer to pr.• Life-time testing(baking, freezing, moisturizing, pressurizing)ASIC design flow – Phase 2Limited transfer to production• Customer prototype approvalChip level designCell/block design• Direction into Phase 3 – prototype readyCell layoutChip-level layoutChip-level post-layoutTech transferFab,characterisationProduct reliability q.Limited transfer to pr.

OUTLINE:IntroductionASIC design flowASIC design exampleConclusionASIC design examplesASIC examples fullydeveloped at AMIS, Brno

ASIC design example #1System for ADAPTIVE LIGHTINGSystem description:shifting lights to either side of the driving directionso that the light beam direction is adapted asneeded during driving.ASIC function:• angular position control of a stepper motor• communication with controller and sensors viabusASIC design example #1The principle of adaptive lighting:non-adaptedlight beamadaptedlight beamdriving direction

ASIC design example #1The adaptive light bulb with a stepper motor:ASIC design example #1The sensors:drivingdirectionsensorambientlightsensor

ASIC design example #1• The IC represents sophisticated systemcontaining sensors interface, analog andsignal processing, bus communicationinterface and supporting functions.So, what is really hidden behind the words?ASIC design example #1ASIC system schematic:PWIN/sleepLINLINtransceiverPosition controllerDecoderPWMregulatorXMOTXPMOTXNHW[2:0]TSTLIN slavecontrollerSynchronousI/O controller(test)Main control&RegistersOTP + ROMSinewavetableDACsPWMregulatorYMOTYPMOTYNVBATVDDVoltageregulatorOscillatorCharge pumpReference voltage&Thermal monitoringVCPCPN CPP

ASIC design example #1ASIC connection:HALL sensing with PWM output1HW0PWMIN202HW1VBAT19C1 100nFC5 1µF+3VDDMOTXP18tantalumC6 100nF4GNDGND 175TSTMOTXN 16LIN busESDR2 1kAdr Connector678LINGNDHW2MOTYP 15GND 14MOTYN 13C2 100nFD1BatteryC8 2.7nFC4 220nF9 CPN10 CPPVBAT 12VCP 11C3 220nF+C0 100µFASIC design example #1Design challenges of this ASIC:• controlling quite high currents• motor microstepping via PWM• handling error conditions• automotive requirements (strict ESD,EMC, EMI, temperature and vibrationconditions)

ASIC design example #1Example summary:• Challenging analog design• Now in production.ASIC design example #2Integrated system for SMART PARKINGSystem description:warning of the driver for any obstacle in theclosest vicinity of a car when driving back or forth.ASIC function:• driving/reading piezo-element• regulation of the ultra-sound level• communication via bus with the control unit

ASIC design example #2… the aim of designers is to reduce accidents …ASIC design example #2Basic principle:VBATTrafoPiezoOBSTACLEIOASICGND

ASIC design example #2ASIC systemschematic:R11000.33WST1D1BAS321C1330pFCdd168uF35V9: VDDCdd222nFCdda1uFCref1uFTrn=7.612: NC 11: VDDA 14: VREF 13: NCCcl1n55: OUT2Rfb16k8Rfb2560L1ACB2012M_0407: OUT1PiezoST4ST5Rio310kVoltageRegulatorsOscillator307.2 kHzFrequencyDividerAmplitudeRegulationTransmitPowerStage1: NC24: NC6: VSSE4: FBST2Rio147Rio21kCio330p10: IO18: Testout1+–LogicSlopeControlVrefFosc&+–2: TestioTESTS17: TestinEEEEPROM16: TestioEEThreshold– Vref+40kD/A15: S–+Vref23: INCs4n780pF8: VSSD3: Testin19: V320: V2 21: V1 22: VSSAST3Rbp1330kCbp1100pCbp2100pRre32.87kRre2220kRre112kCre330pASIC design example #2Safe parking system in a car

ASIC design example #2• example of an ideal usage case:http://www.leftlanenews.com/2006/02/17/video-bmws-automatic-parking-system/ASIC design example #2Design challenges of this ASIC:• receiving sensitivity in a range of mV• very high robustness to ESD, andtemperature conditions• very low EM radiation

OUTLINE:IntroductionASIC design flow ASIC design exampleConclusionConclusion• ASIC stands for Application Specific Integrated Circuit• ASIC provides compact solution for complex applications• ASIC solution is well fitted for mass production and forhighly-specialized applications• ASIC is developed in a design flow• The design flow consists from steps – design phases:• Design feasibility phase• Pre-study phase• Development phase• Limited Production phase

IntermezzoWhat are actually the most often designed analogbuilding blocks during an ASIC design at AMIS?operational amplifierstransconductance stagescomparatorssignal filtersdrivers, buffersoscillatorsanalog-to-digital convertersdc-dc converterscharge pumpsregulatorsbandgap references