TAfS320C3x - Al Kossow's Bitsavers
TAfS320C3x - Al Kossow's Bitsavers
TAfS320C3x - Al Kossow's Bitsavers
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.. TEXASINSTRUMENlS<strong>TAfS320C3x</strong>.• t ••1991Digital Signal Processing Products
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<strong>TAfS320C3x</strong>UserJs Guide2558539-9721 revision EJune 1991~TEXASINSTRUMENTS
IMPORTANT NOTICETexas Instruments (TI) reserves the right to make changes to or to discontinue any semiconductorproduct or service identified in this publication without notice. TI advises its customers to ob. tain the latest version of the relevant information to verify, before placing orders, that the informationbeing relied upon is current.TI warrants performance of its semiconductor products to current specifications in accordancewith Tl's standard warranty. Testing and other quality control techniques are utilized to the extentTI deems necessary to support this warranty. Unless mandated by government requirements,specific testing of all parameters of each device is not necessarily performed.TI assumes no liability for TI applications assistance, customer product design, software performance,or infringement of patents or services described herein. Nor does TI warrant or representthat license, either express or implied, is granted under any patent right, copyright, maskwork right, or other intellectual property right of TI covering or relating to any combination, machine,or process in which such semiconductor products or services might be or are used.Texas Instruments products are not intended·for use in life-support appliances, devices, or systems.Use of a TI product in such applications without the written consent of the appropriate TIofficer is prohibited.WARNINGThis equipment is intended for use in a laboratory test environment only. It generates, uses, andcan radiate (adiofrequency energy and has not been tested for compliance with the limits of computingdevices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonableprotection against radio frequency interference. Operation of this equipment in other environmentsmay cause interference with radio communications, in which case the user at his ownexpense will be required to take whatever measures may be required to correct this interference.Copyright © 1991, Texas Instruments Incorporated
PrefaceRead This FirstThe purpose of this user's guide is to serve as a reference book for theTMS320C3x generation of digital signal processors that includes·TMS320C30, TMS320C30-27, TMS320C30-40, TMS320C31, andTMS320C31-27. Throughout the book, all references to the TMS320C30 applyto the TMS320C30-27 and TMS320C30-40 as well, and TMS320C31 refersto TMS320C31 and TMS320C31-27, unless an exception is noted. Thisdocument provides information to assist managers and hardware/software engineersin application development.How to Use This ManualThis document contains the following chapters:Chapter 1Chapter 2Chapter 3Chapter 4Chapter 5Chapter 6IntroductionA general description of the TMS320C30 and TMS320C31, their key features(features differ), and typical applications.Architectural OverviewFunctional block diagram. TMS320C3x design description, hardware components,and device operation. Instruction set summary.CPU Registers, Memory, and CacheDescription of the registers in the CPU register file. Memory maps providedand instruction cache architecture, algorithm, and control bits explained.Data Formats and Floating-Point OperationDescription of signed and unsigned integer and floating-point formats. Discussionof floating-point multiplication, addition, subtraction, normalization,rounding, and conversions.AddressingOperation, encoding, and implementation of addressing modes. Format descriptions.System stack management. -Program Flow ControlSoftware control of program flow with repeat modes and branching. Interlockedoperations. Reset and interrupts.iii
Read This FirstChapter 1Chapter 8Chapter 9Chapter 10Chapter 11Chapter 12Chapter 13Appendix AExternal Bus OperationDescription of primary and expansion interfaces. Externalinterface timing diagrams.Programmable wait-states and bank switching.PeripheralsDescription of the DMA controller, timers, and serial ports.Pipeline OperationDiscussion of the pipeline of operations on the TMS320C3x.Assembly Language InstructionsFunctional listing of instructions. Condition codes defined. <strong>Al</strong>phabetized individualinstruction descriptions with examples.Software ApplicationsSoftware application examples for the use of various TMS320C3x instructionset features.Hardware ApplicationsHardware design techniques and application examples for interfacing to memories,peripherals, or other microcomputers/microprocessors.TMS320C3x Signal Description and Electrical CharacteristicsPin locations, pin descriptions, dimensions, electrical characteristics, signaltiming diagrams and characteristics.Instruction OpcodesList of the opcode fields for all the TMS320C3x instructions.Appendix B Development Support/Part Order InformationListings of the hardware and software available to support the TMS320C3x device.Appendix CQuality and ReliabilityDiscussion of Texas Instruments quality and reliability criteria for evaluatingperformance.Appendix D Calculation of TMS320C30 Power DissipationInformation used to determine the. power dissipation and the thermal managementrequirements for the TMS320C30.Appendix EAppendix FSMJ320C30 Digital Signal Processor Data SheetData sheet for the SMJ320C30 digital signal processor.Quick Reference GuideOver 30 pages of the most referenced tables and figures.ivRead This First
Read This FirstReferencesThe publications in the following reference list contain useful information regardingfunctions, operations, and applications of digital signal processing .. These books also provide other references to many useful technical papers.The reference list is organized into categories of general DSP, speech, imageprocessing, and digital control theory, and is alphabetized by author.Q General Digital Signal Processing:Antoniou, Andreas, Digital Filters: Analysis and Design. New York, NY:McGraw-Hili Company, Inc., 1979.Bateman, A., and Yates, W., Digital Signal Processing Design. Salt LakeCity, Utah:, W. H. Freeman and Company, 1990.Brigham, E. Oran, The Fast Fourier Transform. Englewood Cliffs, NJ:Prentice-Hall, Inc., 1974. \Burrus, C.S., and Parks, T. W., DFTIFFTand Convolution <strong>Al</strong>gorithms. NewYork, NY: John Wiley and Sons, Inc., 1984.Chassaing, R., and Horning, D., Digital Signal Processing with theTMS320C25. New York, NY: John Wiley and Sons, Inc., 1990.Digital Signal Processing Applications with the TMS320 Family, Vol. I. TexasInstruments, 1986; Prentice-Hall, Inc., 1987.Digital Signal Processing Applications with the TMS320 Family, Vol. II.Texas Instruments; Prentice-Hall, Inc., 1990.Digital Signal Processing Applications with the TMS320 Family, Vol. III.Texas Instruments; Prentice-Hall, Inc., 1990.Gold, Bernard, and Rader, C.M., Digital Processing of Signals. New York,NY: McGraw-Hili Company, Inc., 1969.Hamming, R.W., Digital Filters. Englewood Cliffs, NJ: Prentice-Hall, Inc.,1977.IEEE ASSP DSP Committee (Editor), Programs for Digital Signal Processing.New York, NY: IEEE Press, 1979.Jackson, Leland B., Digital Filters and Signal Processing. Hingham, MA:Kluwer Academic Publishers, 1986.Jones, D.L., and Parks, T.W., A Digital Signal Processing Laboratory Usingthe TMS32010. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987.Hutchins, B., and Parks, T., A Digital Signal Processing Laboratory Usingthe TMS320C25. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1990.Lim, Jae, and Oppenheim, <strong>Al</strong>an V. (Editors), Advanced Topics in SignalProcessing. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1988.v
Read This FirstMorris, L. Robert, Digital Signal Processing Software. Ottawa, Canada:Carleton University, 1983.Oppenheim, <strong>Al</strong>an V. (Editor), Applications of Digital Signal Processing.Englewood Cliffs, NJ: Prentice-Hall, Inc., 1978.Oppenheim, <strong>Al</strong>an V., and Schafer, R.W., Digital Signal Processing. EnglewoodCliffs, NJ: Prentice-Hall, Inc., 1975.Oppenheim, <strong>Al</strong>an V., and Willsky, A.N., with Young, I.T., Signals and Systems.Englewood Cliffs, NJ: Prentice-Hall, Inc., 1983.Parks, T.W., and Burrus, C.S., Digital Filter Design. New York, NY: JohnWiley and Sons, Inc., 1987.Rabiner, Lawrence R., and Gold, Bernard, Theory and Application of DigitalSignal Processing. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1975.Treichler, J.R., Johnson, Jr., C.R., and Larimore, M.G., Theory and Designof Adaptive Filters. New York, NY: John Wiley and Sons, Inc., 1987.QQQSpeech:Gray, A.H., and Markel, J.D., Linear Prediction of Speech. New York, NY:Springer-Verlag, 1976.Jayant, N.S., and Noll, Peter, Digital Coding of Waveforms. EnglewoodCliffs, NJ: Prentice-Hall, Inc., 1984.Papamichalis, Panos, Practical Approaches to Speech Coding. EnglewoodCliffs, NJ: Prentice-Hall, Inc., 1987.Rabiner, Lawrence R., and Schafer, R.W., Digital Processing of SpeechSignals. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1978.Image Processing:Andrews, H.C., and Hunt, B.R., Digital Image Restoration. EnglewoodCliffs, NJ: Prentice-Hall, Inc., 1977.Gonzales, Rafael C., and Wintz, Paul, Digital Image Processing. Reading,MA: Addison-Wesley Publishing Company, Inc., 1977.Pratt, William K., Digital Image Processing. New York, NY: John Wiley andSons, 1978.Digital Control Theory:Dote, Y., Servo Motor and MotibnContr6tUsing Digital Signal Processors.Englewood Cliffs, NJ: Prentice-Hall, Inc., 1990.Jacquot, R., Modern Digital Control Systems. New York, NY: Marcel Dekker,Inc., 1981.Katz, P., Digital Control Using Microprocessors. Englewood Cliffs, NJ:Prentice-Hall, Inc., 1981.viRead This First
Read This FirstKuo, B.C., Digital Control Systems. New York, NY: Holt, Reinholt andWinston, Inc., 1980.Moroney, P., Issues in the Implementation of Digital Feedback Compensators.Cambridge, MA: The MIT Press, 1983.Phillips, C.,. and Nagle, H., Digital Control System Analysis and Design.Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984.Style and Symbol ConventionsThis document uses the following conventions:QProgram listings, program examples, interactive displays, filenames, andsymbol names are shown in a special font. Examples use a bold versionof the special font for emphasis. Here is a sample program listing:0011 0005 00010012 0005 00030013 0005 00060014 0006.field.field.field. even1,"'"3, 46, 3QQIn syntax descriptions, the instruction, command, or directive is in a bold.face font and parameters are in italics. Portions of a syntax that are in boldface should be entered as shown; portions of a syntax that are in italicsdescribe the type of information that should be entered. Here is an exampleof a directive syntax:.asect "section name" ~ address.asect is the directive. This directive has two parameters, indicated by sectionname and address. When you use .asect, the first parameter must bean actual section name, enclosed in double quotes; the second parametermust be an address.Square brackets ( [ and] ) identify an optional parameter. If you use an optionalparameter, you specify the information within the brackets; you don'tenter the brackets themselves. Here's an example of an instruction thathas an optional parameter:LALK 16-bit constant [, shift]The LALK instruction has two parameters. The first parameter, 16-bitconstant,is required. The second parameter, shift, is optional. As this syntaxshows, if you use the optional second parameter, you must precede it witha comma.Square brackets are also used as part of the pathname specification forVMS pathnames; in this case, the brackets are actually part of the pathname(they are not optional).vii
Read This FirstQQBraces ( {and} ) indicate a list. The symbol I (read as or) separates itemswithin the list. Here's an example of a list:{ * I *+ 1*- }This provides three choices: '\ ':'+, or *-.Unless the list is enclosed in square brackets, you must choose one itemfrom the list.Some directives can have a varying number of parameters. For example,the .byte directive can have up to 100 parameters. The syntax for this directiveis.bytevaluB1 [, '" , valUBnJThis syntax shows that .byte must have at least one value parameter, butyou have the option of supplying additional value parameters separated bycommas.Information About Cautions and WarningsThis book may contain cautions and warnings.Q A caution describes a situation that could potentially cause your systemto behave unexpectedly.This is what a caution looks like.The information in a caution is provided for your information. Please read eachcaution carefully.viiiRead This First
Read This FirstTrademarksCode View, MS-Windows, MS, MS-DOS and Presentation Manager are trademarks of MicrosoftCorp.DEC, Digital OX, VAX, VMS, and Ultrix are trademarks of Digital Equipment Corp.HPGL is a registered trademark of Hewlett-Packard Co.Macintosh and MPWare trademarks of Apple Computer Corp.OS/2, PC-DOS, PGA, and Micro Channel are trademarks of IBM Corp.Sun 3, Sun 4, Sun Workstation, SunView, SunWindows, and SPARC are trademarks of SunMicrosystems, Inc.UNIX is a registered trademark of AT&T Bell Laboratories.ix
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Contents3.1.8 CPU/DMA Interrupt Enable Register (IE) .............................. " 3-83.1.9 CPU Interrupt Flag Register (IF) ....................................... 3-93.1.10 110 Flags Register (IOF) ............................................. 3-103.1.11 Repeat-Count (RC) and Block-Repeat Registers (RS, RE) ............... 3-113.1.12 Program Counter (PC) . ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-113.1.13 Reserved Bits and Compatibility ...................................... 3-113.2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-123.2.1 TMS320C3x Memory Maps .......................................... 3-123.2.2 TMS320C31 Memory Maps .......................................... 3-143.2.3 ResetllnterruptiTrap Vector Map ...................................... 3-163.2.4 Peripheral Bus Map ................................................. 3-183.3 Instruction Cache .......................................................... 3-193.3.1 CacheArchitecture ................................................. 3-193.3.2 Cache <strong>Al</strong>gorithm ................................................... , 3-203.3.3 Cache Control Bits .................................................. 3-223.4 Using the TMS320C31 Boot Loader .............. ~ ........................... 3-233.4.1 Boot Loader Operations ... , ......................................"... 3-233.4.2 Invoking the Boot Loader ............................................ 3-233.4.3 Mode Selection ..................................................... 3-253.4.4 External Memory Loading ................. .' ........... ; .............. 3-263.4.5 Examples of External Memory Loads .................................. 3-263.4.6 Serial Port Loading ................................................. 3-283.4.7 Interrupt and Trap Vector Mapping .................................... 3-294 Data Formats and Floating-Point Operation . ..................................... " 4-14.1 Integer Formats ......................................"...................... 4-24.1.1 "Short Integer Format ................................................. "4-24.1.2 Single-Precision Integer Format ....................................... 4-24.2 Unsigned-Integer Formats ................................................... 4-34.2.1 Short Unsigned-Integer Format ............................ ~ ......... " 4-34.2.2 Single-Precision Unsigned-Integer Format .............................. 4-34.3 Floating-Point Formats ...................................................... 4-44.3.1 Short Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-44.3.2 Single-Precision Floating-Point Format ................................ \ 4-64.3.3 Extended-Precision Floating-Point Format .............................. 4-64.3.4 Conversion Between Floating-Point Formats ............................ 4-84.4 Floating-Point Multiplication ................................................. 4-104.5 Floating-Point Addition and Subtraction ..................................... " 4-144.6 Normalization Using the NORM Instruction .................................... 4-184.7 Rounding: The RND Instruction .............................................. 4-20" 4.8 Floating-Point to Integer Conversion ........................................ " 4-224.9 Integer to Floating-Point Conversion Using the FLOAT Instruction ................ 4-245 Addressing .. ................................................................... , 5-15.1 Types of Addressing ........................................................ 5-2xiiTable of Contents
Contents5.1 .1 Register Addressing ................................................. 5-35.1.2 Direct Addressing .................. ,................................ 5-45.1.3 Indirect Addressing .................................................. 5-55.1.4 Short-Immediate Addressing ......................................... 5-175.1.5 Long-Immediate Addressing ......................................... 5-175.1.6 PC-Relative Addressing .......................... ;.................. 5-185.2 Groups of Addressing Modes ............................................... 5-195.2.1 General Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-195.2.2 Three-Operand Addressing Modes ................................... 5-205.2.3 Parallel Addressing Modes .......................................... 5-215.2.4 Long-Immediate Addressing Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-225.2.5 Conditional-Branch Addressing Modes ................................ 5-235.3 Circular Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-245.4 Bit-Reversed Addressing ................................................... 5-295.5 System and User Stack Management ........................................ 5-305.5.1 Stacks ............................................. ; . . . . . . . . . . . . .. 5-315.5.2 Queues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-326 Program Flow Control ........................................................... 6-16.1 Repeat Modes ............................................................. 6-26.1.1 Repeat-Mode Initialization ............................................ 6-26.1.2 RPTB Initialization ................................................... 6-36.1.3 RPTS Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-36.1.4 Repeat-Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-46.2 Delayed Branches ........... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-76.3 Calls, Traps, and Returns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-86.4 Interlocked Operations ..................................................... 6-106.5 Reset Operation ................................. : . . . . . . . . . . . . . . . . . . . . . . . .. 6-166.6 Interrupts. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-206.6.1 Interrupt Control Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-206.6.2 TMS320C3x Interrupt Considerations ................................. 6-216.6.3 TMS320C30 Interrupt Considerations ................................. 6-226.6.4 Prioritization and Control ............................................ 6-257 External Bus Operation . ......................................................... 7-17.1 External Interface Control Registers ........................................... 7-27.1 .1 Primary-Bus Control Register ......................................... 7-37.1.2 Expansion-Bus Control Register ....................................... 7-47.2 External Interface Timing .................................................... 7-57.2.1 Primary-Bus Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-57.2.2 Expansion-Bus 1/0 Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-107.3 Programmable Wait States ................................................. 7-277.4 Programmable Bank Switching .............................................. 7-298 Peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-18.1 Timers ............................... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-2xiii
Contents8.1.1 Timer Global-Control Register ....................................... " 8-38.1.2 Timer Period and Counter Registers ................................... 8-68.1.3 Timer Pulse Generation .............................................. 8-68.1.4 Timer Operation Modes .............................................. 8-98.1.5 Timer Interrupts .................................................... 8-108.1.6 Timer Initialization/Reconfiguration .................................... 8-118.2 Serial Ports ............................................................... 8-128.2.1 Serial-Port Global-Control Register ................................... 8-148.2.2 FSX/DX/CLKX Port Control Register ................................. : 8-178.2.3 FSR/DR/CLKR Port Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-188.2.4 ReceiveiTransmit Timer Control Register ........ .'..................... 8-198.2.5 ReceiveiTransmit Timer Counter Register .............................. 8-218.2.6 ReceiveiTransmit Timer Period Register ............................... 8-218.2.7 Data-Transmit Register .............................................. 8-218.2.8 Data-Receive Register .............................................. 8-228.2.9 Serial-Port Operation Configurations .................................. 8-238.2.10 Serial-Port Timing .................................................. 8-248.2.11 Serial-Port Interrupt Sources ......................................... 8-278.2.12 Serial-Port Functional Operation ...................................... 8-288.2.13 TMS320C3x Serial Port Interface Examples ............................ 8-338.2.14 Serial Port Initialization/Reconfiguration ............................... 8-378.3 DMA Controller ............................................................ 8-388.3.1 DMA Global-Control Register ......................................... 8-398.3.2 Destination a~d Source Address Registers ............................. 8-428.3.3 Transfer Counter Register ........................................... 8-428.3.4 CPU/DMA Interrupt Enable Register .. : ............................... 8-428.3.5 DMA Memory Transfer Operation ..................................... 8-448.3.6 Synchronization of DMA Channels ........ ; ........................... 8-498.3.7 DMA Interrupts ..................................................... 8-518.3.8 DMA Setup and Use Examples .................................... : .. 8-528.3.9 DMA Initialization/Reconfiguration ..................... ~ .............. 8-539 Pipeline Operation ............................................................. " 9-19.1 Pipeline Structure ........................................................... 9-29.2 Pipeline Conflicts ........................................................... 9-49.2.1 Branch Conflicts ..................................................... 9-49.2.2 Register Conflicts. '................................................. " 9-69.2.3 .Memory Conflicts .................................................... 9-99.3 Resolving Register Conflicts ................................................. 9-179.4 Resolving Memory Conflicts ................................................. 9-199.5 Clocking of Memory Accesses ............................................... 9-219.5.1 Program Fetches ................................................... 9-219.5.2 Data Loads and Stores .............................................. 9-2210 Assembly Language Instructions ... ......... , ... " .... " ........................ 10-110.1 Assembly Language Instructions - Instruction Set ............................. 10-3xivTable of Contents
Contents10.1.1 Load-and-Store Instructions 10-310.1.2 Two-Operand Instructions ........................................... 10-410.1.3 Three-Operand Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-510.1.4 Program Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-510.1.5 Interlocked Operations Instructions ................................... 10-610.1.6 Parallel Operations Instructions ...................................... 10-610.2 Condition Codes and Flags ................................................. 10-910.3 Individual Instructions ..................................................... 10-1210.3.1 Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-1210.3.2 Optional Assembler Syntaxes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-1310.3.3 Individual Instruction Descriptions ................................... 10-1511 Software Applications .......................................................... 11-111.1 Processor Initialization ..................................................... 11-311.2 Program Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-711.2.1 Subroutines ....................................................... 11-711 .2.2 Software Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-911.2.3 Interrupt Service Routines ..... ;... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-1011 .2.4 Delayed Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-1511 .2.5 Repeat Modes .................................................... 11-1611.2.6 Computed GOTO's ................................................ 11-2011.3 Logical and Arithmetic Operations .......................................... 11-2111.3.1 Bit Manipulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-2111.3.2 Block Moves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-2311.3.3 Bit-Reversed Addressing ........................................... 11-2311.3.4 Integer and Floating-Point Division .................................. 11-2411.3.5 Square Root. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-3011.3.6 Extended-Precision Arithmetic ...................................... 11-3411.3.7 Floating-Point Format Conversion: IEEE to/from TMS320C3x ........... 11-3811.4' Application-Oriented Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-4811.4.1 Companding...................................................... 11-4811.4.2 FIR, IIR, and Adaptive Filters .......................... '. . . . . . . . . . . .. 11-5211.4.3 Matrix-Vector Multiplication ......................................... 11-6411.4.4 Fast Fourier Transforms (FFT) ...................................... 11-6611.4.5 Lattice Filters .............................................. '. . . . . .. 11-8211.5 Programming Tips ........................................................ 11-8811.5.1 C-Callable Routines ............................................... 11-8811.5.2 Hints for Assembly Coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-8812 Hardware Applications . ......................................................... 12-112.1 System Configuration Options Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-212.1.1 Categories of Interfaces on the TMS320C3x ........................... 12-212.1.2 Typical System Block Diagram ....................................... 12-312.2 Primary Bus Interface ...................................................... 12-4xv
Contents12.2.1 Zero Wait-State Interface to StaticRAMs .............................. 12-412.2.2 Ready Generation .................................................. 12-812.2.3 Bank Switching Techniques ......................................... 12-1212.3 Expansion Bus Interface ............................ ~ ...................... 12-1812.4 System Control Functions .................................................. 12-2512.4.1 ,Clock Oscillator Circuitry ............................................ 12-2512.4.2 Reset Signal Generation ............................................ 12-2712.5 Serial Port Interface ....................................................... 12-3012.6 XDS1 000 Target Design Considerations ..................................... 12-3412.7 Hewlett-Packard 64776 Analysis Subsystem Target Design Considerations ....... 12-3712.7.1 System Overview .................................................. 12-3712.7.2 Electrical Information ............................................... 12-3812.7.3 Timing Information ................................................. 12-3812.7.4 Mechanical Dimensions ............................................ 12-4012.8 TMS320C30 and TMS320C31 Differences ................................... 12-4112.8.1 Data/Program Bus Differences ...................................... ' 12-4112.8.2 Serial Port Differences ............................................. 12-4112,8.3 Reserved Memory Locations ........................................ 12-4112.8.4 Effects on the IF and IE Interrupt Registers ........................... , 12-4212.8.5 User Program/Data ROM ........................................... 12-4212.8.6 Development Considerations .................................. '" .... 12-4213 TMS320C3x Signal Descriptions and Electrical Characteristics. . . . . . . . . . . . . . . . . . . .. 13-113.1 Pinout and Pin Assignments ................................................. 13-213.1.1 TMS320C30 Pinouts and Pin Assignments. . . . . . . . . . . . .. . . . . . . . . . . . . . .. 13-213.1.2 TMS320C31 Pinouts and Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-613.2 Signal Descriptions ........................................................ 13-913.2.1 TMS320C30 Signal Descriptions ..................................... , 13-913.2.2 TMS320C31 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-1213.3 TMS320C3x Mechanical Data .............................................. 13-1513.4 Electrical Specifications .................................................... 13-1713.5 Signal Transition Levels ................................................... 13-1913.5.1 TTL-Level Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-1913.5.2 TTL-Level Inputs .........................,......................... 13-1913.6 Timing ................................................................... 13-2013.6.1 X2/CLKIN, Hi, and H3 Timing ....................................... 13-2013.6.2 Memory Read/Write Timing ......................................... 13-2213.6.3 XFO and XF1 Timing When Executing LDFI or LOll ..................... 13-2713.6.4 XFO Timing When Executing STFI and STII ....................'....... 13-2813.6.5 XFO and XF1 Timing When Executing SIGI ........................... 13-2913.6.6 Loading When the XF Pin Is Configured as an Output .................. 13-3013.6.7 ChanfJ~ng the XF Pin From an Output to an Input ...................... 13-3113.6.8 Changing the XF Pin From an Input to an Output ...................... 13-3213.6.9 Reset Timing ...................................................... 13-33xviTable of Contents
Contents13.6.10 SHZ Pin Timing ................................................... 13-3613.6.11. Interrupt Response Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-3713.6.12 Interrupt Acknowledge Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-3913.6.13 Data Rate Timing Modes ........................................... 13-4013.6.14 HOLD Timing ..................................................... 13-4513.6.15 General-Purpose I/O Timing ........................................ 13-4713.6.16 Timer Pin Timing .................................................. 13-50A Instruction Opcodes ......................................... ~ ................... A-18 Development Support/Part Order Information ..................................... 8-1B.1 TMS320C3x Development Support ........................................... B-2B.1.1 Macro Assembler/Linker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. B-3B.1.2 Optimizing ANSI C Compiler ......................................... , B-3B.1.3 Simulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. B-5B.1.4 The TMS320C3x Operating System (SPOX) ............................ B-6B.1.5 TMS320C3x Evaluation Module ........... ,........................... B-8B.1.6 TMS320C3x Emulator ~ Extended Development System(XDS500 and XDS1 000) ............................................. B-8B.1.7 Hewlett-Packard 64700 Analysis Subsystem ............ ~ .............. B-11B.1.8 TMS320 Third Parties ..................... '. . .. . . . . . . . . . . . . . . . . . . . . . .. B-12B.2 TMS320 Literature/DSP Hotline/Bulletin Board Services ........................ B-13B.3 Technical Training Organization (TTO) TMS320 Workshops . .. . . . . . . . . . . . . . . . . .. B-14B.3.1 TMS320C3x Design Workshop ....................................... B-14B.4 TMS320C3x Part Order Information .......................................... B-15B.4.1 Device and Development Support Tool Prefix Designators ............... 1?-16B.4.2 Device Suffixes .................................................... B-18C Quality and Reliability ........................................................... C-1C.1 Reliability Stress Tests ... ' .................................................. , C-2D Calculation of TMS320C30 Power Dissipation ..................................... D-1D.1 Fundamental Power Dissipation Characteristics ................................ D-3D.1 .1 Components of Power Supply Current Requirements .................... D-3D.1.2 Dependencies ...............•...................................... D-3D.1.3 Determining <strong>Al</strong>gorithm Partitioning ..................................... D-5D.1.4 Test Setup Description ............................................... D-5D.2 Current Requirement of Internal Circuitry ...................................... D-6D.2.1 Quiescent .......................................................... D-60.2.2 Internal Operations .................................................. D-6D.2.3 Internal Bus Operations ..........................•................... D-7D.3 Current Requirement of Output Driver Circuitry ................'............... " D-10D.3.1 Primary Bus .....................................................".. D-11D.3.2 Expansion Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. D-14D.3.3 Data Dependency .................................................. 0-15xvii
ContentsD.3.4 Capacitive Load Dependence ........................................ 0-170.4 Calculation of Total Supply Current ........................................... 0-19D.4.1 Combining Supply Current Due to <strong>Al</strong>l Components ...................... D-19D.4.2 Supply Voltage, Operating Frequency, and Temperature Dependencies .... D-20D.4.3 Design Equation .................................................... D-22D.4.4 Peak Versus Average Current ........................................ D-23D.4.5 Thermal Management Considerations ................................. D-24D.5 Example Supply Current Calculations ......................................... D-27D.5.1 Processing ......................................................... D-27D.5.2 Data Output ................... :.................................... D-27 'D.5.3 Average ........................................................... D-28D.5.4 Experimental Results ................................................ D-28D.6 Summary .................... "............................................ D-29D.7 Photo of IDD for FFT ....................................................... D-30D.8 FFT Assembly Code ....................................................... D-31 ,E SMJ320C30 Digital Signal Processor Data Sheet . .................................. E-1F Quick Reference . ............................................................... , F-1F.1 TMS320C30 and TMS320C31 Differences ..................................... F-2F.1.1 Data/Program Bus Differences ........................................ F-2F.1.2 Serial Port Differences ............................................... F-2F.1 .3 Reserved Memory Locations .......................................... F-2F.1.4 Effects on the IF and IE Interrupt Registers .............................. F-3, F.1.5 User Program/Data ROM ............................................. F-3F.1.6 Development Considerations ......................................... , F-3F.2 TMS320C3x Architecture .................................................... F-4F.3 CPU Register File .......................................................... , F-6F.3.1 Register Addressing ................................................. F-6F.4 Memory Maps ............................................................. F-12F.4.1 Interrupts .......................................................... F-14F.4.2 Peripheral Bus ............. ~ ....................................... F-16F.4.3 Serial Port ......................................................... F-23F.4.4 FSX/DX/CLKX Port Control Register .................................. F-27F.4.5 FSR/DR/CLKR Port Control Register ................... ~ .............. F-28F.4.6 ReceivelTransmit Timer Control Register .............................. F-29F.4.7 Primary-Bus and Expansion-Bus Control ............................... F-31F.4.8 Primary-Bus Control Register ........................................ F-32F.4.9 Expansion-Bus Control Register ...................................... F-33F.4.10 Programmable Bank Switching ....................................... F-34F.5 Instruction Set ............................................................. F-35F.5.1 Instruction Formats ................................................. F-35F.5.2 Summary .......................................................'... F-37xviiiTable of Contents
ures1-1 TMS320 Device Evolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-21-2 TMS320C3x Block Diagram .................................................... 1-42-1 TMS320C3x Block Diagram .................................... ~ . . . . . . . . . . . . . .. 2-22-2 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-42-3 Memory Organization .......................................... ~ . . . . . . . . . . . . .. 2-102-4 TMS320C30 Memory Maps ................................................... 2-122-5 TMS320C31 Memory Maps ................................................... 2-132-6 Peripheral Modules .......................................................... 2-242-7 DMA Controller .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-263-1 Extended-Precision Register Floating-Point Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-43-2 Extended-Precision Register Integer Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-43-3 Status Register ........................ '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-63-4 CPUIDMA Interrupt Enable Register (IE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-83-5 CPU Interrupt Flag Register (IF) ............................................... 3-103-6 1/0 Flag Register (IOF) ....................................................... 3-103-7 TMS320C30 Memory Maps ................................................... 3-133-8 TMS320C31 Memory Maps ................................................... 3-153-9 Reset, Interrupt, and Trap Vectr Locations ..................................... 3-173-10 Peripheral-Bus Memory Map .................................................. 3-183-11 Instruction Cache Architecture ................................................. 3-193-12 Address Partitioning for Cache Control <strong>Al</strong>gorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-203-13 Boot Loader Mode Selection Flowchart ......................................... 3-233-14 Boot Loader Memory Load Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-243-15 Boot Loader Serial Port Load Mode Flowchart ................................... 3-254-1 Short Integer Format and Sign Extension of Short Integer .......................... 4-24-2 Single-Precision Integer Format ...................... _. . . . . . . . . . . . . . . . . . . . . . . . . .. 4-24-3 \ Short Unsigned-Integer Format and Zero Fill ..................................... 4-34-4 Single-Precision Unsigned-Integer Format ....................................... 4-34-5 Generic Floating-Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-44-6 Short Floating-Point Format .................................................... 4-54-7 Single-Precision Floating-Point Format .................... ~ . . . . . . . . . . . . . . . . . . . .. 4-6xix
4-8 Extended-Precision Floating-Point Format ........................................ 4-74-9 Flowchart for Floating-Point Multiplication ....................................... 4-114-10 Flowchart for Floating-Point Addition ............................................ 4-154-11 Flowchart for NORM Instruction Operation ....................................... 4-184-12 Flowchart for Floating-Point Rounding by the RND Instruction ...................... 4-214-13 Flowchart for Floating-Point to Integer Conversion by FIX Instructions ............... 4-234-14 Flowchart for Integer to Floating-Point Conversion by FLOAT Instructions ............ 4-245-1 Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-45-2 Encoding for General Addressing Modes ........................................ 5-205-3 Encoding for Three-Operand Addressing Modes ................................. 5-215-4 Encoding for Parallel Addressing Modes ........................................ 5-215-5 Encoding for Long-Immediate Addressing Mode .................................. 5-235-6 Encoding for Conditional-Branch Addressing Modes .............................. 5-235-7 Flowchart for Circular Addressing .............................................. 5-255-8 Circular Buffer Implementation ................................................. 5-265-9 Circular Addressing Example ................ ~ ................................. 5-275-10 Data Structure for FIR Filters .................................................. 5-285-11 FIR Filter Code Using Circular Addressing ....................................... 5-285-12 Bit-Reversed Addressing Example .............................................. 5-295-13 System Stack Configuration ................................................... 5-305-14 Implementations of High-to-Low Memory Stacks ................................. 5-315-15 Implementations of Low-to-High Memory Stacks ................................. 5-326-1 Repeat-Mode Control <strong>Al</strong>gorithm ................................................. 6-46-2 CALL Response Timing .................................... ' .................... 6-96-3 Multiple TMS320C3xs Sharing Global Memory ................. : ................. 6-136-4 Zero-Logic Interconnect of TMS320C3xs ........................................ 6-146-5 Interrupt Logic Functional Diagram ............................................. 6-206-6 Interrupt Processing .......................................................... 6-277-1 Memory-Mapped External Interface Control Registers .............................. 7-27-2' Primary-Bus Control Register ................................................... 7-37-3 Expansion-Bus Control Register ................................................. 7-47-4 Read-Read-Write for (M)STRB = 0 .............................................. 7-67-5 Write-Write-Read for (M)STRB = 0 .............................................. 7-77-6 Use of Wait States for Read for (M)STRB = 0 ..................................... 7-87-7 Use of Wait States for Write for (M)STRB = 0 ..................................... 7-97-8 Read and Write for IOSTRB = 0 ................................................ 7-107-9 Read With One Wait State for IOSTRB = 0 ...................................... 7-117-10 Write With One Wait-State for IOSTRB = 0 ...................................... 7-12xxTable of Contents
7-11 Memory Read and I/O Write for Expansion Bus .................................. 7-137-12 Memory Read and I/O Read for Expansion Bus ....... . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-147-13 Memory Write and I/O Write for Expansion Bus .................................. 7-157-14 Memory Write and I/O Read for Expansion Bus ................................'.. 7-167-15 I/O Write and Memory Write for Expansion Bus .................................. 7-177-16 I/O Write and Memory Read for Expansion Bus .................................. 7-187-17 I/O Read and Memory Write for Expansion Bus .................................. 7-197-18 I/O Read and Memory Read for Expansion Bus .................................. 7-207-19 I/O Write and I/O Read for Expansion Bus ....................................... 7-217-20 I/O Write and I/O Write for Expansion Bus ....................................... 7-227-21 I/O Read and I/O Read for Expansion Bus ...................................... 7-237-22 Inactive Bus States for 10STRB .........................................'....... 7-247-23 Inactive Bus States for STRB and MSTRB ...................................... 7-257-24 HOLD and HOLDA Timing .................................................... 7-267-25 BNKCMP Example ................................... : .... : .................. 7-297-26 Bank Switching Example ...................................................... 7-308-1 Timer Block Diagram .......................................................... 8-28-2 Memory-Mapped Timer Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-38-3 Timer Global-Control Register .................................................. 8-48-4 Timer. Timing ................................................................. 8-78-5 Timer Output Generation Examples ............................................. 8-88-6 Timer I/O Port Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-98-7 Timer Modes as Defined by CLKSRC and FUNC . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. 8-108-8 Serial-Port Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-138-9 Memory-Mapped Locations for the Serial Port ................................... 8-148-10 Serial-Port Global-Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-158-11 FSX/OX/CLKX Port Control Register ........................................... 8-178-12 FSR/DR/CLKR Port Control Register ........................................... 8-188-13 Receive/Transmit Timer Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-198-14 ReceiveiTransmit Timer Counter Register ................................ ~ ...... 8-218-15 Receive/Transmit Timer Period Register ........................................ 8-218-16 Transmit Buffer Shift Operation ................................................ 8-228-17 Receive Buffer Shift Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-228-18 Serial-Port Clocking in I/O Mode ............................................... 8-238-19 Serial-Port Clocking in Serial-Port Mode ........................................ 8-248-20 Data Word Format in Handshake Mode ... ;.......... . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-268-21 Single Zero Sent as an Acknowledge .............. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-268-22 Direct Connection Using Handshake Mode ...................................... 8-27xxi
8-23 Fixed Burst Mode ................. ' ........................................... 8-298-24 Fixed Continuous Mode With Frame Sync .. " ....... " .......................... 8-298-25 Fixed Continuous Mode Without Frame Sync .................................... 8-308-26 Exiting Fixed Continuous Mode Without Frame Sync, FSX Internal ................. 8-318-27 Variable Burst Mode .......................................................... 8-328-28 Variable Continuous Mode With Frame Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-328-29 Variable Continuous Mode Without Frame Sync .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-338-30 TMS320C3x Zero Glue-Logic Interface to TLC3204x Example ..................... 8-358-31 . TMS320C3x Zero Glue-Logic Interface to Burr Brown AID and D/A Example ......... 8-368-32 Memory-Mapped Locations for a DMA Channel .......................•.......... 8-398-33 DMA Global-Control Register .................................................. 8-408-34 CPU/DMA Interrupt Enable Register ........................................... 8-438-35 Timing and Number of Cycles for DMA Transfers When Destination Is On-Chip ...... 8-458-36 DMA Timing When Destination Is a Primary Bus ................................. 8-468-37 DMA Timing When Destination Is an Expansion Bus .............................. 8-478-38 No DMA Synchronization ....... " ............................................. 8-498-39 DMA Source Synchronization .................................................. 8-508-40 DMA Destination Synchronization .............................................. 8-508-41 DMA Source and Destination Synchronization ................................... 8-519-1 TMS320C3x Pipeline Structure ........................... '. . . . . . . . . . . . . . . . . . . . . .. 9-39-2 Two-Operand Instruction Word ................................................ , 9-229-3 Three-Operand Instruction Word ............................................... 9-239-4 Multiply or CPU Operation With a Parallel Store ................................ ~. 9-24 .9-5 Two Parallel Stores ........................................................... 9-259-6 Parallel Multiplies and Adds ............................... : ................... 9-2510-1 Status Register ............................................................. 10-1011-1 Data Memory Organization for an FIR Filter ..................................... 11-5311-2 Data Memory Organization for a Single Biquad .................................. 11-5511-3 Data Memory Organization for N Biquads ...................................... 11-5811-4 Data Memory Organization for Matrix-Vector Multiplication . . . . . . . . . . . . . . . . . . . . . . .. 11-6411-5 Structure of the Inverse Lattice Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-8311-6 Data Memory Organization for Lattice Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-8311-7 Structure of the (Forward) Lattice Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-8612-1 External Interfaces on the TMS320C3x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-212-2 Possible System Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-312-3 TMS320C3x Interface to Cypress Semiconductor CY7C186 CMOS SRAM .......... 12-512-4 Read Operations Timing ...................................................... 12-612-5 Write Operations Timing ....................................................... 12-7xxiiTable of Contents
12-6 Circuit for Generation of 0, 1, or 2 Wait States for Multiple Devices ................ 12-1112-7 Bank Switching for Cypress Semiconductor's CY7C185 . . . . . . . . . . . . . . . . . . . . . . . . .. 12-1312-8 . Bank Memory Control Logic .................................................. 12-1512-9 Timing for Read Operations Using Bank Switching ....... ,...................... 12-1712-10 Interface to AD1678 AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-1912-11 Read Operations Timing Between the TMS320C30 and AD1678 .................. 12-2112-12 Interface Between the TMS32'OC30 and the AD565A ............................ 12-2312-13 Write Operation to the D/A Converter Timing Diagram ........................... 12-2412-14 Crystal Oscillator Circuit ..................................................... 12-2512-15 Magnitude of the Impedance of the Oscillator LC Network. . . . . . . . . . . . . . . . . . . . . . .. 12-2612-16 Reset Circuit ............................................................... 12-2712-17 Voltage on the TMS320C30 Reset Pin ............. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-2812-18 AIC to TMS320C30 Interface ................................................. 12-3112-19 Synchronous Timing of TLC32044 to TMS320C3x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-3312-20 Asynchronous Timing of TLC32044 to TMS320C30 ............................. 12-3312-21 12-Pin Header Signals ....................................................... 12-3412-22 Typical Setup for Using the Emulation Connection of the XDS1 000 ................ 12-3512-23 Installation Overview ............ ' ............................................ 12-3712-24 Analysis Subsystem Pod/Connector Dimensions ................................ 12-4013-1 TMS320C30 Pinout (Top View) . . . . . . . . . . . . . . . . • . . . . . .. . . . . . . . . . . . . . . . . .. . . . . .. 13-213-2 TMS320C30 Pinout (Bottom View) ............................................. 13-313-3 TMS320C31 Pinout (Top View) ................................................ 13-613-4 TMS320C30 181-Pin PGA Dimensions ........................................ 13-1513-5 TMS320C31 132-Pin Plastic Quad Flat Pack ................................... 13-1613-6 Test Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-1813-7 TTL-Level Outputs .......................................................... 13-1913-8 TTL-Level Inputs ............................................................ 13-1913-9 Timing for X2/CLKIN ........................................................ 13-2013-10 Timing for H1/H3 ............................................................ 13-2013-11 Timing for Memory ( (M)STRB = 0) Read ...................................... 13-2213-12 Timing for Memory ( (f\i1)SfRB = 0) Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-2313-13 Timing for Memory ( IOSTR,B = 0) Read ....................................... 13-2513-14 Timing for Memory ( IOSTRB = 0) Write ....................................... 13-2613-15 Timing for XFO and XF1 When Executing LDFI or LOll ........................... 13-2713-16 Timing for XFO When Executing a STFI or STII ................................. ,13-2813-17 Timing for XFO and XF1 When Executing SIGI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-2913-18 Timing for Loading XF Register When Configured as an Output Pin ............... 13-3013-19 Timing for Change of XF from Output to Input Mode ............................. 13-31xxiii
13-20 Timing for Change of XF From Input to Output Mode ........... ',' ................ 13-3213-21 Timing for RESET ........................................................... 13-3413-22 ClKIN to H1/H3 as a Function of Temperature .................................. 13-3513-23 Timing for SHZ Pin ..................................... ' ..................... 13-3613-24 Timing for INT3-INTO Response ............................................... 13-3713-25 Timing for lACK ............................................................. 13-3913-26 Timing for Fixed Data Rate Mode .............................................. 13-4013-27 Timing for Variable Data Rate Mode ........................................... 13-~ 113-28 Timing for HOLD/HOLDA ..................................................... 13-4513-29 Timing for Peripheral Pin General-Purpose I/O .................................. 13-4713-30 Timing for Change of Peripheral Pin From General-Purpose Output to Input Mode ... 13-4813-31 Timing for Change of Peripheral Pin From General-Purpose Input to Output Mode ... 13-4913-32 Timing for Timer Pin ......................................................... 13-50B-1 TMS320C3x Development Environment .......................................... B-1B-2B-3B-4B-50-10-20-30-40-50-6" 0-70-80-90-100-110-120-13F-1F-2F-3F-4F-5F-6F-7TMS320C3x Simulator User Interface ............................ ~ ............. " B-6Internal SPOX Architecture ..................................................... B-7Multiprocessing Emulation .................................................... " B-9TMS320 Device Nomenclature ................................................. B-18Current Measurement Test Setup ................................................ 0-5Internal Bus Current Versus Transfer Rate ........................................ 0-8Internal Bus Current Versus Data Complexity Derating Curve ....................... 0-9Primary Bus Current Versus Transfer Rate and Wait States ........................ 0-12Primary Bus Current Versus Transfer Rate at Zero Wait States ..................... 0-13Expansion Bus Current Versus Transfer Rate and Wait States ...................... 0-13Expansion Bus Current Versus Transfer Rate at Zero Wait States .................. 0-15Primary Bus Current Versus Data Complexity Derating Curve ..... : ................ 0-16Expansion Bus Current Versus Data Complexity Derating Curve .................... 0-17Current Versus Output" load Capacitance ....................................... 0-18Current Versus Frequency and Supply Voltage ................................... 0-21Current Versus Operating Temperature Change .................................. 0-21load Currents ............................................................... 0-:-24TMS320C3x Block Diagram .................................................... F-4TMS320C3x Block Diagram ....................... :............................ F-5Extended-Precision Register Floating-Point Format .............................. " F-7Extended-Precision Register Integer Format ...................................... F-7Data-Page Pointer (DP) Register Format .................................-...... " F-7Index Register (IRx) Format .................................................... F-7Block-Size (BK) Register Format ............. : .................................. F-7xxivTable of Contents
F-8 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. F-8F-9 CPU/DMA Interrupt Enable Register (IE) ........................................ , F-9F-10 CPU Interrupt Flag Register (IF) ............................................... F-10F-11 I/O Flag Register (lOF) ....................................................... F-11F-12 TMS320C30 Memory Maps ................................................... F-12F-13 TMS320C31 Memory Maps ................................................... F.: 13F-14 Reset, Interrupt, and Trap Vector Locations ..................................... F-14F-15 Reset, Interrupt, and Trap Vector Format .. '................... , .................. F-15F-16 Peripheral-Bus Memory-Map Registers ................"......................... F-16F-17 Memory-Mapped Locations for a DMA Channel ................ . . . . . . . . . . . . . . . . .. F-17F-18 DMA Global-Control Register Format ........................................... F-18F-19 Memory-Mapped Timer Locations .............................................. F-20F-20 Timer Global-Control Register ................................................. F-21F-21 Memory-Mapped Serial-Port Locations ......................................... F-23F-22 Serial-Port Global-Control Register Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. F-24F-23 FSX/DX/CLKX Port Control Register ........................................... F-27F-24 FSR/OR/CLKR Port Control Register ........................................... F-28F-25 ReceivelTransmit Timer Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. F-29F-26 Memory-Mapped External Interface Control Registers ............................ F-31F-27 Primary-Bus Control Register ................................................ " F-32F-28 Expansion-Bus Control Register ............................................... F-33xxv
Tables................................................................................................................................................................................................................................................................................................................'., .. '.............. ,........,.,..:.:.:.:.;.:.:.:.:.:.:.:.:.:.;.;.:.;.;.:.:.:.:.:.:.:.:.:.:.: :.'.:.:.:.:.:.:.:.:.:.:.:.:.:,:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.: :·:·;.:·;.;·;·;.x·;·:·:·;.;.:·;·;·:.:·;·;·:·:.:·:·:·:·;.;·:·;.;.:·:·:·;·;.:·;·:·:·:.;.;·s·:·; .:.:.:.:.:.:.;.;.:.;.:.:.;.;,:.:.:.:.:.;.:.;.;.:~.;.:,:.:.:.;.:.;.;.;.;.;.:.:., • • ,..:.:.;.:.:.:.:.;.:.:.:.:.:.:.......... •.. :.:.:.:.:.:.:.:.:.:.:.;.:.;.:.:.: :.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.;.:.:.:.:.:.;.:.:.:.:.:.:.:.:.;.:.:.:.:.:.:.:.;.:.:.:.:.:.:-1-1 Typical Applications of the TMS320 Family ....................................... 1-72-1 CPU Registers .............................................................. " 2-62-2 Instruction Set Summary ...................................................... 2-152-3 Parallel Instruction Set Summary ............................................... 2-203-1 CPU Registers ................................................................ 3-33-2 Status Register Bits Summary .................................................. 3-73-3 IE Register Bits Summary ...................................................... 3-93-4 IF Register Bits Summary ..................................................... 3-103-5 IOF Register Bits Summary .................................................... 3-113-6 Combined Effect of the CE and CF Bits ......................................... 3-223-7 Loader Mode Selection ....................................................... 3-263-8 External Memory Loader Header ................... . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-263-9 TMS320C31 Interrupt and Trap Memory Maps ................................... 3-305-1 CPU Register/Assembler Syntax and Function .................................. " 5-35-2 Indirect Addressing ............................................................ 5-65-3 Index Steps and Bit-Reversed Addressing ....................................... 5-296-1 Repeat-Mode Registers ........................................................ 6-26-2 Interlocked Operations ............................... : ........................ 6-106-3 Pin Operation at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-; 166-4 Reset and Interrupt Vector Locations ............................................ 6-257-1 Primary-Bus Control Register Bits Summary ...................................... 7-37-2 Expansion-Bus Control Register Bits Summary .................................. " 7-47-3 Wait-State Generation When SWW = 0 0 .... , ................................... 7-287-4 Wait-State Generation When SWW = 0 1 ........................................ 7-287-5 Wait-State Generation When SWW = 1 0 ........................................ 7-28.7-6 Wait-State Generation When SWW = 1 1 ...................... ; .............. : .. 7-287-7 BNKCMP and Bank Size ...................................................... 7-298-1 Timer Global-Control Register Bits Summary ..................................... 8-48-2 Result of a Write of Specified Values of GO and HLD .............................. 8-58-3 Serial-Port Global-Control Register Bits Summary ................................ 8-15xxvi ~ Table of Contents
Tables8-4 FSXlDX/CLKX Port Control Register Bits Summary .............................. 8-178-5 FSR/DR/CLKR Port Control Register Bits Summary .............................. 8-188-6 Receiverrransmit Timer Control Register ................................ ; . . . . . .. 8-198-7 DMA Global-Control Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-408-8 START Bits and Operation of the DMA (Bits 0-1) ................................ 8-418-9 STAT Bits and Status of the DMA (Bits 2-3) ..................................... 8-418-10 SYNC Bits and Synchronization of the DMA (Bits 8-9) ............................ 8-418-11 CPU/DMA Interrupt Enable Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-438-12 Maximum DMA Transfer Rates When Cr = Cw = 0 ............................... 8-488-13 Maximum DMA Transfer Rates When Cr = 1, Cw = 0 ............................. 8-488-14 Maximum DMA Transfer Rates When Cr = 1, Cw = 1 ............................. 8-489-1 One Program Fetch and One Data Access for Maximum Performance .............. 9-199-2 One Program Fetch and Two Data Accesses for Maximum Performance ............ 9-2010-1 Load..:and-Store Instructions ................................................ ~ .. 10-310-2 Two-Operand Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-410-3 Three-Operand Instruct,ons ................................................... 10-510-4 Program Control Instructions .................................................. 10-610-5 Interlocked Operations Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-610-6 Parallel Instructions .......................................................... 10-710-7 Output Value Formats ........................................................ 10-910-8 Condition Codes and Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-1110-9 Instruction Symbols ......................................................... 10-1210-10 CPURegisterSyntax ........................................................ 10-1511-1 .TMS320C3x FFT Timing Benchmarks ......................................... 11-8212-1 Bank Switching Interface Timing .............................................. 12-1712-2 Key Timing Parameter for D/A Converter Write Operation ........................ 12-2412-3 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-3412-4 Feature Set Comparison ................................ , . . . . . . . . . . . . . . . . . . .. 12-4112-5 TMS320C31 ReseNed Memory Locations ..................................... 12-4213-1 TMS320C30 Pin Assignments(by Function) (Figure 13-1 and Figure 13-2) . . . . . . . . .. 13-4·13-2 TMS320C30 Pin Assignments(<strong>Al</strong>phabetical) (Figure 13-1 and Figure 13-2) ......... 13-513-3 TMS320C31 Pin Assignments (<strong>Al</strong>phabetical) (Figure 13-3) . . . . . . . . . . . . . . . . . . . . . . .. 13-713-4 TMS320C31 Pin Assignments (Numerical) (Figure 13-3) . . . . . . . . . . . . . . . . . . . . . . . . .. 13-813-5 TMS320C30 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-913-6 TMS320C31 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-1213-7 Absolute Maximum Ratings Over Specified Temperature Range .................. 13-1713-8 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-17xxvii
Tables13-9 Electrical Characteristics Over Specified Free-Air Temperature Range ............. 13-1813-10 Timing Parameters for CL~IN, H1, and H3 (Figure 13-9 and Figure 13-10) ......... 13-2113-11 Timing Parameters for a Memory ( (M)STRB) = 0) ReadIWrite(Figure 13-11 and Figure 13-12) ............................................. 13-2313-12 Timing Parameters for a Memory ( 10STRB = 0) Read(Figure 13-13 and Figure 13-14) ............................................. 13-2513-13 Timing Parameters for a Memory ( 10STRB = 0) Write (Figure 13-14) .............. 13-2613-14 Timing Parameters for XFO and XF1 When Executing LDFI or LOll (Figure 13-15) ... 13-2713-15 Timing Parameters for XFO When Executing STFI or STII (Figure 13-16) ........... 13-2813-16 Timing Parameters for XFO and XF1 When Executing SIGI (Figure 13-17) .......... 13-2913-17 Timing Parameters for Loading XF Register When Configured as an Output Pin(Figure 13-18) .............................................................. 13-3013-18 Timing Parameters of XF Changing From Output to Input Mode (Figure 13-19) ..... 13-3113-19 Timing Parameters of XF Changing From Input to Output Mode (Figure 13-20) ..... 13-3213-20 Timing Parameters for RESET (Figure 13-21) .................................. 13-3513-21 Timing Parameters for 8HZ Pin (Figure 13-23) ...... -............................ 13-3613-22 Timing Parameters for INT3-INTO (Figure 13-24) ............................... 13-3713-23 Timing Parameters for lACK (Figure 13-25) .................................... 13-3913-24 Serial Port Timing Parameters (Figure 13-26 and Figure 13-27) .................. 13-4213-25 Timing Parameters for HOLD/HOLDA (Figure 13-28) ............................ 13-4613-26 Timing Parameters for Peripheral Pin General-Purpose I/O (Figure 13-29) ......... 13-4713-27 Timing Parameters for Peripheral Pin Changing From General-Purpose Outputto Input Mode (Figure 13-30) ................................................. 13-4813-28 Timing Parameters for Peripheral Pin Changing From General-Purpose Inputto Output Mode (Figure 13-31) ................................................ 13-4913-29 Timing Parameters for Timer Pin (Figure 13-32) ................................. 13-50A-1 TMS320C3x Instruction Opcodes ................................................ A-1B-1 TMS320C3x Digital Signal Processor Part Number ................ : .............. B-15B-2 TMS320C3x Support Tool Part Numbers ........................................ B-15C-1 Microprocessor and Microcontroller Tests ......................................... C-5C-2 TMS320C3x Transistors ................ , ....................................... C-60-1 Current Equation Symbols ..................................................... 0-23F-1 Feature Set Comparison ....................................................... F-2F-2 TMS320C31 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. F-3F-3 CPU Register/Assembler Syntax and Function .................................... F-6F-4 BNKCMP and Bank Size ...................................................... F-34 'F-5 Indirect Addressing ........................................................... F-35F-6 Instruction Set Summary ...................................................... F-37F-7 Parallel Instruction Set Summary ............................................... F-42xxviiiTable of Contents
Exam les3-1 Byte-Wide Configured Memory ................................................ 3-273-2 16-Bit Wide Configured Memory ............................................... 3-273-3 32-Bit Wide Configured Memory ............................................... 3-284-1 Floating-:Point Multiply (Both Mantissas = -2.0) .................................. 4-124-2 Floating-Point Multiply (Both Mantissas = 1.5) ................................... 4-124-3 Floating-Point Multiply (Both Mantissas = 1.0) ................................... 4-134-4 Floating-Point Multiply Between Positive and Negative Numbers ................... 4-134-5 Floating-Point Multiply by Zero. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-134-6. Floating-Point Addition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-164-7 Floating-Point Subtraction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-164-8 Floating-Point Addition With a 32-Bit Shift .......... . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-174-9 Floating-Point Addition/Subtraction and Zero .................................... 4-174-10 NORM Instruction ............................................................ 4-195-1 Direct Addressing ............................'. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-45-2 Auxiliary Register Indirect .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-85-3 Indirect With Predisplacement Add .............................................. 5-85-4 Indirect With Predisplacement Subtract .......................................... 5-95-5 Indirect With Predisplacement Add and Modify. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-95-6 Indirect With Predisplacement Subtract and Modify. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-105-7 Indirect With Postdisplacement Add and Modify. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-105-8 Indirect With Postdisplacement Subtract and Modify. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-115-9 Indirect With Postdisplacement Add and Circular Modify .......................... 5-115-10 Indirect With Postdisplacement Subtract and Circular Modify ...................... 5-125-11 Indirect With Preindex Add .................................................... 5-125-12 Indirect With Preindex Subtract ................................................ 5-135-13 Indirect With Preindex Add and Modify. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-135-14 Indirect With Preindex Subtract and Modify. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-145-15 Indirect With Postindex Add and Modify ......................................... 5-145-16 Indirect With Postindex Subtract and Modify ..................................... 5-155-17 Indirect With Postindex Add and Circular Modify ................................. 5-15xxix
Examples5-18 Indirect With Postindex Subtract and Circular Modify .............................. 5-165-19 Indirect With Postindex Add and Bit-Reversed Modify ............................. 5-165-20 Short-Immediate Addressing ................. ~ ................................. 5-175-21 Long-Immediate Addressing ................................................... 5-175-22 PC-Relative Addressing ..................................................... " 5-186-1 RPTB Operation .............................................................. 6-56-2 Incorrectly Placed Standard Branch .............................................. 6-66-3 Incorrectly Placed Delayed Branch .............................................. 6-66-4 Incorrectly Placed Delayed Branches ............................................ 6-76-5 Busy-Waiting Loop ............................................................ 6-126-6 Multiprocessor Counter Manipulation ........................................... 6-126-7 Implementation of V(S) ...................................................... " 6-146-8 Implementation of P(S) ........................................................ 6-146-9 Code to Synchronize Two TMS320C3xs at the Software Level ............... '.... " 6-159-1 Standard Branch .............................................................. 9-59-2 De layed Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-69-3 Write to an AR Followed by an AR for Address Generation ......................... 9-79-4 A Head of ARs Followed by ARs for Address Generation ........................... 9-89-5 Program Wait Until CPU Data Access Completes ............................... " 9-109-6 Program Wait Due to Multicycle Access ......................................... 9-119-7 Multicycle Program Memory Fetches .......................................... " 9-119-8 Single Store Followed by Two Reads ........................................... 9-129-9 Parallel Store Followed by Single Read ......................................... 9-139-10 Interlocked Load ............................................................. 9-149-11 Busy Extern.al Port ........................................................... 9-159-12 Multicycle Data Reads ........................................................ 9-169-13 Conditional Calls and Traps .................................................. " 9-169-14 Address Generation Update of an AR Followed by an AR for Address Generation .... 9-179-15 Write to an AR Followed by an AR for Address Generation Without a Pipeline Conflict. 9-189-16 Write to DP Followed by a Direct Memory Road Without a Pipeline Conflict .......... 9-1811-1 TMS320C3xProcessorinitialization ............................................ 11-411-2 Subroutine Call (Dot Product) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-811-3 Use of Interrupts for Software Polling .......................................... 11-1011-4 Context-Save for the TMS320C3x ............................................. 11-1211-5 Context-Restore for the TMS320C3x ........................................... 11-1311-6 Interrupt Service Routine .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-1411-7 Delayed Branch Execution ................................................... 11-15xxxTable of Contents
11-8 Loop Using Block Repeat .................................................... 11-1711-9 Use of Block Repeat to Find a Maximum ........................................ 11-1811-10 Loop Using Single Repeat ................................................... 11-1911-11 Computed GOTO ........................................................... 11-2011-12 Use of TSTB for Software-Controlled Interrupt ................................ '. 11-2111-13 Copy a Bit From One Location to Another .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-2211-14 Block Move Under Program Control ........................................... 11-2311-15 Bit-Reversed Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-2411-16 Integer Division .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-2611-17 Inverse of a Floating-Point Number ........................................... 11-2911-18 Square Root of a Floating-Point Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-3211-19 64-Bit Addition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. 11-3511-20 64-Bit Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-3511-21 32-Bit by 32-Bit Multiplication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. 11-3611-22 IEEE toTMS320C3x Conversion (Fast Version) ................................. 11-4011-23 IEEE to TMS320C3x Conversion (Complete Version) ............................ 11-4211-24 TMS320C3x to IEEE Conversion (Fast Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-4511-25 TMS320C3x to IEEE Conversion (Complete Version) ............................ 11-4611-26 J.l-Law Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. 11-4911-27 J.l-Law Expansion ........................................................... 11-5011-28 A-Law Compression ......................................................... 11-5111-29 A-Law Expansion ........................................................... 11-5211-30 FIR Filter .................................................................. 11-5411-31 II R Filter (One Biquad) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-5611-32 IIR Filters (N > 1 Biquads) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-5911-33 Adaptive FIR Filter (LMS <strong>Al</strong>gorithm) ........................................... 11-6211-34 Matrix Times a Vector Multiplication ........................................... 11-6511-35 Complex, Radix-2, DIF FFT .................................................. 11-6811-36 Table With Twiddle Factors for a 64-Point FFT .................................. 11-7111-37. Complex, Radix-4, DIF FFT .................................................. 11-7311-38 Real, Radix-2 FFT .......................................................... 11-7911-39 Inverse Lattice Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-8411-40 Lattice Filter ............................................. ' . . . . . . . . . . . . . . . . . .. 11-86xxxi
xxxiiTable of Contents
Introduction
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Chapter 1IntroductionThe TMS320C3x generation of digital signal processors (DSPs) are high-performanceCMOS 32-bit floating-point devices in the TMS320 family ofsingle-chip digital signal processors. Since 1982, when the TMS3201 0 was introduced,the TMS320 family, with its powerful instruction sets, high-speednumber-crunching capabilities, and innovative architectures, established itselfas the industry standard and is ideal for DSP applications.The TMS320 family consists of five generations: TMS320C1 x, TMS320C2x,TMS320C3x, TMS320C4x, and TMS320C5x (see Figu re 1-1). The expansionincludes enhancements of earlier generations and more powerful new generationsof digital signal processors.1-1
IntroductionFigure 1-1. TMS320 Device EvolutionPERFoRMANCEMI p5I 'MFLoP5TMS320C1xTMS320C10TMS320C10-14/-25TMS320C14TMS320E 14/P14TMS320C 15/LC15TMS320E15/P15TMS320C15-25TMS320E15-25TMS'320C16TMS320C17/LC17TMS320E17/P17GENERATIONL:J Fixed-Point Generations~ Floating-Point GenerationsThe 50-ns cycle time of the TMS320C30-40 allows it to execute operations ata performance rate (up to 40 MFLOPS and 20 MIPS) previously available onlyon a supercomputer. The generation's performance is further enhanced, through its large on-chip memories, concurrent DMA controller, two externalinterface ports, and instruction cache.This chapter presents the following major topics:Q Processor General Description (Section 1.1 on page 1-3)[J Key Features (TMS320C30-Section 1.2 on page 1-5, TMS320C31-Section 1.3 on page 1-6)[J Typical Applications (Section 1.4 on page 1-7)1-2Introduction
;=;=;:;=;=;:;:;:;:;:;:;:;:~;:;:;:;:::::;:;:;:;:;:;:;:;:::;:::;:;:::;:;:::;:;:;:::::;:;:;:;:::::;::::.::::::::;:::::::::::::::;:::;~::::.::::.;.::;.;...;.;.;o.o....;••:;.:...;.;:::::;:; :;·~·;·;·;oh:;·;·;·;O;·;O:·;·,,;,;,;,.·;·;:;·::.·;·:::·;·;.:...:••••••• < .••.;.;...........;... ;~....•....;...;.;.;•••••.•.•;•••..;.;.;•••;General Description............. ;.;.;.;0;.;.;0; ..... ;.;.; ••• ; ..... ; ......... ;0 •••• ;. •• ;0 .... ;.;.;.;.;.;.;.;0,;.;.; ••• ;0;.; ... :.;.;.; .... ~ ••••••••••• ; ••••• ;.; ••••• ; ....... ; ••••••• ;.;:; ••••• ; ................................................................. ;.; ... ;o.;:;:; ••••• ;.;:::;.;.;.;:;o.:;:;o.:.:;:~1.1 General DescriptionThe TMS320's internal busing and special digital signal processing (DSP) instructionset have the speed and flexibility to execute up to 50 MFLOPS (millionfloating-point operations per second). The TMS320 family optimizes speed byimplementing functions in hardware that other processors implement throughsoftware or microcode. This hardware-intensive approach provides power previouslyunavailable on a single chip.The emphasis on total system cost has resulted in a less expensive processorthat can be designed into systems currently using costly bit-slice processors.<strong>Al</strong>so, cost/performance selection is provided by the different processors in theTMS320C3x line: .Q TMS320C30:Q TMS320C30-27:Q TMS320C30-40:Q TMS320C31:Q TMS320C31-27:60-ns single-cycle execution-timeLower-cost, 74-ns single-cycle execution timeHigher speed, 50-ns single-cycle execution timeLow cost, 60-ns single-cycle execution timeLower cost, 74-ns single-cycle execution time<strong>Al</strong>l of these processors are described in this user's guide. Essentially, theirfunctionality is the same. However, electrical and timing characteristics vary(described in Chapter 13); part numbering information is found in Section 8.4on page 8-15. Throughout this book, TMS320C3x is used to refer to theTMS320C30 and TMS320C31 and all speed variations. TMS320C30 andTMS320C31 are used to refer to all speed variants of those processors wherethat is appropriate. Special references, such as TMS320C30-40, are used tonote any specific exceptions.The TMS320C30 and TMS320C31 can perform parallel multiply and ALU operationson integer or floating-point data in a single cycle. The processor alsopossesses a general-purpose register file, program cache, dedicated auxiliaryregister arithmetic units (ARAU), internal dual-access memories, one DMAchannel supporting concurrent 110, and a short machine-cycle time. High performanceand ease of use are products of those features.General-purpose applications are greatly enhanced by the large addressspace, multiprocessor interface, internally and externally generated waitstates, two external interface ports (one on the TMS320C31), two timers, twoserial ports (one on the TMS320C31), and multiple interrupt structure. TheTMS320C3x supports a wide variety of system applications from host processorto dedicated coprocessor.High-level language is more easily implemented through a register-based architecture,large address space, powerful addressing modes, flexible instructionset, and well-supported floating-point arithmetic.Figure 1-2 is a functional block diagram that shows the interrelationships betweenthe various TMS320C3x key components.1-3
TMS320C31FeaturesFigure 1-2. TMS320C3x Block DiagramRDYHOLDHOLDASTRBRIWD31-0A23-0RESETINT3-olACKXF1-0 ...MCBUMP~eX1 c0X2/CLKIN0VDDVSSSHZRAM Block 0(1 K x 32)CPURAM Block 1(1K x 32)Integer/ Integer/ Address GeneratorsFloating-Point Floating-PointMultiplierALUControl Registers8 Extended-PrecisionRegistersAddress AddressGenerator 0 Generator 18 Auxiliary Registers12 Control RegistersAvailable onTMS320C30,TMS320C30-27 andTMS320C30-401-4Introduction
TMS320C30Features1.2 TMS320C30 Key FeaturesSome key features of the TMS320C30 are listed below.ElPerformance1 ) TMS320C30iii 60-ns single cycle instruction execution time11 33.3 MFLOPS (million floating-point operations per second)• 16.7 MIPS (million instructions per second)2) TMS320C30-27II 74-ns single cycle instruction execution timeII 27 MFLOPSII 13.5 MIPS3) TMS320C30-40• 50-ns single cycle instruction execution timeII 40 MFLOPSII 20 MIPS[J One 4K x 32-bit single-cycle dual-access on-chip ROM blockQ Two 1 K x 32-bit single-cycle dual-access on-chip RAM blocksQ 64 x 32-bit instruction cacheQ 32-bit instruction and data words, 24-bit addressesQ 40/32-bit floating-point/integer multiplier and ALUQ 32-bit barrel shifterQ Eight extended-precision registers (accumulators)Q Two address generators with eight auxiliary registers and two auxiliaryregister arithmetic unitsQ On-chip direct memory access (OMA) controller for concurrent I/O andCPU operationQ Integer, floating-point, and logical operationsQ Two- and three-operand instructionsQ Parallel ALU and multiplier instructions in a single cycleQ Block repeat capabilityQ Zero-overhead loops with single-cycle branchesQ Conditional calls and returnsQ Interlocked instructions for multiprocessing supportQ Two 32-bit data buses (24- and 13-bit address)Q Two serial ports to support 8/16/24/32-bit transfersQ Two 32-bit timersQ Two·general-purpose external flags, four external interruptsQ181-pin grid array (PGA) package; 1-Jlm CMOS'1-5
TMS320C31Features1.3 TMS320C31 Key FeaturesThe TMS320C31 and TMS320C31-27 devices are low-cost 32-bit DSPs thatoffer the advantages of a floating-point processor and ease of use. These devicesare object-code compatible with the TMS320C30. The devices are functionallyequivalent and differ only in their respective electrical and timing characteristics.Chapter 13 describes these differences in detail.TMS320C31 features are identical to those of the TMS320C30 device, exceptthat the TMS320C31 uses a subset of the TMS320C30's standard peripheraland memory interfaces-thus maintaining the TMS320C30 core CPU33-MFLOP performance while providing the cost advantages associated with132-pin plastic quad flat pack (PQFP) packaging.The TMS320C31-27 is a slower speed, pin and object-code compatible versionof the TMS320C31. It delivers 27 MFLOPS (million floating-point operationsper second) and runs at 27 MHz. The reduced speed allows you to realizean immediate system cost reduction by using slower off-chip memories and alower cost processor.Some key features of the TMS320C31, including those which differentiate itfrom the TMS320C30, are summarized as follows:QPerformance• TMS320C31• 60-ns single-cycle instruction execution time• 33.3 MFLOPS• 16.7 MIPS (million instructions per second)• TMS320C31-27• 74-ns single-cycle instruction execution time• 27 MFLOPS• 13.5 MIPSQQFlexible boot program loaderOne serial port to support 8/16/24/32-bit transfersQ . One 32-bit data bus (24-bit address)Q132-pin plastic quad flat pack (PQFP) package, .8 J.lm CMOS1-6Introduction
Typical Applications1.4 Typical ApplicationsThe TMS320 family's versatility, realtime performance, and multiple functionsoffer flexible design approaches in a variety of applications, which are shownin Table 1-1.Table 1-1. Typical Applications of the TMS320 FamilyGeneral-Purpose DSP Graphics/Imaging I nstrumentati onDigital Filtering 3-D Transformations Rendering Spectrum AnalysisConvolution Robot Vision Function GenerationCorrelation Image Transmission/Compression Pattern MatchingHilbert Transforms Pattern Recognition Seismic ProcessingFast Fourier Transforms Image Enhancement Transient AnalysisAdaptive Filtering Homomorphic Processing Digital FilteringWindowing Workstations Phase-Locked LoopsWaveform GenerationAnimation/Digital MapVoice/Speech Control MilitaryVoice Mail Disk Control Secure CommunicationsSpeech Vocoding Servo Control Radar ProcessingSpeech Recognition Robot Control Sonar ProcessingSpeaker Verification Laser Printer Control Image ProcessingSpeech Enhancement Engine Control NavigationSpeech Synthesis Motor Control Missile GuidanceText-to-Speech Kalman Filtering Radio Frequency ModemsNeural NetworksSensor FusionTelecommunicationsAutomotiveEcho Cancellation FAX Engine ControlADPCM Transcoders Cellular Telephones Vibration AnalysisDigital PBXs Speaker Phones Antiskid BrakesLine Repeaters Digital Speech Adaptive Ride ControlChannel Multiplexing Interpolation (DSI) Global Positioning1200- to 19200-bps Modems X.2S Packet Switching NavigationAdaptive Equalizers Video Conferencing Voice CommandsDTMF Encoding/Decoding Spread Spectrum Digital RadioData Encryption Com mu nications Cellular TelephonesConsumer Industrial MedicalRadar Detectors Robotics Hearing AidsPower Tools Numeric Control Patient MonitoringDigital Audio/TV Security Access Ultrasound EquipmentMusic Synthesizer Power Line Monitors Diagnostic ToolsToys and Games Visual Inspection ProstheticsSolid-State Answering Lathe Control Fetal MonitorsMachines CAM MR Imaging1-7
1-8 Introduction
~ ______ A_r_c_h_it_e_c_tu_r_a_I_O_v_e_r_v_ie_w __________________________________ ='f=HIIIII
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Chapter 2Architectural OverviewThe TMS320C3x architecture (shown in Figure 2-1) responds to systemdemands that are based on sophisticated arithmetic algorithms and which emphasizeboth hardware and software solutions. High performance is achievedthrough the precision and wide dynamic range of the floating-point units, largeon-chip memory, a high degree of parallelism, and the DMA controller.Major areas of discussion are listed below.Q Central Processing Unit (CPU) (Section 2.1 on page 2-3)• Floating-point/integer multiplier• ALU for floating-point, integer, and logical operations• 32-bit barrel shifter• Internal buses (CPU1/CPU2 and REG1/REG2)• Auxiliary register arithmetic units (ARAUs)• CPU register fileQ Memory Organization (Section 2.2 on page 2-9)• RAM, ROM, and cache• Memory maps• Memory addressing modes• Instruction set summaryQ Internal Bus Operation (Section 2.3 on page 2-22)a External Bus Operation (Section 2.4 on page 2-23)Q Peripherals (Section 2.5 on page 2-24)• Timers• Serial portsQ Direct Memory Access (DMA) (Section 2.6 on page 2-26)Q System Integration (Section 2.7 on page 2-27)2-1
Architectural OverviewFigure 2-; 1. TMS320C3x Block DiagramCACHE(64X32)RAMBlock 0(1KX32)RAMBlock 1(1KX32)32r,:"RDY -tHOLD -tHOLDA4- kSTRB 4-r-.-IRiW4- I "D31-DO ..A23-AO 4--I32 1. ,24 32 24 24 32 '::-DMA ControllerSerial Port 0r""'jR~fRESE~-+ ..........INT3~-+IACK4-MC/MP-+XF(1,0)"VDD(3-0)-+IODVDD(1 ,0)-+ADVDD(1,O)-+PDVDD-+DDVDD(1,0) -.MDVDD-'VSS(3-0)-.DVSS(3-D) -.CVSS(1,0)-+IVSS-+VBBp4-SUBS-+X14-X2/CLKIN-+H14-H34-EMU6-0 ..RSV10-o .. _CoNTRoLLERLMUXl Multiplier32-BitBarrelShifter~~l~Global Control,RegisterSource AddressRegisterDestinationAddressRegisterTransferCounterRegister40 tALU f--40403240 'r+-f-+Port Control ... FSXO~ ___ R_eg_i_st_er __ ~ .. DXORlX Timer ... CLKXO~ ___ R_eg_is_t_er __ ~ ... FSROData Transmit ~ DRORegister .. CLKROI------fData ReceiveRegister,''Senal' 86rV1,,'r+- 1::>:::::,Pbrt"CO~lrOI/' ,/,/
Central Processing Unit (CPU);0;-)';:::::;:;:::::::;:;:;:::;:::;:;:;:::;:;:;:::;:;:;:::;:::::;:::;:;:::::;:;:;:;:;:;:;:::;:;:;:::::::::::::::;:~:::;:;:;:;:;:;:::;:~.:::::::;:::;'::;:::;:;o;:::;.;:;:.:::::::::;:::;o;.;:;:..;...;0;,,';';:::;:::::::::::::;0;';';0;';0;0;0:';':';0;0;:;'::;:;:;';';:;';:;';'::;';',';:;0;';:;:;:::;:::;';';';0;';';0;';0;0;'::":,;,:';:;';0:';':':';''';',';0;0»;0;0;';:;:::;:;':';';';';';0;0;0;';':';';';',';:::::;';:;0;:;';';0;0;';0;';';';0;';';0;0;';':::';0;0••••;0;.;•••;0;0;.......;...,::;•••;0::;.;...;0;•••;.;0;0;.».;.;0;0;·;·;o::::::::;:;:::::;:::::::;:::;:::;o;:::;:::::;o».;o;~:::::;:;:~;sFigure 2-2. Central Processing Unit (CPU)Multiplier40ExtendedPrecisionRegisters(RO-R?)404032OtherRegisters(12) _32* Disp = an 8-bit integer displacement carried in a program control instruction2-4 Architectural Overview
Central Processing Unit (CPU);:::;=:*;:::;:;:::::::::::;o;:;:;:;:;o;:::::::-~:;%::=;::,::::-.:::=:::-~;:;:;:;:::;:;:;:;:;:;: ;:~:::::::::x::::::::;:::;.:;:;:;:;::*;x:::::;:;:::::::::::;:;::::::: ::::::;:::::::4!~::;::*
Central Processing Unit (CPU):::::::::::::;:::;:::::::::;:::::.~:;:::;O:::o:::;:::;:;::::::::::::~ ..:::::::;:::::;:;:::;:;:::::;:::::::::;:::::::::::::::::::;:::;:::::;:;:,::::::::::::;:::;:::;::::::,,,').,;::::%..:::::::::::;:;..::::::..::::.::::;::.;.:::..:;::::::.:.... ~:::::~~:::.;.:.:.:.~ ..::.:.:.:~:.::;:;.:.::;.;.~:::::::.:.:.:.;::.:..:::::;.;,...:::.;.:.:.:~::.~:.,;.;.:::::::::::.;.::;::.;.;.;.:.;.;..·;·:·:·:·;·~::.. :::::::::;:::;:~;::.,;·:·:·:·;v:::.;::::::.;.-:·: ·;..:;·:..·:.;....::.;::..::..:::;..:~;·:::.;::...... :::;~s::::::~::::::::~::;:::;:;>"!;..;:::;::::~~::;::sThe repeat counter (RC) is a 32-bit register used to specify the number oftimes a block of code is to be repeated when performing a block repeat. Whenthe processor is operating in the repeat mode, the 32-bit repeat start addressregister (RS) contains the starting address of the block of program memoryto be repeated, and the 32-bit repeat end address register (RE) contains theending address of the block to be repeated.The program counter (PC) is a 32-bit register containing the address of thenext instruction to be fetched. <strong>Al</strong>though the PC is not part of the CPU registerfile, it is a register that can be modified by instructions that modify the programflow.2-8Architectural Overview
Memory Organization>;:;:;::?):;!;!::l:::~"y'O:::"«";!";:;:;:::?O?;~;:::::"'::::"'::::::::;Y;:~::::-o':::.:".(6!::::;:::::::::::;:;:-~»'~~~':::9,~::::":9/;?;.o::».::;xY.O';O;:::::::::";·::;:":·";::::::: ..;:::;:>.;?;::-::::::::;:::;:..; ...;:;.;:;.::;o;v.;..::;v..:.....::..::-..::;.;.;:;:>.;:;y;:;o;.::..::>.::::...::;:;o;.::~::::..;o......;y;o;o;o..;o.. ;om.;:>.~;o:....... :.~;:;y::::::;:;:;o».;o».::~::;..;so::;:;'::~,"'M""',"""""~;:OO"~:>';O;o;o.6:~:>'~o':;:O:::;';:.:::::;:::.:>.~:::>.::2.2 Memory OrganizationThe total memory space of the TMS320C3x is 16M (million) 32-bit words. Program,data, and I/O space are contained within this 16M-word address space,thus allowing tables, coefficients, program code, or data to be stored in eitherRAM or ROM. In this way, memory usage is maximized and memory space allocatedas desired.2.2.1 RAM, ROM, and CacheFigure 2-3 shows how the memory is organized on the TMS320C3x. RAMblocks 0 and 1 are each 1 K x 32 bits. The ROM block, available only on theTMS320C30, is 4K x 32 bits. Each RAM and ROM block is capable of supportingtwo CPU accesses in a single cycle. The separate program buses, databuses, and DMA buses allow for parallel program fetches, data reads andwrites, and DMA operations. For example: the CPU can access two data valuesin one RAM block and perform an external program fetch in parallel withthe DMA loading another RAM block, all within a single cycle.A 64 x 32-bit instruction cache is provided to store often repeated sections ofcode, thus greatly reducing the number of off-chip accesses necessary. Thisallows for code to be stored off-chip in slower, lower-cost memories. The externalbuses are also freed for use by the DMA, external memory fetches, or otherdevices in the system.Refer to Chapter 3 for detailed information about the memory and instructioncache.2-9
Memory Organization::;~:o::o:;:;?;:"o:;~;:;:::;:::::.;:o::::-.::::::::::;:;?;:::::::;:;:;:::::::: :::::;:::::::;O:::;:;::O:;::O:;?'~;:~:;y';:::::;:::;:;:;:::::;::.;.;:;:;o.;:;:;:;:::;:::;:;·:o:~;·;:::;:;:::;?::::;o;:h:;:;·;·;:;:;:;::·;·; :;:;.;y.;:::;:;:;:;::.::;:;:;:;.:::.;:;.;:.:;:::;::~;o::::;::::::.;.;.::;.;.;::.;.;:::;::••:0:;:;::.:.;.;:;::.;:::;.;::....:::••·;·:·;·;·;·;·;.;:.·;·;:;...·.:;·.·;:;s:;·;·;o;:;:;::·;·.·;::.;:::;:"':;:";';';:::;:;"';':.;.;:;:;:;:;:::;:;:;:.:;:~:;:;:&;:.:;:.:::.:.:.:.:.:.:0:•.,,',:.:.:.:.:.:&... :;:.:.:.:.:.:.:::&.:.:,:.:O:";'o:.:.:.?;:;:.:.:.~:;:;:;:::;:;:6::Y'::2.2.2 Memory MapsThe memory map is dependent upon whether the processor is running in themicroprocessor mode (MC/MP or MCBUMP = 0) or the microcomputer mode(MC/MP or MCBUMP = 1). The memory maps for these modes are similar (seeFigure 2-4). Locations 800000h through 801 FFFh are mapped to the expansionbus. When this region, available only on the TMS320C30, is accessed,MSTRB is active. Locations 802000h through 803FFFh are reserved. Locations804000h through 805FFFh are mapped to the expansion bus. When thisregion, available only on the TMS320C30, is accessed, IOSTRB is active. Locations806000h through 807FFFh are reserved. <strong>Al</strong>l of the memory-mappedperipheral registers are in locations 808000h through 8097FFh. In both modes,RAM block 0 is located at addresses 809800h through 809BFFh, and RAMblock 1 is located at addresses 809COOh through 809FFFh. Locations80AOOOh through OFFFFFFh are accessed over the external memory port(STRB active).In microprocessor mode, the 4K on-chip ROM (TMS320C30) or bootloader(TMS320C31) is not mapped into the TMS320C3x memory map. Locations Ohthrough OBFh consist of interrupt vector, trap vector, and reserved locations,all of which are accessed over the external memory port (STRB active). LocationsOCOh through 7FFFFFh are also accessed over the external memoryport.In microcomputer mode, the 4K on-chip ROM (TMS320C30) or bootloader(TMS320C31) is mapped into locations Oh through OFFFh. There are 19210cations(Oh through OBFh) within this block for interrupt vectors, trap vectors, anda reservj3d space. Locations 1 OOOh through 7FFFFFh are accessed over theexternal memory port (STRB active).Section 3.2 describes the memory maps in greater detail. The peripheral busmap and the vector locations for reset, interrupts, and traps are also given.l3ecareful !Access to· a reserved area produces unpredictablere~suits.2-11
Memory OrganizationFigure 2-4. TMS320C30 Memory MapsOhOBFhOCOh7FFFFFh800000h801FFFh802000h803FFFh804000h805FFFh806000h807FFFh808000hInterrupt Locationsand Reserved (192)External STRB ActiveExternalSTRB Active~nsionBusMSTRB Active (8K)Reserved(8K)~sionBusIOSTRB Active (8K)Reserved(8K)OhOBFhOCOhOFFFh1000h7FFFFFh800000h801FFFh802000h803FFFh804000h805FFFh806000h807FFFh808000hInterrupt Locationsand Reserved (192)~---------ROM(Internal)ExternalSTRB Active~nsionBusMSTRB Active (8K)Reserved(8K)~sionBusIOSTRB Active (8K)Reserved(8K)Peripheral BusMemory-MappedRegisters(Internal) (SK)Peripheral BusMemory-MappedRegisters(Internal) (SK)8097FFh809800h809BFFh809COOh809FFFh80AOOOhOFFFFFFhRAM Block 0(1 K) (Internal)RAM Block 1(1 K) (Internal)ExternalSTRB Active8097FFh809800h809BFFh809COOh809FFFh80AOOOhOFFFFFFhRAM Block 0(1 K) (Internal)RAM Block 1(1 K) (Internal)ExternalSTRB Active(a) Microprocessor Mode(b) Microcomputer Mode2-12Architectural Overview
Memory Organization~.::;:(:e~:;."W:~.:::s:~:::;: .. s!~:;.:;:O:"''':>::::::s..~:: .. o;ss::,,*:ss:~::::::;~;sx:;:>.v.::;:::~.;~:. .. ~::::Figure 2-5. TMS320C31 Memory MapsOhOBFhOCOhInterrupt Locationsand Reserved (192)(External STRB Active)OhReserved for BootLoader Operations(See Section 3.4)ExternalSTRB ActiveFFFh1000h400000h EJ Boot 2))1ExternalSTRBActive7FFFFFh800000h807FFFh808000h8097FFh809800h809BFFh809COOh809FFFh80AOOOhFFFFFFhReserved(32K Words)Peripheral BusMemory-MappedRegisters(6K Internal)RAM Block 0(1 K Internal)RAM Block 1(1 K Internal)ExternalSTRB Active7FFFFFh800000h807FFFh808000h8097FFh809800h809BFFh809COOh809FCOh80A9F1h809FFFh80AOOOhFFFOOOhFFFFFFhReserved(32K Words)Peripheral BusMemory-MappedRegisters(6K Internal)RAM Block 0(1 K Internal)RAM Block 1(1 K-64 Internal)User Program Interruptand Trap Branches(64 Internal)(a) Microprocessor Mode(b) Microcomputer/Boot Loader Mode2-13
Memory Organization.... :::;:::;~:::;:;~;,:::::::::::::::::::::::::::::%::::::::::o;:$:;:;.:;:::::::::::;:::;:::::::::::".:~:::"-::::::::::::%::::::::::f.5::::n::::~:::::~::::::::::::"Q~::y.,::::::::~::::::::~"X:::::::::::".:::::::::::::::::::."!'.:::::::::::::::::.~:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::f.5:::::"'('::::::~~::~~::::::::'::::::::::::::::::::::::::::::::::;:-.. '4!:::::::::::::9,;:::::::::;::::ss::%:;:;::::..o,;y'.(.y.::%~%:::-)'"*:'''f.5m::>"S::~-m::~ .. ~s::.::s:;:;:;.:~:::::s2.2.3 Memory Addressing ModesThe TMS320C3x supports a base set of general-purpose instructions as wellas arithmetic-intensive instructions that are particularly suited for digital signal. processing and other numeric-intensive applications. Refer to Chapter 5 fordetailed information on addressing.Five groups of addressing modes are provided on the TMS320C3x. Six typesof addressing may be used within the groups, as shown in the following list:l;i General addressing modes:• Register. The operand is a CPU register.• Short immediate. The operand is a 16-bit immediate value.• Direct. The operand is the contents of a 24-bit address.• Indirect. An auxiliary register indicates the address of the operand.QThree-operand addressing modes:• Register. Same as for general addressing mode.• Indirect. Same as for general addressing mode.QParallel addressing modes:• Register. The operand is an extended-precision register.• Indirect. Same as for general addressing mode.l;i Long-immediate addressing mode.• Long-immediate. The operand is a 24-bit immediate value.QConditional branch addressing modes:• Register. Same as for general addressing mode• PC-relative. A signed 16-bit displacement is added to the PC.2.2.4 Instruction Set SummaryTable 2-2 lists the TMS320C3x instruction set in alphabetical order. Each tableentry shows the instruction mnemonic, description, and operation. Refer toChapter 10 for a functional listing of the instructions and individual instructiondescriptions.2-14Architectural Overview
Memory OrganizationTable 2-2. Instruction Set SummaryMnemonicABSFABSIADDCADDC3ADDFADDF3ADDIADDI3ANDAND3ANDNANDN3ASHASH3BcondBcondDDescriptionAbsolute value of a floating-point numberAbsolute value of an integerAdd integers with carryAdd integers with carry (3-operand)Add floating-point valuesAdd floating-point values (3-operand)Add integersAdd integers (3-operand). Bitwise logical-ANDBitwise logical-AND (3-operand)Bitwise logical-AND with complementBitwise logical-ANON (3-operand)Arithmetic shiftArithmetic shift (3-operand)Branch conditionally (standard)Branch conditionally (delayed)Isrcl ~ RnIsrcl ~ DregOperationsrc + Dreg + C ~ Dregsrc1 + src2 + C ~ Dregsrc + Rn ~ Rnsrc1 + src2 ~ Rnsrc + Dreg ~ Dregsrc1 + src2 + ~ DregDreg AND src ~ Dregsrc1 AND src2 ~ DregDreg AND src ~ Dregsrc1 AND src2 ~ DregIf count ~ 0:(Shifted Dreg left by count) ~ DregElse:(Shifted Dreg right by Icount!) ~ DregIf count ~ 0:(Shifted src left by count) ~ DregElse:(Shifted src right by Icount!) ~ DregIf cond = true:If Csrc is a register, Csrc ~ PCIf Csrc is a value, Csrc + PC ~ PCElse, PC + 1 ~ PCIf cond = true:If Csrc is a register, Csrc ~ PCIf Csrc is a value, Csrc + PC + 3 ~ PCElse,PC + 1 ~ PCLEGEND:srcsrc1src2CsrcSregcountSPGIERMTOSgeneral addressing modesthree-operand addressing modesthree-operand addressing modesconditional-branch addressing modesregister address (any register)shift value (general addressing modes)stack pointerglobal interrupt enable registerrepeat mode bittop of stackDregRnDaddrARnaddrcondSTRERSPCCregister address (any register)register address (R7 - RO)destination memory addressauxiliary register n (AR7 - ARO)24-bit immediate address (label)condition code (see Chapter 11)status registerrepeat interrupt registerrepeat start registerprogram countercarry bit2-15
Memory Organization:e:s:;:"q,;~q-...:;m:;-:::,.:;:".::Y..::m:::::,~:::::::::,.s::::-::~~@~:;$::::w.~:::;::~d/..::%~?:mx~(.(.::~~.:",(~~.w.a~:,a:::.~~~:::,.. ~h.:::Y..w.~Q.::,.::~~~.(.:,.::~:~.(.(~::::,aaQ.:",(.(Q.»."('::w..(.(.(.(.~~~'(':''(~L'('('::9/.~S:;:~'('('~;:::'i''.(,~~~;::':'':~Q.::'«'::~:;~Q.(.:;m-::,:,.s:;~...:;::ss:;~:,.(.w~~Table 2-2.Instruction Set Summary (Continued)Mnemonic Description OperationBR Branch unconditionally (standard) Value~ PCBRO, Branch unconditionally (delayed) Value~ PCCALL Call subroutine PC+1 ~TOSValue~ PCCALLcond Call subroutine conditionally If cond = true:PC+1 ~ TOSIf Csrc is a register, Csrc ~ PCIf Csrc is a value, Csrc + PC ~ PCElse, PC + 1 ~ PCCMPF Compare floating-point values Set flags on Rn - srcCMPF3 Compare floating-point values Set flags on src1 - src2(3-operand)CMPI Compare integers Set flags on Dreg - srcCMPI3 Compare integers (3-operand) Set flags on src1 - src2DBcond Decrement and branch conditionally ARn-1 ~ ARn(standard)If cond = true and ARn ~ 0:If Csrc is a register, Csrc ~ PCIf Csrc is a value, Csrc + PC + 1 ~ PCElse, PC + 1 ~ PCDBcondD Decrement and branch conditionally ARn-1 ~ARn(delayed)If cond = true and ARn ;::: 0:If Csrc is a register, Csrc ~ PCIf Csrc is a value, Csrc + PC + 3 ~ PCElse, PC + 1 ~ PCFIX Convert floating-point value to integer Fix (src) ~ DregFLOAT Convert integer to floating-point value Float(src) ~ RnlACK Interrupt acknowledge Dummy read of srclACK toggled low, then highIDLE Idle until interrupt PC+ 1 ~ PCIdle until next interruptLDE Load floating-point exponent src(exponent) ~ Rn(exponent)LDF Load floating-point value src~ RnLDFcond Load floating-point value conditionally If cond = true, src ~ RnElse, Rn is not changedLDFI Load floating-point value, interlocked Signal interlocked operation src ~ RnLDI Load integer src~ DregLDlcond Load integer conditionally If cond = true, src ~ DregElse, Dreg is not changed2-16 Architectural Overview
Table 2-2.Il?struction Set Summary (Continued)Mnemonic Description OperationPUSHF Push floating-point value on stack Rn -7 *++ SPRETlcond Return from interrupt conditionally If cond = true or missing:*SP---7 PC1 -7 ST (GIE)Else, continueRETScond Return from subroutine conditionally If cond = true or missing:*SP---7 PCElse, continueRND Round floating-point value Round (src) -7 RnROL Rotate left Dreg rotated left 1 bit -7 DregROLC Rotate left through carry Dreg rotated left 1 bit through carry -7 DregROR Rotate right Dreg rotated right 1 bit -7 DregRORC Rotate right through carry Dreg rotated right 1 bit through carry -7DregRPTB Repeat block of instructions src -7 RE1 -7 ST (RM)Next PC -7 RSRPTS Repeat single instruction src -7 RC1 -7 ST (RM)Next PC -7 RSNext PC -7 RESIGI Signal, interlocked Signal interlocked operationWait for interlock acknowledgeClear interlockSTF Store floating-point value Rn -7 DaddrSTFI Store floating-point value, interlocked Rn -7 DaddrSignal end of interlocked operationSTI Store integer Sreg -7 DaddrSTII Store integer, interlocked Sreg -7 DaddrSignal end of interlocked operationSUBB Subtract integers with borrow Dreg - src - C -7 DregSUBB3 Subtract integers with borrow (3-operand) src1 - src2 - C -7 DregSUBC Subtract integers conditionally If Dreg - src ;:: 0:[(Dreg - src) « 1) OR 1 -7 DregElse, Dreg « 1 -7 Dreg2-18 Architectural Overview
Table 2-3. Parallel Instruction Set SummaryMnemonic j Description1OperationParallel Arithmetic With Store InstructionsABSF Absolute value of a floating-point Isrc21 ~ dst1IISTFII src3 ~ dst2ABSI Absolute value of an integer Isrc21 ~ dst1IISTIII src3 ~ dst2ADDF3 Add floating-point src1 + src2 ~ dst1II STFII src3 ~ dst2ADDI3 Add integer src1 + src2 ~ dst1II STIII src3 ~ dst2AND3 Bitwise logical-AND src1 AND src2 ~ dst1IISTIII src3 ~ dst2ASH3 Arithmetic shift If count;;::: 0:IISTIsrc2 « count ~ dst1II src3 ~ dst2Else:src2 » Icountl ~ dst1II src3 ~ dst2FIX Convert floating-point to integer Fix(src2) ~ dst1IISTIII src3 ~ dst2FLOAT Convert integer to floating-point Float(src2) ~ dst1IISTFII src3 ~ dst2LDF Load floating-point src2 ~ dst1IISTFII src3 ~ dst2LDI Load integer src2 ~ dst1IISTIII src3 ~ dst2LSH3 Logical shift If count;;::: 0:IISTIsrc2 « count ~ dst1II src3 ~ dst2Else:src2 » Icountl ~ dst1II src3 ~ dst2MPYF3 Multiply floating-paint src1 x src2 ~ dst1IISTFII src3 ~ dst2MPYI3 Multiply integer src1 x src2 ~ dst1IISTIII src3 ~ dst2NEGF Negate floating-point 0- src2 ~ dst1II STFII src3 ~ dst22-20 Architectural Overview
Internal Bus UJ)leralrion2.3 Internal Bus OperationA large portion of the TMS320C3x's high performance is due to internal busingand parallelism. The separate program buses (PADDR and PDATA) , databuses (DADDR1, DADDR2, and DDATA), and DMA buses (DMAADDR andDMADATA) allow for parallel program fetches, data accesse~, and DMA accesses.These buses connect all of the physical spaces (on-chip memory,off-chip memory, and on-chip peripherals) supported by the TMS320C30.Figure 2-3 shows these internal buses and their connection to on-chip and offchipmemory blocks.The program counter (PC) is connected to the 24-bit program address bus(PADDR). The instruction register (IR) is connected to the 32-bit program databus (PDATA). These buses can fetch a single instruction word every machinecycle.The 24-bit data address buses (DADDR1 and DADDR2) and the 32-bit datadata bus (DDATA) support two data memory accesses every machine cycle.The DDATA bus carries data to the CPU over the CPU1 and CPU2 buses. TheCPU1 and CPU2 buses can carry two data memory operands to the multiplier,ALU, and register file every machine cycle. <strong>Al</strong>so internal to the CPU are registerbuses REG1 and REG2 that can carry two data values from the register fileto the multiplier and ALU every machine cycle. Figure 2-2 shows the busesinternal to the CPU section of the processor.The DMA controller is supported with a 24-bit address bus (DMAADDR) anda 32-bit data bus (DMADATA). These buses allow the DMA to perform memoryaccesses in parallel with the memory accesses occurring from the data andprogram buses.2-22Architectural Overview
External Bus []DI~r,qlfi{)n2.4 External Bus OperationThe TMS320C30 provides two external interfaces: the primary bus and the expansionbus. The TMS320C31 provides one external interface: the primarybus. Both primary and expansion buses consist of. a 32-bit data bus and a setof control signals. The primary bus has a 24-bit address bus, whereas the expansionbus has a 13-bit address bus. Both buses can be used to address externalprogram/data memory or I/O space. The buses also have an externalROY signal for wait-state generation. Additional wait states may be insertedunder software control. Refer to Chapter 7 for detailed information on externalbus operation.2.4.1 External InterruptsThe TMS320C3x supports four external interrupts (iNf3-INTO), a number ofinternal interrupts, and a nonmaskable external RESET signal. These can beused to interrupt either the DMA or the CPU. When the CPU responds to theinterrupt, the lACK pin can be used to signal an external interrupt acknowledge.Section 6.5 (beginning on page 6-16) cover RESET and interrupt processing.2.4.2 Interlocked-Instruction SignalingTwo external I/O flags, XFO and XF1 , can be configured as input or output pinsunder software control. These pins are also used by the interlocked operationsof the TMS320C3x. The interlocked-operations instruction group supportsmultiprocessor communication (see Section 6.4 on page 6-10 for examples ofthe use of interlocked instructions).2-23
".Peripherals'2.5 Peripherals<strong>Al</strong>l TMS320C3x peripherals are controlled through memory-mapped registerson a dedicated peripheral bus. This peripheral bus is composed of a 32-bit databus and a 24-bit address bus. This peripheral bus permits straightforward communicationto the peripherals. The TMS320C3x peripherals include two timersand two serial ports (only one serial port is available on the TMS320C31).Figure 2-6 shows the peripherals with associated buses and signals. Refer toChapter 8 for detailed information on the peripherals.Figure 2-6. Peripheral ModulesM SE PM Ao CR EYCI"""PERIPHER<strong>Al</strong>0ATABUSf+- '.'"\Jvf+-.............Serial Port 0..--.- Port Control RegisterPERIPHE-+- RALA00RES-+- S'.,BUS'. ....R/X Timer RegisterData Transmit RegisterData Receive Register~ : .>:,..:,":::::>:::>::::: ~~,ri~'1 ~o.rt .1' ,.:::"':"""':'::"":,:>::,I:::::::::::::::::::, ,., ...... ,"" ,.,.....,/ .... ,.' ,,.. ...,,,,' ,:::::,..:::",:~,~~::·~:~~t,~~~,,:~,~~:~:~~:~~,::'::::::::':: :::::1,:::::::::::::::::::::,,:R!X,,~,m,~r}~~~.ls~.e
Direct Memory Access (DMA)2.6 Direct Memory Access (DMA)Figure 2-7. DMA ControllerThe on-chip Direct Memory Access (DMA) controller can read from or write toany location in the memory map without interfering with the operation of theCPU. Therefore, the TMS320C3x can interface to slow external memories andperipherals without reducing throughput to the CPU~ The DMA controller containsits own address generators, source and destination registers, and transfercounter. Dedicated DMA address and data buses allow for minimization ofconflicts between the CPU and the DMA controller. A DMA operation consistsof a block or single-word transfer to or from memory. Refer to Chapter 8 for detailedinformation on the DMA. Figure 2-7 shows the DMA controller with associatedbuses./ ...••... DMADATA Bus ........... ;~ /'E P.. /'~ R EI Rp I../';:.. HpE HR EA RL A-.:,/'"LDMA ControllerDA AT DGlobal Control Register A DR~ "\ ESource Address RegisterB~ -I u SDestination AddressS S/ LDMAADDR·Bus·· .. ;Register ./ 8ATransfer Counter Register V UI\.S~V2-26 Architectural Overview
2-28 Architectural Overview
~ ______ C_p_u_R __ e_g_is_te_r_s_,_M_e_m_o_~ __,_a_nd__ C_a_C_h_e ____________________ ~'f__ 111111
CPU Registers, Memory, and Cache"-------------'
CPU Register File;O;=~:::'::'::::;:~::::::;:;:::;O;:;':;:::::::>::::9.::::::;:::::::::::;:::::::::::::;:;:;:::::;:::;:;:;:;:;:::::::~:::;::y.~::;:;:::;:::;:::::;:: :::::::;::-::,':::::::::9,:::::9,;-:::::::-;6'*»'::::::::::::;9,::::::::;-::::;-;:::::;:;:::*;:::::;:;:::::;':::-:::';-::;-;-»::,'::::::::;::'::::;:::::::;-;::~~;-~;::::·";:;Y,;~::;·;·N;-;·;·:·::.·::.:::;·.·:: .·:·..:....•..;...;..·:·:·;·;::·::;::..·;-::~::::;y::x:::;:::::;·;·.:::.·*~·;9.*.:~:::;::9..:::;::w.;y":O?;>Y».::*":O~:::.:::Mo:;:::::::::::;~;:::::;::::="'):;-~:::::::::~3.1 CPU Register FileThe TMS320C3x provides 28 registers in a multiport register file that is tightlycoupled to the CPU. The PC is not included in the 28 registers. <strong>Al</strong>l of these registerscan be operated upon by the multiplier and ALU, and can be used as general-purpose32-bit registers. However, the registers also have some specialfunctions for which they are particularly appropriate. For example, the eight extended-precisionregisters are especially suited for maintaining extended-precisionfloating-point results. The eight auxiliary registers support a variety ofindirect addressing modes and can be used as general-purpose 32-bit integerand logical registers. The remaining registers provide system functions suchas addressing, stack management, processor status, interrupts, and block repeat.Refer to Chapter 5 for detailed information and examples of the use ofCPU registers in addressing.The registers names and assigned function are listed in Table 3-1.Table 3-1. CPU RegistersRegisterAssigned Function NameRO Extended-precision register 0R1 Extended-precision register 1R2 Extended-precision register 2R3 Extended-precision register 3R4 Extended-precision register 4R5 Extended-precision register 5R6 Extended-precision register 6R7 Extended-precision register 7AROAuxiliary register aAR1 Auxiliary register 1AR2 Auxiliary register 2AR3 Auxiliary register 3AR4 Auxiliary register 4AR5 Auxiliary register 5AR6 Auxiliary register 6AR7 Auxiliary register 7DPData-page pointerIRO Index register 0IR1 Index register 1BKBlock-size registerSPSystem stack pointerSTIEIF10FRSRERCPCStatus registerCPU/DMA interrupt enableCPU interrupt flagsI/O flagsRepeat start addressRepeat end addressRepeat counterProgram counter3-3
CPU Register File~:".(.:=:;O'::::::"':::::::~::"'::::~-::::::::::o:::'!;:~.:m::::::%!::::::::;:::::;:::::-~:::=::::::~;:::;:::;:O::::::::::::~::::;:::::::~-::9.~.:;::::%~:".:.'!;:::::::::O:::::;9.::::l:::::~:;::::::o;:::".(.::::::::::::::::::::? .."!om:::::~::~::::;:;:::::::::::::::=:;::::::::~::::w.-::9.:y.;:::::-'!;:;:::~::::?7..(.:::::;:-.(.:;::~Q.:::::~'!~;:::::".:::::-'!;:;:::;::::::::::::::::::::::::::::::::::':::::::::::::::::::::::::::::::::$"$.::::".:X:;:::;7.;:;::~::::::::::::%::::::::::»'!:::,::::;~::::--:::::,-::::::w.::;s3.1.1 Extended-Precision Registers (R7 - RO)The eight extended-precision registers (R7 - RO) are capable of storing andsupporting operations on 32-bit integer and 40-bit floating-point numbers.These registers consist of two separate and distinct regions:a bits 39 -number.32: dedicated to storage of the exponent (e) of the floating-pointa bits 31 -0: store the mantissa of the floating-point number:• bit 31: sign bit (s),• bits 30 - 0: the fraction (f).Any instruction that assumes the operands are floating-point numbers usesbits 39 - O. Figure 3-1 illustrates the storage of 40-bitfloating-point numbersin the extended-precision registers.Figure 3-1. Extended-Precision Register Floating-Point Format39 32 31 30 0fraction (f)I IIeIs~ mantissa .1For integer operations, bits 31 ~ 0 of the extended-precision registers containthe integer (signed or unsigned). Any instruction that assumes the operandsare either signed or unsigned integers uses only bits 31 - O. Bits 39 - 32 remainunchanged. This is true for all shift operations. The storage of 32-bit integersin the extended-precision registers is shown in Figure 3-2.Figure 3-2. Extended-Precision Register Integer Format39 32 31 oI unchanged I signed or unsigned integer3.1.2 Auxiliary Registers (AR7 - ARO)The eight 32-bit auxiliary registers (AR7 - ARO) can be accessed by the CPUand modified by the two Auxiliary Register Arithmetic Units (ARAUs). The primaryfunction of the auxiliary registers is the generation of 24-bit addresses.However, they can also be used as loop counters in indirect addressing or as32-bit general-purpose registers that can be modified by the multiplier andALU. Refer to Chapter 5 for detailed information and examples of the use ofauxiliary registers in addressing.3-4CPU Registers, Memory, and Cache
CPUFile3.1.3 Data~Page Pointer (DP)The data-page pointer (DP) is a 32-bit register, which is loaded using the LOPinstruction. The eight LSBs of the data-page pointer are used by the direct addressingmode as a pointer to the page of data being addressed. Data pagesare 64 K words long with a total of 256 pages. Bits 31 - 8 are reserved; youshould always keep these zero.3.1.4 Index Registers (IRO, IR1)The 32-bit index registers (IRO and IR1) are used by the Auxiliary RegisterArithmetic Unit (ARAU) for indexing the address. Refer to Chapter 5 for detailedinformation and examples of the use of index registers in addressing.3.1.5 Block-Size Register (BK)The 32-bit block-size register (BK) is used by the ARAU in circular addressingto specify the data block size (see Section 5.3 on page 5-24).3.1.6 System Stack Pointer (SP)The system stack pointer (SP) is a 32-bit register that contains the address ofthe top of the system stack. The SP always points to the last element pushedonto the stack. The SP is manipulated by interrupts, traps, calls, returns, andthe PUSH, PUSHF, POP, and POPF instructions. Pushes and pops of the stackperform preincrement and postdecrement, respectively, on all 32 bits of thestack pointer. However, only the 24 LSBs are used as an address. Referto Section5.5 on page 5-30 for information about system stack management.3.1.7 Status Register (ST)The status register (ST) contains global information relating to the state of theCPU. Typically, operations set the condition flags of the status register accordingto whether the result is zero, negative, etc. This includes register load andstore operations as well as arithmetic and logical functions. When the statusregister is loaded, however, the contents of the source operand replace thecurrent contents bit-for-bit, regardless of the state of any bits in the source operand.Therefore, following a load, the contents of the status register are identicallyequal to the contents of the source operand. This allows the status registerto be saved easily and restored. At system reset, 0 is written to this register., .3-5
CPU Register File:r:~.:"«~;x.:;.-::-.:;((o!';:;''''=;:::;:::::;:~->:;:
CPU Register File~;:::;:;::'''':::''.:::!;:;:;=':;:;:;:;:i:;:;:...:::;:;:;:;.::::;:::::::::::;::::::::::':::::::w.::::::::::::::::::::;o;o::;.;.;.;.::::::;:::::::::::::;::::.;:..::::::::;v.;,;.::::;:;:;.::;-;:~:::~;v.;.~;.::::::::::::;::::::::::::::...::::::;:::::;:;:::;:::;:;:::;:::;:;:.:::::::::::::;:::;:.;:"=::;:;:~~;:::::::~::;:.;:::::~;:::(::::;:::;:::;:~Table 3-2. Status Register Bits SummaryBit Name Reset Value Functionot C 0 Carry flag.1t V 0 Overflow flag.2t Z 0 Zero flag.3t N 0 Negative flag.4t UF 0 Floating-point underflow flag.st LV 0 Latched overflow flag.6t LUF 0 Latched floating-point underflow flag.7 OVM 0 Overflow mode flag. This flag affects only the integer operations. If OVM= 0, the overflow mode is turned off; integer results that overflow aretreated in no special way. If OVM = 1,a) integer results overflowing in the positive direction are set to themost positive 32-bit twos-complement number (7FFFFFFFh)b) integer results overflowing in the negative direction are set to themost negative 32-bit twos-complement number (80000000h).Note that the function of V and LV is independent of the setting of OVM.8 RM 0 Repeat mode flag. If RM = 1, the PC is being modified in either therepeat-block or repeat-single mode.9 Reserved 0 Read as O.10 CF 0 Cache freeze. When CF = 1 , the cache is frozen. If the cache is enabled(CE = 1), fetches from the cache are allowed, but no modification of thestate of the cache is performed. This function can be used to save frequentlyused code resident in the cache. At reset, a is written to this bit.Cache clearing (CC=1) is allowed when CF=O.11 CE 0 Cache enable. CE = 1 enables the cache, allowing the cache to be usedaccording to the least recently used (LRU) cache algorithm. CE = a disablesthe cache; no update or modification of the cache can be performed.No fetches are made from the cache. This function is useful forsystem debug. At system reset, 0 is written to this bit. Cache clearing(CC = 1) is allowed when CE=O.12 CC 0 Cache clear. CC = 1 invalidates all entries in the cache. This bit is alwayscleared after it is written to and thus always read as O. At reset, 0 is writtento this bit.13 GIE 0 Global interrupt enable. If GIE = 1 ,the CPU responds to an enabled interrupt.If GIE = 0, the CPU does not respond to an enabled interrupt.15-14 Reserved 0 Read as O.31-16 Reserved 0-0 Value undefined.t The seven condition flags (ST bits 6 -0) are defined in Section 10.2 on page 10-9.3-7
CPU Register File;o;o;!O!'O:~;y)!;:;:;:~:?;e;:;:::',:;::x~::::::;:;:;:;:;-;*'::"'::;:;:~;:::;:::::::;:i:::;!;x:::::!;f.:;!:::!'I.'«o:;:,o:;:".:'o:::-.:'..;:;:::;O;:;:;:::"o:::O:::~o:::;fo:~U.@O:~O:;:;:::;y;::y'".. ~;o;.-.:' ...... ~;y~ ..;:"..."...:»'..w.yx;o::Mv.-;..·:««
CPUFileTable 3-3. IE Register Bits SummaryBit Name Reset Value Function0 EINTO 0 Enable external interrupt 0 (CPU)1 EINT1 0 Enable external interrupt 1 (CPU)2 EINT2 0 Enable external interrupt 2 (CPU)3 EINT3 0 Enable external interrupt 3 (CPU)4 EXINTO 0 Enable serial-port 0 transmit interrupt (CPU)5 ERINTO 0 Enable serial-port 0 receive interrupt (CPU)6 EXINT1 0 Enable serial-port 1 transmit interrupt (CPU)7 ERINT1 0 Enable serial-port 1 receive interrupt (CPU)8 ETINTO 0 Enable timer 0 interrupt (CPU)9 ETINT1 0 Enable timer 1 interrupt (CPU)10 EOINT 0 Enable OMA controller interrupt (CPU)15-11 Reserved 0 Value undefined16 EINTO 0 Enable external interrupt 0 (DMA)17 EINT1 0 Enable external interrupt 1 (OMA)18 EINT2 0 Enable external interrupt 2 (OMA)19 EINT3 0 Enable external interrupt 3 (OMA)20 EXINTO 0 Enable serial-port 0 transmit interrupt (OMA)21 ERINTO 0 Enable serial-port 0 receive interrupt (OMA)22 EXINT1 0 Enable serial-port 1 transmit interrupt (OMA)23 ERINT1 0 Enable serial-port 1 receive interrupt (OMA)24 ETINTO 0 Enable timer 0 interrupt (OMA)25 ETINT1 0 Enable timer 1 interrupt (OMA)26 EOINT 0 Enable OMA controller interrupt (OMA)31-27 Reserved 0-0 Value undefined3.1.9 CPU ·Interrupt Flag Register (IF)The 32-bit CPU interrupt flag register (IF) is shown in Figure 3-5. A 1 in a CPUinterrupt flag register bit indicates that the corresponding interrupt is set. TheIF bits are set to 1 when an-interrupt occurs. They may also be set to 1 throughsoftware to cause an interrupt. A 0 indicates that the corresponding interruptis not set. If a 0 is written to an interruptflag register bit, the corresponding interruptis cleared. At reset, O. is written to this register. Table 3-4 lists the bit fields,bit field names, and bit field functions of the CPU interrupt flag register.3-9
CPU Register FileFigure 3-5. CPU Interrupt Flag Register (IF)31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16I xx I xx I xx I xx I xx I xx xx xx xx xx xx xx xx xx xx xx15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0I xx I xx I xx I xx I xx I DINT I TINT1 I TINTO I RINT1 I XINT1 I RINTO I XINTO I INT31 INT21 INT1 I INTO IRIW RIW RIW RIW RIW RIW RIW RIW RIW RIW RIWNOTE: xx = reserved bit, read as 0,R = read, W = write.Table 3-4. IF Register Bits SummaryBit Name Reset Value Function0 INTO 0 External interrupt 0 flag1 INT1 0 External interrupt 1 flag2 INT2 0 External interrupt 2 flag3 INT3 0 External interrupt 3 flag4 XINTO 0 Serial-port 0 transmit interrupt flag5 RINTO 0 Serial-port 0 receive interrupt flag6 XINT1t 0 Serial-port 1 transmit interrupt flag7 RINT1t 0 Serial-port 1 receive interrupt flag8 TINTO 0 Timer 0 interrupt flag9 TINT1 0 Timer 1 interrupt flag10 DINT 0 DMA channel interrupt flag31-11 Reserved 0-0 Value undefinedt Reserved on TMS320C31.3.1.10 I/O Flags Register (IOF)Figure 3-6. 110 Flag Register (IOF)The I/O flags register (IOF) is shown in Figure 3-6 and controls the functionof the dedicated external pins, XFO and XF1. These pins may be configuredfor input or output. They may also be read from and written to. At reset, 0 is writtento this register. The bit fields, bit field names, and bit field functions areshown in Table 3-5.31 30 29 28 27 26 25 24 2322xx21 20 19 18 17 16xx I xx I xx xx xx I xx I-15 14 13 12 11 10 9 8 765 4 3 2 oNOTE: xx = reserved bit, read as O.R = read, W = write.3-10CPU Registers, Memory, and Cache
Table 3-5. IOF Register Bits SummaryBit Name Reset Value Function0 Reserved 0 Read as O.1 I/OXFO 0 If l'0XFO = 0, XFO is configured as a general-purpose input pin.If I/OXFO = 1 , XFO is configured as a general-purpose output pin.2 OUTXFO 0 Data output on XFO.3 INXFO 0 Data input on XFO. A write has no effect.4 Reserved 0 Read as O.5 I/OXF1 0 If I/OXF1 = 0, XF1 is configured as a general-purpose input pin.If I/OXF1 = 1 , XFt is configured as a general-purpose output pin.6 OUTXF1 0 Data output on XF1.7 INXF1 0 Data input on XF1. A write has no effect.31-8 Reserved 0-0 Read as O.3.1.11 Repeat-Count (RC) and Block-Repeat Registers (RS, RE)The repeat-count register (RC) is a 32-bit register used to specify the numberof times a block of code is to be repeated when performing a block repeat.The repeat start address register (RS) is a 32-bit register containing the startingaddress of the block of program memory to be repeated when operatingin the repeat mode.The 32-bit repeat end address register (RE) contains the ending address of theblock of program memory to be repeated when .operating in the repeat mode.3.1.12 Program Counter (PC)The program counter (PC) is a 32-bit register containing the address of the nextinstruction to be fetched. While the program counter is not part of the CPU registerfile, it is a register that can be modified by instructions that modify the programflow.3.1.13 Reserved Bits and CompatibilityIn order to retain compatibility with future members of the TMS320C3x familyof microprocessors, reserved bits that are read as zero must be written as zero.Reserved bits that have an undefined value must not have their current valuemodified. In other cases, the user should maintain the reserved bits as specified.3-11
3.2 MemoryThe TMS320C3x's total memory space of 16M (million) 32-bit words containsprogram, data, and I/O space, allowing tables, coefficients, program code, ordata to be stored in either RAM or ROM. In this way, memory usage can bemaximized and memory space allocated as desired.RAM blocks 0 and 1 are each 1 K x 32 bits. The ROM block is 4K x 32 bits. Eachon-chip RAM and ROM block is capable of supporting CPU two accesses ina single cycle. The separate program buses, data buses, and DMA buses allowfor parallel program fetches, data reads/writes, and DMA operations. Chapter9 covers this in detail.3.2.1 TMS320C3x Memory MapsThe memory map is dependent upon whether the processor is running in themicroprocessor mode (MC/MP or MCBUMP = 0) or the microcomputer mode(MC/MP or MCBUMP = 1). The memory maps for these modes are similar (seeFigure 3-7). Locations 800000h through 801 FFFh are mapped to the expansionbus. When this region, available only on the TMS320C30, is accessed,MSTRB is active. Locations 802000h through 803FFFh are reserved. Locations804000h through 805FFFh are mapped to the expansion bus. When thisregion, available only on the TMS320C30, is accessed, 10STRB is active. Locations806000h through 807FFFh are reserved. <strong>Al</strong>l of the memory-mappedperipheral registers are in locations 808000h through 8097FFh. In both modes,RAM block 0 is located at addresses 809800h through 809BFFh, and RAMblock 1 is located at addresses 809COOh through 809FFFh. Memory locations80AOOOh through OFFFFFFh are accessed over the primary external memoryport (STRB active).In microprocessor mode, the 4K on-chip ROM (TMS320C30) or bootloader(TMS320C31) is not mapped into the TMS320C3x memory map. As shown inFigure 3-7, locations Oh through BFh consist of interrupt vector, trap vector,and reserved locations, all of which are accessed over the primary externalmemory port (STRB active). Interrupt and trap vector locations are shown inFigure 3-9. Locations COh through 7FFFFFh are also accessed over the primaryexternal memory port.In microcomputer mode, the 4K on-chip ROM (TMS320C30) or bootloader(TMS320C31) is mapped into locations Oh through OFFFh. There are 19210cations(Oh through BFh) within this block for interrupt vectors, trap vectors, anda reserved space. Locations 1 OOOh through 7FFFFFh are accessed over theprimary external memory port (STRB active)'.Do not read and write reserved portions ofthe TMS320C3x memory space andreserved peripheral bus addresses. Doing so may cause the TMS320C3x tohalt operation and require a system reset to restart.3-12CPU Registers, Memory, and Cache
Figure 3-7. TMS320C30 Memory MapsOhOBFhOCOh7FFFFFhBOOOOOhB01FFFhB02000h803FFFh804000h805FFFhB06000hB07FFFhBOBOOOhInterrupt Locationsand Reserved (192)External STRB ActiveExternalSTRB Active~nsionBusMSTRB Active (8K)Reserved(8K)~sionBusIOSTRB Active (BK)Reserved(BK)OhOBFhOCOhOFFFh1000h7FFFFFhBOOOOOh801FFFh802000h803FFFh804000hB05FFFhB06000hB07FFFhBOBOOOhInterrupt Locationsand Reserved (192)----------ROM(Internal)ExternalSTRB Active~nsionBusMSTRB Active (8K)Reserved(8K)~sionBusIOSTRB Active (BK)Reserved(BK)Peripheral BusMemory-MappedRegisters(Internal) (6K)Peripheral BusMemory-MappedRegisters(Internal) (6K)B097FFh809BOOh809BFFhB09COOh809FFFh80AOOOhOFFFFFFhRAM Block 0(1 K) (Internal)RAM Block 1(1 K) (Internal)ExternalSTRB Active8097FFh809800h809BFFhB09COOh809FFFh80AOOOhOFFFFFFhRAM Block 0(1 K) (Internal)RAM Block 1(1 K) (Internal)ExternalSTRB Active(a) Microprocessor Mode(b) Microcomputer Mode3-13
Memory~::;:;:;:::::;:-':;-:;:;:;:::::;:;:;:;':::-:;x:;:;::::-:::::;::m:;-:::::;-:::::::;::::::::::-:::::;::::::~::;:;:~;::!::;:::;:::;:;:;:;:::;:;:::;:;:::;:::;:::;:::::;:;:::::;:;:::;::::::::::::::::::~~~::;X~::;:::::~.:::;::::~:;:::m.::::~~;:X-;-::;:::;:::::::X::-:::::::::::::::::';:::::::::;:;:;:::::;:::::;::~::;:~;-;-;~-:::;:::::;:::::::~,,!:::-;.::;-::;:::::::;.:::::~.(.:;:::;:::;.;:::::::;::-;.::;:;:;.::;:;:~:;::.:.::: ..-:::;:;::.::;.:::::.:::~.:;:::::;:;:;:;:;:;:;:::::;::::::::::-:;:::::::::::::::::::::::::;:::;:;:;~::::;:;:::::;:::;~:::::::::o:::;:::::::;-;:::::::::s3.2.2 TMS320C31 Memory MapsSetting the state of the TMS320C31 MCBUMP pin determines the mode inwhich the TMS320C31 can function:Q Microprocessor mode (MCBUMP = 0)Q Microcomputer/boot loader mode (MCBUMP = 1)The major difference between these two modes is their memory maps (seeFigure 3-8). The program boot load feature is enabled when the MCBUMP pinis driven high during reset.Notice that special memory locations are used by the loader (internal and external).They are identified in the microcomputer/boot loader memory mapshown in Figure 3-8.3-14CPU Registers, Memory, and Cache
Figure 3-9. Reset, Interrupt, and Trap Vector LocationsOOh01h02h03h04h05h06h07h08h09hOAhOBhOCh1 Fh20h3Bh3Ch3Dh3Eh3FhRESETINTOINT1INT2INT3XINTORINTOXINT1tRINT1tTINTOTINT1DINTRESERVEDTRAP 0·TRAP 27TRAP 28 (Reserved)TRAP 29 (Reserved)TRAP 30 (Reserved)TRAP 31 (Reserved)tReserved on TMS320C313-17
Memory~:~:9.=~s~.s~Y..:s!".x':~~:s:--::?"~~w.Q.:::~~.:~!".s::::~~~~m~;:::;s:;:;:~SY.~~s::::~~:::==m?O .. ~S::~~"-::~Q.~~~:::;O~Y;-;O::~~~~~:~::::S~:-:9' ..(.......:::v.;::9-"'·:','~::;Y;?;"S«~~XS'~y':Y;·~%:;YXY:~5Y.X:»';::·:S"«SY.>v.:%s~:m?~9.:y';~":"SS:~~:O::!:::~~SS~:;:;7.>Y.."!:S!-::SS::~6~SS~3.2.4 Peripheral Bus MapFigure 3-10. Peripheral-Bus Memory MapThe memory-mapped peripheral registers are located starting at address808000h. The·peripheral bus memory map is shown in Figure 3-10. Each peripheraloccupies a 16-word region of the memory map. Locations 80801 Ohthrough 80801 Fh and locations 808070h through 8097FFh are reserved.808000h80800Fh808010h80801Fh808020h80802Fh808030h80803Fh808040h80804Fh808050h80805Fh808060h80806Fh808070h8097FFhDMA Controller Registers(16)Reserved(16)Timer 0 Registers(16)Timer 1 Registers(16)Serial-Port 0 Registers(16)Serial-Port 1 Registerst(16)Primary and Expansion PortRegisters (16)ReservedtReserved on TMS320C313-18CPU Registers, Memory, and Cache
Instruction Cache3.3 Instruction Cache3.3.1 Cache ArchitectureFigure 3-11. Instruction Cache ArchitectureA 64 x 32-bit instruction cache facilitates maximum system performance withminimal system cost by storing sections of code that can be fetched when repeatedlyaccessing time-critical code. This reduces the number of off-chip accessesnecessary and allows for code to be stored off-chip in slower, lowercostmemories. The cache also frees external buses from program fetches sothey can be used by the DMA or other system elements.The cache can operate in a completely automatic fashion without the need foruser intervention. Section 3.3.2 describes a form of the LRU (least recentlyused) cache update algorithm.The instruction cache (see Figure 3-11) contains 64 32-bit words of RAM andis divided into two 32-word segments. Associated with each segment is a 19-bitsegment start address (SSA) register. for each word in the cache, there is acorresponding single bit: Present (P) flag.IISegment StartAddress RegistersASSA Register 0I~ 19 ~PFlagsffiHEISegment WordsASegment Word 0Segment Word 1Segment Word 3031 Segment Word 31~ 32 ~Segment 0LRUStackECSegmentMost Recently UsedNumberLeast Recently UsedSegment NumberSSA Register 1tBSegment Word 0Segment Word 1HESegment Word 3031 Segment Word 31Segment 1When the CPU requests an instruction word from external memory, a checkis made to determine if the word is already contained in the instruction cache.Figure 3-11 shows the partitioning of an instruction address as used by the3-19
Instruction Cachecache control algorithm. The19 most significant bits of the instruction addressare used to select the segment, and the 5 least significant bits define the addressof the instruction word within the pertinent segment. The 19 MSBs of theinstruction address are compared with the two segment start address (SSA)registers. If a match is found, a check is made of the relevant P flag. The Pflag indicates whether or not the word within a particular segment is alreadypresent in cache memory.Figure 3-12. Address Partitioning for Cache Control <strong>Al</strong>gorithm23segment start address(SSA)54instruction wordaddress within segmentoIf there is no match, one of the segments must be replaced by the new data.The segment replaced in this circumstance is determined by the LRU (Ieast-recently-used)algorithm. The LRU stack (see Figure 3-11) is maintained for thispurpose.The LRU stack determines which of the two segments qualifies as the least-recently-usedafter each access to the cache; therefore, the stack contains either0,1 or 1,0. Each time a segment is accessed, its segment number is removedfrom the LRU stack and pushed onto the top of the LRU stack. Therefore, thenumber at the top of the stack is the most recently used segment number, andthe number at the bottom of the stack is the least recently used segment number.At system reset, the LRU stack is initialized with 0 at the top and 1 at the bottom.<strong>Al</strong>l P flags in the instruction cache are cleared. .When a replacement is necessary, the least recently used segment is selectedfor replacement. <strong>Al</strong>so, the 32 P flags for the segment to be replaced are setto 0, and the segment's SSA register is replaced with the 19 MSBs of the instructionaddress.3.3.2 Cache <strong>Al</strong>gorithmWhen the TMS320C3x requests an instruction word from external memory,one of two possible actions occurs: a cache hit or a cache miss. These are describedin the following list:QCache Hit. The cache contains the requested instruction, and the followingactions occur:• The instruction word is read from the cache.• The number of the segment containing the word is removed from theLRU stack and pushed to the top of the LRU stack, thus moving theother segment number to the bottom of the stack.3-20CPU Registers, Memory, and Cache
Instruction CacheQ Cache Miss. The cache does not contain the instruction. Types of cachemiss aremEJWord miss. The segment address register matches the instruction address,but the relevant P flag is not set. The following actions occur inparallel:aThe instruction word is read from memory and copied into thecache.1:1 The number of the segment containing the word is removed fromthe LRU stack and pushed to the top of the LRU stack, thus movingthe other segment number to the bottom of the stack.1:1 The relevant P flag is set. ,Segment miss. Neither of the segment addresses matches the instructionaddress. The following actions occur in parallel:aThe least recently used segment is selected for replacement. TheP flags for all 32 words are cleared.a The SSA register for the selected segment is loaded with the 19MSBs of the address of the requested instruction word.aThe instruction word is fetched and copied into the cache. It goesinto the appropriate word of the least recently used segment. TheP flag for that word is set to 1.1:1 The number of the segment containing the instruction word is removedfrom the LRU stack and pushed to the top of the LRU stack,thus moving the other segment number to the bottom of the stack.Only instructions may be fetched from the program cache. <strong>Al</strong>l reads and writesof data in memory bypass the cache. Program fetches from internal memorydo not modify the cache and do not generate cache hits or misses. The programcache is a single-access memory block. Dummy program fetches (i.e.,following a branch) are treated by the cache as valid program fetches and cangenerate cache misses and cache updates.Take care when using self-modifying code. If an instruction resides in'cacheand the corresponding location in primary memory is modified, the copy of theinstruction in cache is not modified.You can make more efficient use of the cache by aligning program code on32-word address boundaries. Do this by using the ALIGN directive when codingassembly language.3-21
Instruction Cache3.3.3 Cache Control BitsTable 3-6. Combined Effect of the CE and CF BitsThree cache control bits are located in the CPU status register: the cache clearbit (CC), the cache enable bit (CE), and the cache freeze bit (CF).Cache Clear Bit (CC). Writing a 1 to the cache clear bit (CC) invalidates allentries in the cache. <strong>Al</strong>l P flags in the cache are cleared. The CC bit isalways cleared after the cache is cleared. It is therefore always read asa o. At reset, the cache is cleared and 0 is written to this bit.Cache Enable Bit (CE). Writing a 1 to this bit enables the cache. When enabled,the cache is used according to the previously described cachealgorithm. Writing a 0 to the cache enable bit disables the cache; noupdates or modification of the cache can be performed. Specifically,no SSA register updates are performed, no P flags are modified (unlessCC = 1), and the LRU stack is not modified. Writing a 1 to CC whenthe cache is disabled clears the cache, and, thus, the P flags. Nofetches are made from the cache when the cache is disabled. At reset,o is written to this bit.Cache Freeze Bit (CF). When CF = 1, the cache is frozen. If, in addition, thecache is enabled, fetches from the cache are allowed, but no modificationofthe state of the cache is performed. Specifically, no SSA registerupdates are performed, no P flags are modified (unless CC = 1), andthe LRU stack is not modified. This function can be used to keep frequentlyused code resident in the cache. Writing a 1 to CC when thecache is frozen clears the cache, and, thus, the P flags. At reset, 0 iswritten to this bit.Table 3-6 defines the effect of the CE and CF bits used in combination.CE CF Effect0 0 Cache not enabled0 1 Cache not enabled1 0 Cache enabled and not frozen1 1 Cache enabled and frozen3-22 CPU Registers, Memory, and Cache
the TMS320C31 Boot Loader3.4 Using the TMS320C31 Boot Loader3.4.1 Boot Loader Operations3.4.2 Invoking the Boot LoaderThis section describes howto use the TMS320C31 microcomputer/boot loader(MCBUMP)function. This feature is unique to the TMS320C31 and is not availableon the TMS320C30 device.The boot loader lets you load and execute programs that are received from ahost processor, inexpensive EPROMs, or other standard memory devices.The programs to be loaded reside in one of three memory mapped areas identifiedas Boot 1, Boot 2, and Boot 3 (see the shaded areas of Figure 3-8 ), orthe programs are received by means of the serial port.User-definable byte, half-word, and word data formats are supported. 32-bitfixed burst loads from the TMS320C31 serial port are also supported. See Section8.2 for a detailed description of the serial port operation.The boot loader function is selected by resetting the processor while drivingthe MCBUMP pin high. Figure 3-13 shows the flow of this operation, which isdependent upon the mode selected (external' memory or serial boot).Figure 3-14 shows memory load operations; Figure 3-15 shows serial portload operations.Figure 3-13. Boot Loader Mode Selection Flowchart3-23
the TMS320C31 Boot LoaderFigure 3-15. Boot Loader Serial Port Load Mode FlowchartBranch to DestinationAddress of FirstBlock LoadedBegin Program Execution3.4.3 Mode SelectionAfter reset, the loader mode is determined by polling the status of the INT3-INTO pins. Table 3-7 lists the options that you can select. The options arebased upon the active low state of the INT3-INTO signals. The TMS320C31device begins reading data from the boot memory location selected by the activeinterrupt signal. Interrupts can be driven any time after the RESET pin hasbeen deasserted.3-25
the TMS320C31 Boot LoaderTable 3-7. Loader Mode SelectionActive Interrupt Loader Mode Memory AddressesINTO External memory Boot 1 address Ox001 000INT1 External memory Boot 2 address Ox400000INT2 External memory Boot 3 address OxFFFOOOINT3 32-bit serial Serial port 03.4.4 External Memory LoadingTable 3-8. External Memory Loader HeaderTable 3-8 shows and describes the information that you must specify to defineboot memory organization (8, 16, or 32 bits), the code block size, the load desti-. nation address, and memory access timing control for the boot memory. Thismust be done before a source program can be externally loaded.This information must be specified in the first four locations of the Boot 1 , Boot2, or Boot 3 areas. The header is followed by the data or program code thatis the BLK size in length.Location01234DescriptionBoot memory type (8, 16, or 32)Boot memory configuration(defined # of wait states, etc.)Valid Data EntriesOx8, Ox1 0, or Ox20 specified as a 32-bit number.See Chapter 7 of the TMS320C3x User's Guidefor valid bus control register entries.Program block size (BLK) Any value 0 < BLK < 224.Destination addressProgram code starts hereAny valid TMS320C31 24-bit address.Any 32-bit data value or valid TMS320C3x instruction.The loader fetches 32 bits of data for each specified location, regardless ofwhat memory configuration width is specified. The data values must residewithin or be written to memory, beginning with the value of least significancefor each 32 bits of information.3.4.5 Examples of External Memory LoadsExample 3-1, Example 3-2, and Example 3-3 show memory images forbyte-wide, 16-bit wide, and 32-bit wide configured memory.These examples assume that1) an INTO signal was detected after reset is deasserted (external memoryload from Boot 1).2) the loader header resides at memory location Ox1 000 and defines the following:3-26CPU Registers, Memory, and Cache
the TMS320C31 Boot LoaderExample 3-1. Byte-Wide Configured Memorya) boot memory type EPROMs that require two wait states and SWW =11,b) a loader destination ·address at the beginning of the TMS320C31's internalRAM Block 0, andc) a single block of memory that is Ox1 FF in length.Address Value Commentsox1000 Ox08 Memory width = 8 bitsox1001OxOOOx1002OxOOox1003OxOOOx1004 Ox58 Memory type = sww = 11, WCNT c 2Ox1005Ox10Ox1006OxOOOx1007OxOOOx1008 OxFF Program code size = Ox1 FFOx1009Ox01Ox100AOxOOOx100BOxOOOx100C OxOO Program load starting address = Ox8098POOx100DOx98Ox100EOx80Ox100FOxOOExample 3-2. 16-Bit Wide Configured MemoryAddress Value Commentsox1000 Ox10 Memory width = 16Ox1001OxOOOOOx1002 Ox1058 Memory type = SWW = 11, WCNT = 2Ox1003OxOOOOOx1004 Ox1FF Program code size = Ox1 FFOx1005OxOOOOOx1006 Ox9800 Program load starting address = Ox809800Ox1007OxOO803-27
the TMS320C31 Boot LoaderExample 3-3. 32-Bit Wide Configured MemoryAddress Value CommentsOx1000 OxOOOOOO20 Memory width = 32Ox1001 OxOOOO1058 Memory type = sww = 11, WeNT = 2Ox1002 Ox000001 FF Program code size = Ox1 FFOx1003 OxOO809800 Program load starting address = Ox809800After the header is read, the loader transfers BLK, 32-bit words beginning ata specified destination address. Code blocks require the same byte and halfwordordering conventions. Additionally, the loader can be used to load multiplecode blocks at different address destinations.If multiple code blocks are loaded, execution begins at the first block of codeloaded. Consequently, the first code block loaded should be a startup routineto access the other loaded programs.If another code block is to be loaded, the following header and its correspondingcode must be appended to the preceding code block:BLK sizeDestination address1st location2nd locationRepeat this procedure for additional code blocks. End the loader function andbegin execution of the first code block by appending the value of OxOOOOOOOOto the last block .•·I!••• i·~···~·~.~ti·fu~ .. th·at··at ••• I.~ast.·()~.e···bl~·~·~ •• Of··cod.e··W~.I.I .•·be··lo~de~ •• VJh~h •• ~.~.~····· .............I.~acl~r!§ihyok~d. ··.Ir'li~iaIJ9ad~r.illvocationwitha . block sizepfPxOQ9Q9.Q90»pr9cilJc¢~unpredict~~,e r~sults.·3.4.6 Serial Port LoadingBoot loads, by way of the TMS320C31 serial port, are selected by driving theINT3 pin active low following reset. The loader automatically configures the serialport for 32-bit fixed burst reads. It is interrupt-driven by the FSR signal. Youcannot change this mode for boot loads. The serial port clock and FSR are externallygenerated by your hardware.As in parallel loading, a header must precede the actual program to be loaded.However, only the block size and destination address must be provided becauseserial port speed and data format are predefined by the loader and yourhardware (Le., skip data words 0 and 1 from Table 3-8).3-28CPU Registers, Memory, and Cache
the TMS320C31 Boot LoaderThe transferred data-bit order must begin with the most significant bit (MSB)and end with the least significant bit (LSB).3.4.7 Interrupt and Trap Vector MappingUnlike the microprocessor mode, the microcomputer/boot loader (MCBL)mode uses a dual-vectoring scheme to service interrupt and trap requests.Dual vectoring was implemented to ensure code compatibility with future versionsof TMS320C3x devices.In a dual-vectoring scheme, branch instructions to an address, rather than directinterrupt vectoring, are used. The normal interrupt and trap vectors are definedto vector to the last 63 locations in the on-chip RAM. When the loader isinvoked, the TMS320C31's last 63 locations of RAM Block 1 are assumed tocontain interrupt and trap branch instructions.Table 3-9 shows the MCBUMP mode interrupt and trap instruction memorymaps.3-29
the TMS320C31 Boot LoaderTable 3-9. TMS320C31 Interrupt and Trap Memory MapsAddress809FC1809FC2809FC3809FC4809FC5809FC6809FC7809FC8809FC9809FCA809FCB809FCC-809FDF809FEO809FE1DescriptionINTOINT1INT2INT3XINTORINTOReservedReservedTINTOTINT1DINTOReservedTRAPOTRAP1• •• •• •809FFBTRAP27809FFC-809FFFReserved3-30 CPU Registers, Memory, and Cache
~ ______ D_a_ta __ Fo __ rm __ at_s_a_n_d __ F_lo_a_t_in_g_-P_o __ in_t_O_p_e_r_at_i_o_n ______________ ~" __~11111
IIImIII~ ______________ D_a_t_a_F_o_r_m_a_ts __ a_n_d_F_lo_a_t_in_g_-_p_o_in_t_O_p_e_r_a_ti_o_n ______ ~
Integer Formats4.1 Integer FormatsThe TMS320C3x supports two integer formats: a 16-bit short integer formatand a 32-bit single-precision integer format. When extended-precision registersare used as integer operands, only bits 31- 0 are used; bits 39 - 32 remainunchanged and unused.4.1.1 Short Integer FormatThe short integer format is a 16-bit twos-complement integer format used forimmediate integer operands. For those instructions that assume integer operands,this format is sign-extended to 32 bits (see Figure 4-1). The range of aninteger si, represented in the short integer format, is -2 15 ~ si ~ 2 15 -1. InFigure 4-1, s = signed bit.Figure 4-1. Short Integer Format and Sign Extension of Short Integer15 o(a) Short Integer Format31 16 15 o15 5 5 5 5 5 5 5 5 5 5 5 5 5 5 51 5(b) Sign Extension of a Short Integer4.1.2 Single-Precision Integer FormatFigure 4-2. Single-Precision Integer FormatIn the single-precision integer format, the integer is represented in twos-complementnotation. The range of an integer sp, represented in the single-precisioninteger format, is- 2 31 ~ sp~ 2 31 -1. Figure 4-2 shows the single-precisioninteger format.31 o4-2 Data Formats and Floating-Point Operation
Floating-Point Formats;:;~".S·;Y ... ·;·;·.·;:::;:;:;o;·.·.·.:;:.:;:;:.:;:::;:;:;:o:;:::;:::::::::::::;:::;:::::;:;:;:.:::::::;:-:;:;:.:::::;::.::;.;:.:;o:;:::::>:::::;:::::::::;:::;o;:;:;:::;.::;:::;::::.;.;~::: ;o::;·;:;·;y;y~·;::,.·;!OV;.~:::",:,;,:,,·;-;y';o;:;·;v;"·M·;·;·;o;,::;o; ... :.:.: ... ;.;.;.;.;.:.::::; ... ;.;o;.; .. o;.;.; .. o;~.;.;.;.;o»;·;.;o;·;·;.;.: .... ·.« ...... ·;o;·;v;·:·;·; .... ·;·;·;·;·.·;·;·;·;·;·;.;.;.;.; ••• ;.:«.:.;.; ..... ; ••. : .... o;.;o •• : ••• ; ..... ;~ ••• ;.; .. ·;·;·;·;o;.;·;·;·; .. o;·;·;o;.o·;·;v;·;· ... ·;·;.::;·;·;·.v.:·;·; ... ;::.;::.::;.;:;~;o; ... ;:;::.;.;:;:::::;:;:::::;::::::::4.3 Floating-Point Formats<strong>Al</strong>l TMS320C3x floating-point formats consist of three fields: an exponent field(e), a single-bit sign field (s), and a fraction field (t). These are stored as shownin Figure 4-5. The exponent field is a twos-complement number. The sign fieldand fraction field may be considered as one unit and referred to as the mantissafield (man). The twos-complement fraction is combined with the sign bit andthe implied most significant bit to create the mantissa. The mantissa is usedto represent a normalized twos-complement number. In a normalized representation,a most significant nonsign bit is implied, thus providing an additionalbit of precision. The value of a floating-point number xas a function of the fieldse, s, and f is given asx=01.fx2 e1 O.fx 2eoif S = 0, or where the leading zero is the sign bit and theone is the implied most significant nonsign bit.if S = 1 , or where the leading one is the sign bit and thezero is the implied most significant nonsign bit.if e = most negative twos complementvalue of the specified exponent field width.Figure 4-5. Generic Floating-Point Formatte-~--- man (mantissa) ----Dl~Note:e = exponent fields = single-bit sign fieldf = fraction fieldThree floating-point formats are supported on the TMS320C3x. The first is ashort floating-point format for immediate floating-point operands, consisting ofa 4-bit exponent, 1 sign bit, and an 11-bit fraction. The second is a single-precisionformat consisting of an 8-bit exponent, 1 sign bit, and a 23-bit fraction. Thethird is an extended-precision format consisting of an 8-bit exponent, 1 sign bit,and a 31-bit fraction.4.3.1 Short Floating-Point FormatIn the short floating-point format, floating-point numbers are represented by atwos-complement 4-bit exponent field (e) and a twos-complement 12-bit mantissafield (man) with an implied most significant nonsign bit.4-4Data Formats and Floating-Point Operation
I-I"''',;)tln,n_/-J,nint FormatsFigure 4-6. Short Floating-Point Format15 12111 110 oI e I sI/1+411---- man ----I)f~Operations are performed with an implied binary point between bits 11 and 10.When the implied most significant nonsjgn bit is made explicit, it is located tothe immediate left of the binary point. The floating-point twos-complementnumber x in the short floating-point format is given byx=01.fx2 910.fx2 9oif 5= 0if 5 = 1if e=- 8You must use the following reserved values to represent zero in the short floating-pointformat:e=-85=0f= 0The following examples illustrate the range and precision of the short floating-pointformat:Most Positive:Least Positive:Least Negative:Most Negative:X= (2-2 -11) x 27 = 2.5594 x 102X= 1 x2 -7 = 7.8125 x10-3x=(-1- 2 -11) x2 -7 = -7.8163 x1 0-3x = -2 x 27 = - 2.5600 x 10 24-5
Floating-Point Formats4.3.2 Single-Precision Floating-Point FormatIn the single-precision format, the floating-point number is represented by an8-bit exponentfield (e) and a twos-complement 24-bit mantissa field (man) withan implied most significant nonsign bit.Operations are performed with an implied binary point between bits 23 and 22.When the implied most significant nonsign bit is made explicit, it is located tothe immediate left of the binary point. The floating-point number x is given byx = 01.f x 2 e if s = 010.fx2 eoFigure 4-7. Single-Precision Floating-Point Formatif s = 1ife=-12831 24/23/22 o./4---- man ----D-I~IYou must use the following reserved values to represent zero in the single-precisionfloating-point format:e = -1285=0f= 0The following examples illustrate the range and precision of the single-precisionfloating-point format.Most Positive: x= (2 - 2 -23) x 2127 = 3.4028234 x1 038Least Positive:Least Negative:Most Negative:x= 1 x2 -127 = 5.8774717 x10 -39x= (-1-2 -23) x2 -127 =- 5.8774724x10- 39x=- 2 x 2127 =- 3.4028236x10384.3.3 Extended-Precision Floating-Paint FormatIn the extended-precision format, the floating-point number is represented byan 8-bit exponent field (e) and a32-bit mantissa field (man) with an impliedmost significant nonsign bit.4-6Data Formats and Floating-Point Operation
~:.-;::.-:.-:::~::::::;~::;~;.::::~"S:~o;:::::~::=:::;~::::::::::;~;::::~;~;:;:;:;~:;:i:;:;:::;:::;:;:;:;:;:::'.:;:;:::;~","~';:;:::;:::~"';:;'; ..::::.:::::::~o;:::~o;..:.:....,=,;:::~... ~.:.;.;,o::::::::~..::;~: ..... ;:;~:~:::::·::::;.o;:~..·;x~:..::::.....:......·;..«·~o;:......... o;.~~«-;" ....;....:·;.., .. ~::;:;. ..:;:;·;..,'S..«-;........::::;......,yo·;.. ~·;,o;';'V;'''';''''''';''''''·K''';''''':::: .............;....;..« ...............::::~..................::::::::::..... ~.::::::::::::;~Floating-Point Formats..... ~::::::;.~::;.~;..;., .. ~.s. ....;se~!O...:~~~:>:;S%:.;s.:~Operations are performed with an implied binary point between bits 31 and 30.When the implied most significant nonsign bit is made explicit, it is located tothe immediate left of the binary point. The floating-point number x is given by:x = 01.f x 2 9 if s = 01 O.fx 2 9 if s = 1o if e = -128Figure 4-8. Extended-Precision Floating-Point Format39 32131 130 oe~------- manYou must use the following reserved values to represent zero in the extended-precisionfloating-point format:e = -128s=Of= 0The following examples illustrate the range and precision of the extended-precisionfloating-point format:Most Positive:x= (2 - 2-31 )x 2127 = 3.4028236683 x1038Least Positive: X= 1 x 2 -127 = 5.8774717541 x10 -39Least Negative: x= (...... 1-2 -31) x2 -127 =- 5.8774717569 x1 0 -39Most Negative: X= - 2 x 2127 = - 3.4028236691 x 10384-7
Floating-Point Formats;s~~«;!;:r.:~«,('::9.;:o~:-~~:"~:;:::os:;:-;:o::;:;:.;:o::o:;:;:;:;:;:;:;:;:;:~;:;:-.:::;r.:;::::r.(.:;:"
Floating-Point Formats~;:'::'::'::'::::~~;Y;:':~;:'::;:;:;:'::;:;:;:;:;~;:;:;Y.;:;:::;:;:'::'::;:;~:'::'::;:::;:;:'::;:;:>:'::::;:; :'::;:'::';~:'::':.~:-:'::'::':;:'::;:;:;:'::;~:':.~:':';:'::;:;:;';.~:':';:::S';:.S:;'::;O;';:-';.. ,;';:;:.:;';';~~~.~-;';~;';:;-;';';';-;-;-;-;-;';.-;.-;"-;-;';';-;';:;';';"O;-;O;';';:;:;-;O;~';:-';';"';';:i';"';'.';';:-"';-;-;"."""""""';~"":;"""""""';"';"·;.;....·:.;,;..............,;....,;...... ·~;-;,;,;..:... ,,·~;·;,:s·;:;·;·;·;·~;·;.;...;~..;:.......... ~ ........ ~.: ••;.......... ~ .....;~.:~..... ~.~::.:;::""::"'::::;:::;:::::::::::"';:~:;::''':::;';:;:':::::::::'~Q Single-precision floating-point format conversion to extended-precisionfloating-point format.31 24 23 22 o(a) Single-Precision Floating-Point Format39 32 31 30 8 7 o(b) Extended-Precision Floating-Point FormatThe fraction field is filled with zeros.I:lExtended-precision floating-point format conversion to single-precisionfloating-point format.39 32 31 30 8 7 o(a) Extended-Precision Floating-Point Format31 24 23 22 ox I y I y(b) Single-Precision Floating-Point FormatThe fraction field is truncated.4-9
Floating-Point Multiplication4.4 Floating-Point MultiplicationA floating-point number a can be written in floating-point format as in the followingformula, where a(man) is the mantissa and a(exp) is the exponent.a = a( man} x 2a ( exp)The product of a and b is c, defined asc = a x b = a(man) x b(man) x 2(a(exp)+b (exp))c(man) = a(man) x b(man)c( exp) = a( exp) + b( exp)During floating-point multiplication, source operands are always assumed tobe in the single-precision floating-point format. If the source of the operandsis in short floating-point format, it is extended to the single-precision floating-pointformat. If the source of the operands is in extended-precision floating-pointformat, it is truncated to single-precision format. These conversionsoccur automatically in hardware with no overhead. <strong>Al</strong>l results of floating-pointmultiplications are in the extended-precision format. These multiplications occurin a single cycle.A flowchart for floating-point multiplication is shown in Figure 4-9. In step 1,the 24-bit source operand mantissas are multiplied, producing a 50-bit resultc(man). (Note that input and output data are always represented as normalizednumbers.) In step 2, the exponents are added, yielding c(exp). Steps 3 through6 check for special cases. Step 3 checks for whether c(man) in extended-precisionformat is equal to zero. If c(man} is zero, step 7 sets c(exp} to -128, thusyielding the representation for zero.Steps 4 and 5 normalize the result. If a right shift of one is necessary, then instep 8,c(man) is right-shifted one bit, and one is added to c(exp}. If a right shiftof two is necessary, then in step 9, c(man} is right-shifted two bits, and two isadded to c(exp). Step 6 occurs when the result is normalized.In step 10, c(man) is set in the extended-precision floating-point format. Steps11 through 16 check for special cases of c(exp). In step 14, if c(exp) has overflowed(step 11) in the positive direction, then c(exp) is set to the most-positiveextended-precision format value. If c(exp) has overflowed in the negative direction,then c( exp) is set to the most-negative extended-precision format value.If c(exp) has underflowed (step 12), then c is set to zero (step 15); i.e.,c(man) = a and c(exp) = -128.4-10Data Formats and Floating-Point Operation
Floating-Point MultiplicationFigure 4-9. Flowchart for Floating-Point Multiplicationa(man) b(man) a(exp) b(exp)~ ~ (1 ) 'J J (2Multiply mantissasAdd exponentsc(man) = a(man) x b(man)c(exp) = a(exp) + b(exp)(50-bit result)J_ ~Test for special cases of c(roan)(3) (4) (5) (6)c(man) = 0 Right- shift 1 Right- shift2 No shiftto normalize to normalize to normalize~ (7) ~ (8) ~ (9)c(exp) =-128c(roan) > > 1and c(exp) =c(roan) > > 2and c(exp) =c(exp) + 1 c(exp) + 2I•~Dispose of extra bits (10)Put c(roan) in extendedprecision floating-pointformat' .. ~Test for special cases of c( exp)(11 ) (12) (13)c( exp) overflow c( exp) underflow c( exp) rn range~ (14\ ~If c(man) > 0,set c to mostc(exp) = -128c(roan) = 0(15)positive value.If c(man) < 0,set c to mostnegative value.IJ, ~,~!rI Set c to final result 1(16)~c=axb4-11
Floating-Point Multiplicationi! ........... :.~~.:... y. .... ~;~.~:;!;:.:.:;:;:.:.x;~.:;:;!o,:~;:;:;.),;:;:;:;:;:;:;''':;:;:;:;:;!"F.':;:;:;:.:;:;:.:::;:.:':':''~:;:; .... '.:. :,:;:;·;s:>%:;:::;:;:;:~::>:;:;:,.:;:;:;:;y::~:.:;:>~:~;:;,~:;:.":;........:.....·;:;....:;:h....«:..;::..·::;·;:;:;~h~...;SS';·...·;.;..«·......,..;.....;.....;:;.;.........;..:..;:... Y. ........;O;:;.;...:...;•••••:.......;...;o............. y; .............. y.o.YH .................:.......;...;«O'-».Y~......:...:......... y.oN.oO.;O;:>.::;~;:;:;:;:;:~:;:;:~9.;:;:;:;:::;:;:;:;:O=-::The following examples illustrate how floating-point multiplication is performedon the TMS320C3x. For these examples, the implied most significant nonsignbit is made explicit.Example 4-1. Floating-Point Multiply (Both Mantissas = -2. D)Let(J. = -2.0 x 2a(exp) = 10.00000000000000000000000 x 2a(exp)b = -2.0 x 2b( exp) = 10.00000000000000000000000 x 2b( exp)where a and b are both represented in binary form according to the normalizedsingle-precision floating-point format. Then10.00000000000000000000000 x 2a(ex~x 10.00000000000000000000000 x 2b(ex~0100.0000000000000000000000000000000000000000000000 x 2(a(ex~ +b(ex~)To place this number in the proper normalized format, it is necessary to shiftthe mantissa two places to the right and add two to the exponent. This yields10.00000000000000000000000 x 2a(ex~x 10.00000000000000000000000 x 2b(exp)01.0000000000000000000000000000000000000000000000 x 2 (a( exp) +b( exp) +2)In floating-point multiplication, the exponent of the result may overflow. Thiscan occur when the exponents are initially added or when the exponent is modifiedduring normalization.Example 4-2. Floating-Point Multiply (Both Mantissas = 1.5)Leta = 1.5 x 2a(exp) = 01.10000000000000000000000 x 2a(exp)b = 1 .5 x 2b( exp) = 01.1 0000000000000000000000 x 2b( exp)where a and b are both represented in binary form according to the single-precisionfloating-point format. Then01.10000000000000000000000 x 2a(exp)x 01.10000000000000000000000 x 2b( exp)0010.0100000000000000000000000000000000000000000000 x 2 (a(ex~ +b(ex~)4-12Data Formats and Floating-Point Operation
Floating-Point Multiplication;:::::::::::::::::::::::::::::::::::::::::::::'::::::::::::::;:::::::::::::;:::::::;:::::::::::::::::::::::::::::::::::::::::::::::.:::::::::::::::::::::::::::::::::::::::::..;:;.;:;.;:::::::::::::::;::::::::......:;.;.;:;.;.;...;.;.....:...;...;.;.;....•..;:;.;...........;.........................................;.;•....;.............................;.;.........••...:....;.................;................................................................................................:.:.....:.......................',:.:.:.:.:.:.:.:::.:::::::.:.:::.:::::::::::::::::::::::::::::::::::::::.:::::::::::::::::::To place this number in the proper normalized format, it is necessary to shiftthe mantissa one place to the right and add one to the exponent. This yields01.100000000000000000000.00 x 2«( exp)x 01 .10000000000000000000000 x 2b( exp)01.00100000000000000000000000000000000000000000000 x 2 (0:( exp) +b(exp) + 1)Example 4-3. Floating-Point Multiply (Both Mantissas = 1.0)Letex. = 1.0 x 2a(exp) = 01.00000000000000000000000 x 2 a(exp)b = 1.0 x 2b(exp) = 01.00000000000000000000000 x 2b(exp)where a and b are both represented in binary form according to the single-precisionfloating-point format. Then01.0000000000000000000000.0 x 2a.(ex~x 01.00000000000000000000000 x 2b(ex~0001.0000000000000000000000000000000000000000000000 x 2 (a(exp) +b(exp))This number is in the proper normalized format. Therefore, no shift of the mantissaor modification of the exponent is necessary.These examples have shown cases where the product of two normalized numberscan be normalized with a shift of zero, one, or two. For all normalized inputswith the floating-point format used by the TMS320C3x, a normalized resultcan be produced by a shift of zero, one, or two.Example 4-4. Floating-Point Multiply Between Positive and Negative NumbersLetex. =1.0 x 2a.(exp) = 01.00000000000000000000000 x 2a(exp)b = -2.0 x 2b( exp) = 10.00000000000000000000000 x 2b( exp)Then01.00000000000000000000000 x 2 a (exp)x 10.00000000000000000000000 x 2b( exp)1110.0000000000000000000000000000000000000000000000 x 2 (ex( exp) +b( exp))Example 4-5. Floating-Point Multiply by ZeroThe result is c = - 2.0 x 2(et(exp) + b(exp))<strong>Al</strong>l multiplications by a floating-point zero yield a result of zero (f= 0, s = 0, andexp = -128).4-13
Floating-Point Addition and Subtraction4.5 Floating-Point Addition and SubtractionIn floating-point addition and subtraction, two floating-point numbers a and bcan be defined asa = a(man) x 2 a(exp)b = b(man) x 2 b(exp)The sum (or difference) of a and b can be defined asc=a±b= (a(man) ± (b(man) x 2 -(a(exp)-b(exp)))) x 2 a(exp),if a( exp) ~ b( exp)= ((a(man) x 2 -(b(exp)-a(exp))) ± b(man)) x 2 b(exp),if a( exp) < b( exp)The flowchart for floating-point addition is shown in Figure 4-10. Since thisflowchart assumes signed data, it is also appropriate for floating-point subtraction.lnthis figure, it is assumed that a(exp) :::; b(exp).ln step 1, the source exp·onentsare compared, and c(exp) is set equal to the largest of the two sourceexponents. In step 2, d is set to the difference of the two exponents. In step 3,the mantissa with the smallest exponent, in this case a(man), is right-shiftedd bits in order to align the mantissas. After the mantissas have been aligned,they are added (step 4).Steps 5 through 7 check for a special case of c(man). If c(man) is zero (step5), then c(exp) is set to its most negative value (step 8) to yield the correct representationof zero. If c(man) has overflowed c (step 6), then in step 9, c(man)is right-shifted one bit, and one is added to c(exp). In step.1 0, the result is normalized.In steps 11 and 12, special cases of c(exp) are tested. If c(exp) hasoverflowed, then c is set to the most positive extended-precision value if it ispositive; otherwise, it is set to the most negative extended-precision value.4-14Data Formats and Floating-Point Operation
Floating-Point Addition and Subtractiono::~y'o:~:e;:::o:;:::>?;:.~m~::;:::;~:::::::::::x::::::::;:;:::;:::::;o;:;:::;:".:;:;:::; :::::;:;:::;:;:::::;:::::;:;y.;:;o,::;:;~;:;:;o;:;:;:::;:~;:::::,;,;:::;:».:.:::.::::;:::::;.::;:::::::~.:;:::::;:::;:::::::::::;:::;:;:;.::::;:::;:;::::::.;·::;:::::::::::~:::·;:::::;:::::::;o::::::;o)';:;s:;·::::;V;'~:::;';:;':·:·;':·N.;o;..;·:::·:.,;:;·.·.·::.....•••...•••••••••••...•••.........-.:.·... w,y.M'.:.·.v. ... :.:.·.~:.·.·.~;..:...:..... :.:~:.:o"N.>·~:::.:~../.;om..::~;w..;:;:.:.:D:;:.:.:::;:::;:;:;:::::;:;:;:::;:::::::::::::::::;eFigure 4-10. Flowchart for Floating-Point Addition(14 )a(man) b(man) a (exp) b(exp)~ J, (1 )Compare exponents~, ~,(3)<strong>Al</strong>ign mantissasa(man) = a(man) > > dDiscard LSBs to keepa(man) inIf a( exp) < = b( exp)c( exp) = b( exp)elsec( exp) = ex( exp)[Assume for simplicitythat a(exp) < < = b(exp)]~ +extended-precision (2) Subtract exponentsfloating-point format~ d = b( exp) - ex( exp)IW(4)1 Add mantissas II c (man) = a(man) + b(man) J-bTest for special cases of c(man)(5) (6) (7)c(man) = 0 Overflow of c(man)k =# leadingnon-significantsign bits,I,c(man) = c(man) > > 1c( exp) = c( exp) + 1Discard LSBs to keep inextended-precisionfloating-point format ,,. (9)~,. (8)I c(man) < < kI c(exp) = -128 Ic( exp) = c( exp) - kJ, u ~Test for special cases of c( exp)(11 ) (12) (13)c( exp) overflow ' c( exp) underflow c( exp) in range~ Jr ~,If c(man) > 0,set c to zero (15)set c to mostc(exp) = -128positive value.c(man) = 0If c(man) < 0,set c to mostnegative value.•u1 (16)I•Set c to final result Ic=a+b4-15
Floating-Point Addition and SubtractionExample 4-6. Floating-Point AdditionThe following examples describe the floating-point addition and subtractionoperations. It is assumed that the data is in the extended-precisionfloating-point format.In the case of two normalized numbers to be summed, letex = 1 .5 = 01 .1 000000000000000000000000000000 x 20b = 0.5 = 01.0000000000000000000000000000000 x 2-1It is necessary to shift b to the right by one so that ex and b have the same exponent.This yieldsThenb = 0.5 = 00.1000000000000000000000000000000 x 2001.10000000000000000000000000000000 x 20+ 00.10000000000000000000000000000000 x 20010.00000000000000000000000000000000 x 20As in the case of multiplication, it is necessary to shift the binary point one placeto the left and to add one to the exponent. This yields01.1000000000000000000000000000000 x 20± 00.1000000000000000000000000000000 x 2001.0000000000000000000000000000000 x 21Example 4-7. Floating-Point Subtraction~ subtraction is performed in this example. Letex = 01.0000000000000000000000000000001. x 20b = 01.0000000000000000000000000000000 x 20The operation to be performed is ex - b. The mantissas are already aligned becausethe two numbers have the same exponent. The result is a large cancellationof the upper bits, as shown below.01.0000000000000000000000000000001 x 20- 01.0000000000000000000000000000000 x 2000.0000000000000000000000000000001 x 204-16Data Formats and Floating-Point Operation
Normalization Using the NORM Instruction::.m!";e;.~;~~::-~».««~~:::;~~m~:
Normalizationthe NORM InstructionExample 4-10. NORM InstructionAssume that an extended-precision register contains the valueman = 00000000000000000001000000000001, exp = 0When the normalization is performed on a number assumed to be unnormalized,the binary point is assumed to beman = 0.0000000000000000001000000000001, exp = 0This number is then sign-extended one bit so that the mantissa contains 33bits.man = 00.0000000000000000001000000000001, exp = 0The intermediate result after the most significant nonsign bit is located and theshift performed is:man = 01.0000000000010000000000000000000, exp = -19The final 32-bit value output after removing the redundant bit is:man = 00000000000010000000000000000000, exp = -19The NORM instruction is useful for counting the number of leading zeros orleading ones in a 32-bit field. If the exponent is initially zero, the absolute valueof the final value of the exponent is the number of leading ones or zeros. Thisinstruction is also useful for manipulating un normalized floating-point numbers.4-19
Rounding: The RND InstructionN.~;~;~~.w;:~%~~.:.:;:;:~;lo!'.:.:,:;:«.:;:;:;:;:;:::::;:::::: :::;:;:::;::~:;:;:::::;:;:;:;:';:;:::>:;:':"'>''';'.:;.;:.y..:.:.:::;:.:;:.:••••;... ::;:;:;.;.~;•.:;:;s:;.;::.-;.;.;.;.;~:'.:::::;...;y;·;o;';9.·;o.. ;·;·;·;·::.:»;·;·;:;:::;o:~v.xy.;o;o;o;y.",;,;o.,::;,;o;o;.;o;v;o;--"»;•• ~;."",,;.;.;o;.;.;.;o;o;,;o.,;,.,,,;,;o;o;O.~.'Y. ... ~;o;0;.;0;.;0;.;:;:; ....;0•••..:-;0•..,;,;.;0••;0;...;.;.;•••;...;.;.;.;.;.;.....;o».:o;.;o;o;o;.;,;.;o;.;... ;~...;o;.....;.. yN; .. v.;.;o;o.~ ......;.o.. o;o;y;y.v.;~;o;.,; o;v.;:>y.~~r.x~~9.>.';'o;~~4.7 Rounding: The RND InstructionThe RND instruction rounds a number from the extended-precision floating-pointformat to the single-precision floating-point format. Rounding is similarto floating-point addition. Given the number a to be rounded, the followingoperation is performed first.c = a(man) x 2n(exp) + (1 x 2n(exp)-24)Next, a conversion from extended-precision floating-point to single-precisionfloating-point format is performed. Given the extended-precision floating-pointvalue, the rounding, rnd( ), is performed as shown in Figure 4-12.4-20Data Formats and Floating-Point Operation
Floating-Point to Integer Conversion;::::::=;::::::::::::-:::::::::::::::::::-.$:::;:::::;:::::::::::::::::::::::::::::;:::::::::::::::::;:::;:::;::::::::::::::::::::::;:::::::::::::::::::::::::::::::::::::::::::::::%:::::::::::::::;:::::::;:::::::::;t.:;:::::::::::::::::::;:::::::::::::::::::::::::::::::::::::::;::.;:;:::::::::::::::::::;::::.:::::,;:::;,:::,:,::;:;,;,;:;,;:;:::;,::::;,:.;.:::.,.;::.::::::;::.;.;0;:.: .. ;.;::;;.;:;:;.:: •••••••• ; •• : •• ;; •••• ; •• :.:.:.: ••• :.: ••• : ...... ;:.:::;:;:.:.:;:;.;~.; •••• :;: •• ;:; •• :.:;:::.:.:.~: ••••• :.:;:;:;:;:.: ••• :.:::;:;:;:;:;:::;:;:;:;:o:::::;:;:;:::;:::;:::;:::::::;:::::;:;:::.~::;:::;:::::;:;:".:::Figure 4-13.Flowchart for Floating-Point to Integer Conversion by FIX Instructionsa1Test for special cases of a(exp)a(exp) > 301OverflowIf a(man) > 0,c = most positive integer.If a(man) < 0,C = most negative integer.a(exp) in rangers = 31 - a(exp)ShiftC = a(man) > > rsI~ IISet c to final resultI~Irc = fix(a)4-23
Integer to Floating-Point Conversion Using the Float Instruction"*"~~;~::;~;·::~~::;~~:::~;~;~::;:O~;~::::::-~-::::;:Of.$::('f(O!O:"(.::'-;:::o::,v.::;:::::::;:::;:;:::-~:::;:::;:::::o:;:::;:::;:::~~;:;:;:::o:;:::;:;:;-;:;:::>:;:::::;:o:;:>~...::::::;:::::;.::::::::::::;:::;:::;:;:;:::::::::::::::::::::::::::;::::s:::::;o;.::::::::::::::::::::::::.:::::0:::::::;';:::;';:::;:::::;'-:;';:::;';':';:::::;';';·;.;::::-::::::::;·;::::v:·:·:::·;·;:;,:::·:.;·;·;·;·;·;·;·;·;::·;·;·;·;·;o;·;·:f";:;·:';·;·;';':·::~::::::":;:;·;·;o:.::::::: :.;0:.:;.;.;.;:::;.;:;.;.;.;:::;.;:;.:::::::::.::::;-;.:::.;:;.;:::::;:;:;f"'::;:;:::;:';:::;:::-~::~:::;:;::~:::;~4.9 Integer to Floating-Point Conversion Using the FLOAT InstructionInteger to floating-point conversion, using the FLOAT instruction, allows single-precisionintegers to be converted to extended-precision floating-point numbers.The flowchart for this conversion is shown in Figure 4-14.Figure 4-14.Flowchart for Integer to Floating-Point Conversion by FLOAT Instructionsex~c (man) = exc (exp) = 30J,Test for special cases of c (man)c (man) = 0uc (exp) = -128ILeading nonsignificantsign bits.k = # leadingnonsignificant,,, sign bitsc (man) =c (man) < < kc (exp) = 30 - kI~Remove most significant nonsign bit~,ISet c to final result~I~c = float (ex)4-24 Data Formats and Floating-Point Operation
=========---~-----------------------------------'-Ii_Addressing_ I
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Types of Addressing~.:;~.;:.:; •• ~ ••• .,;~!.~!.!;!>:.!;!;.;!;:;:;:;: •• ;:~;.;:;:.~:;::~:o!;:;!;!::::;:;:o:;:;~;:;~;:;:.:;!.:::::::;:;:;:;::.;:;:;:;:;:;:::;.;!;:;:::::o:;:::::;o;:;:;o;:;,,::,,::.~::y;::::~:;::::~::~::~~~y.;~:;y';:::::::;y';o;::::~;::::::.;:::::::;:;:::::;.;.;.,; .. ::.;:::;-::::;.::;:;:;::':';';y';.,.:o;.;::.;.;..,;.;~~.; .. :;.; .. .,;::.;.:.: ... ; ...... ..::::;o;·;:;::::,,·:·;s::,,·:y:O;"::';';':':';';:;O~;:;"':'~;::SO;::::"!>';::.::;o; ... ~:::::.;.;~:.;.:::.:.:,,::::o;::.:.;s.;o::::;.;::~:;s::.;::.;::';';«:::;'.:;:::;s:;:.::::::';:;s::::::::::::::::::::·5.1 Types of AddressingSix types of addressing allow access of data from memory, registers, and theinstruction word:• Register• Direct• Indirect• Short-immediate• Long-immediate• PC-relativeSome types of addressing are appropriate for some instructions and not others.For this reason, the types of addressing are used in the five differentgroups of addressing modes as follows:Q General addressing modes (G):• Register• Direct• Indirect• 'Short-immediateQ Three-operand addressing modes (T):II Register• IndirectQ Parallel addressing modes (P):.. Register• IndirectQLong-immediate addressing mode• Long-immediateQ Conditional-branch addressing modes (8):• RegisterII PC-relativeThe six types of addressing are discussed first, followed by the five groups ofaddressing modes.5-2Addressing
Types of Addressing5.1.1 Register AddressingIn register addressing, a CPU register contains the operand, as shown in thisexample:ABSF Rl i Rl = I RliThe syntax for the CPU registers, the assembler syntax, and the assignedfunction for those registers are listed in Table 5-1.Table 5-1. CPU Register/Assembler Syntax and FunctionCPU Register Assembler AssignedAddress Syntax FunctionOOh RO Extended-precision register01h R1 Extended-precision register02h R2 Extended-precision register03h R3 Extended-precision register04h R4 Extended-precision registerOSh RS Extended-precision register06h R6 Extended-precision register07h R7 Extended-precision register08h ARO Auxiliary register09h AR1 Auxiliary registerOAh AR2 Auxiliary registerOBh AR3 Auxiliary registerOCh AR4 Auxiliary registerODh ARS Auxiliary registerOEh AR6 Auxiliary registerOFH AR7 Auxiliary register10h DP Data-page pointer11h IRO Index register 012h IR1 Index register 113h BK Block-size register14h SP Active stack pointer1Sh ST Status register16h IE CPU/DMA interrupt enable17h IF CPU interrupt flags18h 10F liD flags19h RS Repeat start address1Ah RE Repeat end address1Bh RC Repeat counter5-3
Types of Addressing;:::::::::::::::::;:::::;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;::::::::::::::::::::::::::::::::::::::::::::.::::::::::::::::::::::::::::::::::::::::::::::;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;:::::::::::::::::::::::::::::::::::::;::::::::.;:::::;.::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;':::::::::::::::::::::::;'::.:;:::.:::;::::::::::::::::::::::::::::!':;:::::':;:;:;:::::::::::::::::::::::::::::::::::::::::::::::Table 5-2. Indirect Addressing (Concluded)Mod Field10000100011001010011101001010110110101111100011001LEGEND:addrARnIRndisp++circ( )%8Syntax Operation DescriptionIndirect Addressing with Index Register IR1*+ ARn(IR1) addr = ARn + IR1 With preindex (IR1) add* - ARn(IR1) addr = ARn -IR1 With preindex (IR1) subtract* ++ ARn(IR1) addr ARn + IR1 With preindex (IR1) addARn = ARn + IR1and modify* - - ARn(IR1) addr ARn -IR1 With preindex (IR1) subtractARn = ARn -IR1and modify* ARn ++ (IR1) addr ARn With postindex (IR1 ) addARn = ARn + IR1and modify*ARn-- (IR1) addr ARn With postindex (IR1) subtractARn = ARn - IR1and modify* ARn ++ (IR1)% addr ARn With postindex (IR1) addARn = circ(ARn + IR1) and circular modify* ARn -- (IR1)% addr ARn With postindex (IR1) subtractARn = circ(ARn - IR1) and circular modify*ARnIndirect Addressing (Special Cases)addr = ARnIndirect* ARn ++ (IRO)8 addr = ARnARn = 8(ARn + IRO)memory addressauxiliary register ARO - AR7index register IRO or IR1displacementadd and modifysubtract and modifyaddress in circular addressingwhere circular addressing is performedwhere bit-reversed addressing is performedWith postindex (IRO) addand bit-reversed modify5-7
Types of Addressing;:;:;:;:;:;:~;:;:.!;:;:::::;:;:;:::::::;:;:;:;:;:;:;:;:;:;:;:;:;:::::::::::::::::::::::::::;:;:;:::;:::;:~;::::~:::::::::::::::::::::::::::::::::;::::::::::::::::::::::::::::::x::::;:::;:;:;:::::;:::::;-;:::;:;:::~:;:;:::::::;::::::::y.::;:::::;:;:;:::;:;:::;:;:::;:::::::;:;:::::;:;::.:.::;:;%:::;~;.::::;·;:::;::·:::·;·::;·::::;·::::::::::::::::;·::::::;·;O;':x::;::.::;.::;.::::::;::::::::.;o.;.;.;.;:::;:~;.;.;.:.;.:.:.:::.::;.;:;.;:;:;.;.;.;.;::::.;.::::;.;::.:::.:.::;~;~.;.:v.;:::;:;.;:;:;:;:::;.;:;y::::::;::::.::;:;:;:;:::~:;:::::::::::;:::::::::::::::::=:::;:::;''';':::::::::;0;Example 5-2. Auxiliary Register IndirectAn auxiliary register (ARn) contains the address of the operand to be fetched.Operation:operand address = ARnAssembler Syntax:*ARnModification Field:11000ARn31xxaddress31operandExample 5-3. Indirect With Predisplacement AddThe address of the operand to be fetched is the sum of an auxiliary register(ARn) and the displacement (disp). The displacement is either an eight-bit unsignedinteger contained in the instruction word or an implied value of 1.Operation:Assembler Syntax:operand address = ARn+ disp*+ARn(disp)Modification Field: 0000031 24 23 0ARn ---I x x IaddressI31 8 7 0diSPI 0 0 ... 0 01 integer, ~ (+)31 ~0IoperandI5-8Addressing
Types of Addressing~::::::;!::;:;~:;:;:;:::;:"':y'::o:;:;:::o:::::::;.;::-;:;:;o;:::::;:;:;:;:;:;:-.. ;:::;::::~~::::;:;:;:;:;:;:::::;:::;:~::::::::::::;:::";:;:O:;~o!'~::::;:::::::;S:::";:;:::W.::;:O~;:;:;:::::;~O;~::::;:::;:..;:;-::~::::::.:>:..;:;S ::y';::::::y'::;o;:::~~:::~;:::;:;:;~;:o!;~;.~::::.:::::;Y.;:::;:~;:.:::;:o!;:::.v."::"::O!;:I.;:~".y.•• o!.:.:o!.~.'; ••';:;:::.... ::~.:;:o!::;:::::::;:;·~::;:;:.:::::::;:::::.:::::;:.:::':::::::;'W.;:~6·;~"",v..!>'':b:':':':";~~':::.:':.~.:"Y,o:':':""~::~':::;:::.!::;*-;:';:~::):;:;::::':;:;:::(Example 5-4. Indirect With Predisplacement SubtractThe address of the operand to be fetched is the contents of an auxiliary register(ARn) minus the displacement (disp). The displacement is either an eight-bitunsigned integer contained in the instruction word or an implied value of 1.Operation:Assembler Syntax:Modification Field: 00001operand address = ARn- disp*- ARn(disp)31 24 23 0ARn~~x _________ x~I __________ ad_d_re_s_s ______ ~ ___ 131 8 7 odisp I 0 0 ... 0 o I integer~ (-)31J, ooperandExample 5-5. Indirect With Predisplacement Add and ModifyThe address of the operand to be fetched is the sum of an auxiliary register(ARn) and the displacement (disp). The displacement is either an eight-bit unsignedinteger contained in the instruction word or an implied value of 1. Afterthe data is fetched, the auxiliary register is updated with the address gener-~ed. .Operation:Assembler Syntax:Modification Field:operand address = ARn + dispARn = ARn + disp*++ARn(disp)00010312423oARnxxaddress31disp I 0 0 ... 08 7 oo I integer ~ (..+ )_----'31operand5-9
Types of AddressingExample 5-6. Indirect With Predisplacement Subtract and ModifyThe address of the operand to be fetched is the contents of an auxiliary register(ARn) minus the displacement (disp). The displacement is either an eight-bitunsigned integer contained in the instruction word or an implied value of 1. Afterthe data is fetched, the auxiliary register is updated with the address generated.Operation:Assembler Syntax:Modification Field:operand address = ARn- dispARn= ARn+ disp*- - ARn(disp)00011312423oARnxxaddress31disp I 0 0 ... 08 7 oo I integer J-. (.-)_---'31operandExample 5-7. Indirect With Postdisplacement Add and ModifyThe address of the operand to be fetched is the contents of an auxiliary register(ARn). After the operand is fetched, the displacement (disp) is added to theauxiliary register. The displacement is either an eight-bit unsigned integer containedin the instruction word or an implied value of 1.Operation:Assembler Syntax:Modification Field: 00100operand address = ARnARn = ARn+disp*ARn++ (disp)31 24 230ARn x x address31 8 7 0disp I 0 0 ... 0 o I integer j-.(+)31operand5-10Addressing
Types of Addressing;r.;:.~-:;.. :;%:;r..:;:.:;:;:.!.:-:;r.;:;r.;~;:;~.. .-':;:;:.::.::>:::::::::::::::::::::::::~,::-.. ~:::,;!;r.;:;:;:::::::::::;:::::::;o.::::::;~;:;::::::~::.;::::~:;:::::-.:~.:::';,~x:~~;:.·::~:;o;o;r.?»':"~:::::;-:""N;·;o,:?;o;o;-;y;o.;."",;,;::::,;9.;O:·:,;o;o::~.;o" ..;:;o;o;,;",::::;o... ~u.:-»,;·u ..;o;",~·::;oH"";o;Y',.«o;o;o;y"'~"':.v;."/..;...;w.... o.h'W~ ................. ~;ow;.v-.~.~.o;,"·;w;O~::';~,::"'O»>·;~"'N...:·:«o.o;.".~.y.y'x·:9''''«9,:v.;O::9);·;Y.>:::;~:.~~::;::::z: ..:~:;o;:."SExample 5-10. Indirect With Postdisplacement Subtract and Circular ModifyThe address of the operand to be fetched is the contents of an auxiliary register(ARn). After the operand is fetched, the displacement (disp) is subtracted fromthe contents of the auxiliary register using circular addressing. This result isused to update the auxiliary register. The displacement is either an eight-bit unsignedinteger contained in the instruction word or an implied value of 1.Operation:Assembler Syntax:Modification Field:operand address = ARnARn= circ(ARn- disp)* ARn- - (disp)%00111ARn31x24 23xaddress31disp I 00 ... 08 7 0 (%)o I integer ~ (~)31operandExample 5-11. Indirect With Preindex AddThe address of the operand to be fetched is the sum of an auxiliary register(ARn) and an index register (IRO or IR1).Operation:Assembler Syntax:operand address = ARn+ IR m*+ ARn(lRm)Modification Field:0100010000ifm = 0ifm = 1ARn --.f31 24 23.... x _____ x .... I""-____ a_d_d_re_ss ___ ~-....o31 24 23 oIRm~ .... x ____ x-""I ______ in_d_ex _______31operandI----.(+)1 o5-12Addressing
Types of Addressing~;:;:;.x:;:>:~;:~:=::::~::;.:;: ... ~:;~:;:>:;:;:;:~;:;:>:;::-:;~:;)%:;:;:;:.;~:;:.;:-:;:.:;:;:;:;):~::;~::)~:::;::::::):;:-~::
Types of Addressing~~'-"Y.~~::,*",;~;:i:'~w.-=:-;::-';:~~~o!~o?~~~~'-o!~~~~~:Y,
Groups of Addressing Modes::-'::*;';:;:';~:;~;:~;::~:;:';:::;:'::::;:;:;:~;:;:;:;:;:;:;::::-;::X:;:;*;:::;:::,::,::;:;:;:::::::::;:::;:::::::,::::::::::;,v.::;:::::::::::::::::::::::;::,,,;:;:::::::::::::;:;~:::::::::;:::;:::::::::;:::~;:~;::*;::::::::::»:J:~):;Y;:;:;:::;::Y;:::::;:::;::::::y;:.,:;:;:::::::::::::;s.:;:::::::;.;o;:~,:::::::::::;:;::.:::;o;y>.;::::.::;:::::;:::;:;:::::::;:::::::::;:::::;:~:::::::;:;::y,:,..:~;~::;:;..'.:~.y.:.:;:.:.!ow~.:.:.v....:::.:::;:;:~;:b:::::::o!.::::-;::::!o..:.:;::y'o:«:::::::::::::::::::»:::
Groups of Addressing Modes;.:;:::;:;:~:;:;:;~@.~:;:;:::::::;:;:~:::;:;m~:>::Y.4:::::::::;::-::~":::::::y.:::*:::::::::9.::::;:;S:::::~::;::::9>,::::::."!:::~:::;:;:::"q£.:::::"':::::>';:;':I:::9.~:::::::~:::::::;:::"-::9.;X::::::;::::;:::::::::::::;:::::::;:::::::::::::::::::::;:;:;:::;:;:::;:::;:;:;:,:y.:::~::~6::%·;:::::;:::~;:::: .. ::s::·m:.y.;:::::;:;:::~;'~:::~"!~:~::::9.::::::;.~::~::~.:.:.y.:. .. :~.~ ... !>!.:.:.:~.!>:.:~':':.W.6:OS:::::«~:::::;9.O:O':;:';:::::::~::::O»:;:::;:::::";9.~:::::::::::eIn indirect addressing of the three-operand addressing mode, displacements(if used) are allowed to be 0 or 1, and the index registers (IRO and IR1) can beused. The displacement of 1 is implied and is not explicitly coded in the instructionword.Figure 5-3. Encoding for Three-Operand Addressing Modes31 2928 23 22 21 20 16 15 13 12 11 10 8 7 5 4 3 20 0 1 . operation 0 0 dst o 0 0 I src1 000 src20 0 1 operation 0 1 dst modnIARn 000 src20 0 1 operation 1 0 dst o 0 0 I src1 modn ARn0 0 1 operation 1 1 dst modn ARn modm ARmIT SRC1 SRC2o5.2.3 Parallel Addressing ModesFigure 5-4. Encoding for Parallel Addressing ModesInstructions that use parallel addressing, indicated by II (two vertical bars), allowfor the greatest amount of parallelism possible. The destination operandsare indicated as d1 and d2, signifying dst1 and dst2, respectively (see Figure6-4). The source operands, signified by src1 and src2, use the extended-precisionregisters. The parallel operation to be performed is called operation.31 3029 26 25 2423 2221 1918 1615 10 11 8 7 3 2osrC3src4The parallel addressing mode (P) field specifies how the operands are to beused, i.e., whether they are source or destination. The specific relationship betweenthe P field and the operands is detailed in the description of the individualparallel instructions (see Chapter 10). However, the operands are always encodedin the same way. Bits 31 and 30 are set to the value of 10, indicating paralleladdressing mode instructions. Bits 25 and 24 specify the parallel addressingmode (P) field, which defines how bits 21 - 0 are to be interpreted for addressingthe src operands. Bits 21 - 19 are used to define the src1 address,bits 18 - 16 to define the src2address, bits 15 - 8 the src3 address, and bits7 - Ohe src 4 address. The notations modn and modm indicate which modificationfield goes with which ARn or ARm (auxiliary register) field, respectively.The parallel addressing operands are listed below.5-21
Circular Addressing..;e;:~::;:*::::*~;:::;:;:.~:..:*w. /.;o..:~~.:;*,.(.:~~:>.w..::9.::;:"~::>'~.::-:::".::::~:>.:::::::::x-..'!:::7."..::;:::::::".::::::·;.:....:·::l:~;o::;,.w:;o>::~../.(.:~y..($:"Q.~~>.»;.x«':..::"..;o;o;o»;.;o.::;o::;.-.::-:::;y:y:....»:y;o;.;o;o;o:·:-:·;o;-;·~..:·;o:::.;0;0;0;0;.;0;0;0;0;.;0;0;0;0;0;0;0;0;.;.;.:-.,.;.••;.;.»;.;.;.;.;.»....;0:.;.;.;•• o,,;·;o;·:·;,;·;o;::·;·;o;o;o;o;.:o:o;v;.;.;.;.»;.;.;.;.;.;.; ...:·;o;...;o;o:-;o:·;o;«o;«o;o;o:y;o;';o»;:;o:~6:::x9;o;o::;·:·:!xo;o~~:;:::>'~:::::;5.3 Circular AddressingMany algorithms, such as convolution and correlation, require the implementationof a circular buffer in memory. In convolution and correlation, the circularbuffer is used to implement a sliding window that contains the most recent datato be processed. As new data is brought in, the new data overwrites the oldestdata. Key to the implementation of a circular buffer is the implementation of acircular addressing mode. This section describes the circular addressing modeof the TMS320C3x.'The blocksize register (BK) specifies the size of the circular buffer. The bottomof the circular buffer is specified by the first bit (counting from the most significantbit to the least significant bit) in the lower 16 bits of the BK register, plusa user-selected auxiliary register (ARn). With the location of the first 1 bit specifiedas bit N, the address at the top of the buffer is referred to as the effectivebase (EB) and is equal to bits 31 through (N+ 1) of ARn with bits N-1 througho of EB being zero and bit N being one.Figure 5-7 illustrates the relationships between the blocksize register (BK),the auxiliary registers (ARn), the bottom of the circular buffer, the top of the circularbuffer, and the index into the circular buffer.A circular buffer of size R must start on an N-bit boundary (Le., N LSBs of addressare 0) where N is the smallest integer that satisfies 2N > R. <strong>Al</strong>so, the valueR must be loaded into the BK register. For example, a 31-word circular buffermust start at an address whose 5 LSBs are 0 (Le.,XXXXXXXX~XXXXXXXXXOOOOOOb) and 31 must be loaded into BK.5-24Addressing
Circular Addressing~;o:.~; •• ~;~;~;:;:;!.~~!;!.~.~;:~;:;~:::.~:;:.~;:;:~:.~:;:;:.~;7..~.~:,.~;:;:::~:;::.~;::~~ .. ~;:;:;:;:::;:;:::;:;~-::;:::;::::o;-;::::::.;:;:;:::::;:;"~"''':::::-;:::-::;7.;:::::::::::;:::~:: .. -::::::::: .... :::::::::;:;.;:: .. ::,;:;.; ......... ;-:::::::::::-:.;:;.;.;::0:: .. :.:::::.:::::0;.;:;.;.;.;0;.:.:.;::.:::.;.:0:.;.;.; ..... :.;.;0;.;.;0;::.;.;.;.;.;.:-:.;.;.;.;0;';';';';':::::::::';';-;';';';';';0;0:::':';:;';':::';';';:;o;.;o;:: ... ;::.:.::~; .. :;.;::.:.;.;.:.:o;.;::::::.~;.;.;.::::;:;:;:;';:;':';';:;':::-:::::'::::::::::;:::;0;:::::::::::::::::::::::::::::::;:;:::;::::::::::::::::::In circular addressing, index refers to the N LSBs of the auxiliary register selected,and step is the quantity being added to or subtracted from the auxiliaryregister. Follow these two rules when you use circular addressing:~ The step used must be less than or equal to the blocksize.QThe first time the circular queue is addressed, the auxiliary register mustbe pointing to an element in the circular queue.Figure 5-8. Circular Buffer ImplementationThe algorithm for circular addressing is as follows:If 0 ~ index + step < BK:index = index + step.Else if index + step ~ BK:index = index + step - BK.Else if index + step < 0:index = index + step + BK.Figure 5-8 shows how the circular buffer is implemented. It illustrates the relationshipof the quantities generated and the elements in the circular buffer.AddressDataEffective Base (EB> I ...._H_._._. H ___ I __31 N + 1 N o Top of Circular Buffero_. _.._0_--, Element 0Element 131 N + 1 N oAuxiliary Register (ARn>II-_H_._._" H _____ L_. _."_L_--,Element (N LSBs of ARn)31 N + 1 N 0 Last ElementH ... H LSBs BK -7 Last Element + 15-26 Addressing
Circular AddressingFigure 5-9. Circular Addressing ExampleFigure 5-9 gives an example of the operation of circular addressing. Assumingthat all ARs are four bits, let ARO = 0000, and BK = 0110 (blocksize of 6).This example shows a sequence of modifications and the resulting value ofARO. It also shows how the pointer steps through the circular queue with a varietyof step sizes (both incrementing and decrementing).* ARO '++ (5)% ARO*ARO ++ (2)%ARO*ARO - - (3)% ARO*ARO++(6)%ARO*ARO - -% ARO*AROARO0 (Oth value)5 (1 st value)1 (2nd value)4 (3rd value)4 (4th value)3 (5th value)ValueDataOth~ Element 02nd ~ Element 1Element 25th ~ Element 34th,3rd~ Element 41 st ~Element 5 (Last Element)Last Element + 1Addresso234565-27
Bit-Reversed Addressing~~-::O:::::::O:::::;::--~"::::m::::::;:::::'l:i::~:::;'::Z:;:;::~::~ ..-:::::::::::~::-:;::~:::::;;"..
System and User Stack Management5.5 System and User Stack ManagementThe TMS320C3x provides a dedicated system stack pointer (SP) for buildingstacks in memory. The auxiliary registers can also be used to build a varietyof more general linear lists. This section discusses the implementation of thefollowing types of linear lists:StackQueueOequeA linear list for which all insertions and deletions are made at oneend of the list.A linear Iistfor which all insertions are made at one end of the list,and all deletions are made at the other end.A double-ended queue linear list for which insertions and deletionsare made at either end of the list.Figure 5-13. System Stack ConfigurationThe system stack pointer (SP) is a 32-bit register that contains the address ofthe top of the system stack. The system stack fills from low-memory addressto high-memory address (see Figure 5-13). The SP always points to the lastelement pushed onto the stack. A push performs a preincrement, and a popperforms a postdecrement of the system stack pointer.The program counter is pushed onto the system stack on subroutine calls,traps, and interrupts. It is popped from the system stack on returns. The systemstack can be pushed and popped using the PUSH, POP, PUSHF, and POPFinstructions.Low MemoryBottom of StackSP -7 Top of Stack(Free)High Memory5-30 Addressing
System and User Stack Management~::~::::!':::::;:::;::~::~';::~~Q.;y.~w.~::?C~::x::~~::~y.~::%~y.~:::::"'::Y-h:::"'(.::w.,(.6::::::~:::::~~:;.::::~-=~~a.!"~::W'«-:;~~-5!~S!C~::::::!~y''::::::?;~:~:S!-w..(.::y..(.:"
~ ______ P_ro_g __ ra_m __ F_lo_w __ C_o_n_t_r_o_I ________________________________ ~11_1II1II
_program Flow Control~-----------'
Repeat Modes6.1 Repeat ModesTable 6-1. Repeat-Mode RegistersThe repeat modes of the TMS320C3x can implement zero-overhead looping.For many algorithms, most execution time is spent in an inner kernel of code.Using the repeat modes allows these time-critical sections of code to be executedin the shortest possible time.The TMS320C3x provides two instructions to support zero-overhead looping:RPTB (repeat a block of code) and RPTS (repeat a single instruction). RPTBcauses a block of code to be repeated a specified number of times. RPTScauses a single instruction to be repeated a number of times and reduces thebus traffic by fetching the instruction only once.Three registers (RS, RE, and RC) are associated with the updating of the programcounter when it is updated in a repeat mode. Table 6-1 describes theseregisters.RegisterRSRERCFunctionRepeat Start Address Register. Holds the address of the·first instructionof the block of code to be repeated.Repeat End Address Register. Holds the address of the last instructionof the block of code to be repeated.Repeat-Count Register. Contains one less than the number of timesthe block remains to be repeated. For exampJe. to execute a block Ntimes. load N-1 into RC.6.1.1 Repeat-Mode InitializationTwo bits are important to the operation of RPTB and RPTS: the RM and S bits.The RM (repeat-mode flag) bit in the status register specifies whether the processoris running in the repeat mode. If RM = 0, fetches are not made in repeatmode. If RM = 1, fetches are made in repeat mode.The S bit is hidden from the user but is necessary to fully describe the operationof RPTB and RPTS. If S = 0, the CPU is not performing fetches in the repeatsinglemode. If S = 1 and RM = 1, the CPU is performing fetches in the repeatsinglemode.The correct operation of the repeat modes requires that all of the above registersand status register fields be initialized correctly. The RPTB and RPTS instructionsperform this initialization in slightly different ways (see Sections6.1.2 and 6.1.3).6-2Program Flow Control
Modes6.1.2 RPTB InitializationWhen RPTS src is executed, the following operations take place:1) PC + 1 -t RS2) src -t RE3) 1 -t RM status register bit4) 0 -t S bit.Step 1 loads the start address of the block into RS. Step 2 loads the src intothe RE (end address of the block). The srcoperand is a 24-bit value containedin the instruction word. Step 3 sets the status register to indicate the repeatmode of operation. Step 4 indicates that this is the repeat block mode of operation.The last bit of information required is the number of times to repeat the block.The value is determined by properly initializing the RC (repeat count) register.Since the execution of RPTS does not load the RC; you must load this registeryourself. The typical setup of the block repeat operation is shown below.LDI 15,RC 15 -t RC, LOOP will be executed 16 timesRPTB LOOP LOOP -t RE, PC + 1 RS, 1 -t RM, 0 -t SThe repeat modes repeat a block of code at least once in a typical operation.The repeat counter should be loaded with one less than the number of timesto repeat the block; i.e., a value of 0 in RC repeats the block of code one time.<strong>Al</strong>l block repeats initiated by RPTS can be interrupted.6.1.3 RPTS InitializationWhen RPTS src is executed, the following sequence of operations occurs:1 ) PC + 1 -t RS2) PC + 1 -t RE3) 1 -t RM status register bit4) 1 -t S bit5) src-t RCThe RPTS instruction loads all registers and mode bits necessaryforthe operationof the single instruction repeat mode. Step 1 loads the start address ofthe block into RS. Step 2 loads the end address into the RE (end address ofthe block). Since this is a repeat of a single instruction, the start address andthe end address are the same. Step 3 sets the status register to indicate the6-3
Modes6.1.4 Repeat-Mode OperationFigure 6-1. Repeat-Mode Control <strong>Al</strong>gorithmrepeat mode of operation. Step 4 indicates that this is the repeat single-instructionmode of operation. The operand src is loaded into RC, as in Step 5 andthe following instruction is executed src+ 1 times.Repeats of a single instruction initiated by RPTS are not interruptible, becausethe RPTS fetches the instruction word only once and then keeps it in the instructionregister for reuse. An interrupt would cause the instruction word to belost. The refetching of the instruction word from the instruction register reducesmemory accesses and, in effect, acts as a one-word program cache. If it is necessaryto have a single instruction that is repeatable and interruptible, you canuse the RPTS instruction.The information in the repeat-mode registers and associated control bits isused to control the modification of the PC when the fetches are being madein repeat mode. The repeat modes compare the contents of the RE registerwith the program counter (PC). If they match and the repeat counter is nonnegative,the repeat coulter is decremented, the PC is loaded with the repeat startaddress, and the processing continues. The fetches and appropriate statusbits are modified as necessary. Note that the repeat counter (RC) is never modifiedwhen RM is O. The maximum number of repeats occurs.when RC =080000000h. This will result in 080000001 h repetitions. The detailed algorithmfor the update of the PC is described in Figure 6-1.if RM == 1if S == 1if first time throughfetch instruction from memoryelsefetch instruction from IRRC - 1 -7 RCif RC < 0o -7 ST (RM)o -7 SPC + 1 -7 PCelse if S == 0fetch instruction from memoryif PC == RERC - 1 -7 RCif RC ~ 0RS -7 PCelse if RC < 0o -7 ST (RM)o -7 SPC + 1 -7 PCIf in repeat mode (RPTB or RPTS)If RPTSIf this is the first fetchFetch instruction from memoryIf not the first fetchFetch instruction from IRDecrement RCIf RC is negativeRepeat single mode completedTurn off repeat mode bitClear SIncrement PCIf RPTBFetch instruction from memoryIf this is the end of the blockDe-:;rement RCIf RC is not negativeSet PC to start of blockIf RC is negativeTurn off repeat·mode bitsClear SIncrement PC6-4Program Flow Control
Repeat ModesExample 6-1. RPTB OperationThe RPTB and RPTS are four-cycle instructions. These four cycles ofoverhead are incurred only on the first pass through the loop. <strong>Al</strong>l subsequentpasses through the loop are accomplished with zero cycles of overhead. InExample 6-1, the block of code from STLOOP to ENDLOP is repeated sixteentimes.STLOOPLDIRPTB15, RCEND LOPLoad repeat counter with 15E~ecute the block of codefrom STLOOP to END LOP 16 timesEND LOPUsing the repeat block mode of modifying the PC. facilitates analysis of whatwould happen in the case of branches within the block. Assume that the nextvalue of the PC will be either PC + 1 or the contents of the RS register. It is thusapparent that this method of block repeat allows many amount of branchingwithin the repeated block. Execution can go anywhere within the user's codevia interrupts, subroutine calls, etc. For proper modification of the loop counter,the last instruction of the loop must be fetched. You can stop the repeating ofthe loop prior to completion by writing a 0 into the repeatcounter orwriting 0into the RM bit of the status register.Since the block repeat modes modify the program counter, other instructionscannot modify the program counter at the same time. Two rules apply here:1) The last instruction in the block (or the only instruction in a block ofsize one) cannot be a Bcond, BR, DBcond, CALL, CALLcond, TRAPcond,RETlcond, RETScond, IDLE, RPTB, or RPTS. Example 6-2shows an incorrectly placed standard branch.2) None of the last four instructions from the bottom of the block (or theonly instruction in a block of size one) can be a BcondD, BRD, orDBcondD. Example 6-3 shows an incorrectly placed delayed branch.If either of these rules is violated, the PC will be undefined.6-5
ModesExample 6-2. Incorrectly Placed Standard BranchSTLOOPLDIRPTBlS,RCEND LOPLoad repeat counter with 15Exec~te block of codefrom STLOOP to ENDLOP 16 timesEND LOP BR OOPSThis branch violates rule 1Example 6-3. Incorrectly Placed Delayed BranchSTLOOPLDIRPTB15,RCEND LOPLoad repeat counter with 15Execute block of codefrom STLOOP to END LOP 16 timesEND LOPBRDADDFMPYFSUBFOOPSThis branch violates rule 2Block repeats (RPTB) are nestable. Since all of the control is defined by theRS, RE, Re, and ST registers, these registers must be saved and stored in ordertonest block repeats. The RM bit in the status register can be used to determineif the block repeat mode is active. For example, if you write an interruptseNice routine that requires the use of RPTB, it is possible that the interruptassociated with the routine may occur during another block repeat. The interruptseNice routine can check the RM bit. If this bit is set, the interrupt routinesaves RS, RE, Re, and ST. The interrupt routine can then perform a block repeat.Before returning to the interrupted routine, the interrupt routine restoresRS, RE, Re, and ST. If the RM bit is not set, you don't need to save and restorethese registers.6-6Program Flow Control
I..JGla"o:::a .. Branches6.2 Delayed BranchesExample 6-4. Incorrectly Placed Delayed BranchesThe TMS320C3x offers two main types of branching: standard and delayed.Standard branches empty the pipeline before performing the branch; this guaranteescorrect management of the program counter and results in aTMS320C3x branch taking four cycles. Included in this class are repeats, calls,returns, and traps.Delayed branches on the TMS320C3x do not empty the pipeline, but ratherguarantee that the next three instructions will execute before the programcounter is modified by the branch. The result is a branch that requires only asingle cycle, thus making the speed of the delayed branch very close to the optimalblock repeat modes of the TMS320C3x. However, unlike block repeatmodes, delayed branches may be used in situations other than looping. Everydelayed branch has a standard branch counterpart that is used when adelayed branch cannot be used. The delayed branches of the TMS320C3x areBcondD, BRD, and DBconaD.Conditional delayed branches use the conditions that exist at the end of theinstruction immediately preceding the delayed branch. They do not dependupon the instructions following the delayed branch. The condition flags are setby a previous instruction only when the destination register is one of the extended-precisionregisters (RO-R7) or when one of the compare instructions(CMPF, CMPF3, CMPI, CMPI3, TSTB, or TSTB3) is executed. Delayedbranches guarantee that the next three instructio·ns will execute, regardlessof other pipeline conflicts.When a delayed branch is fetched, it remains pending until the three followinginstructions are executed. None of the three instruction~ that follow a delayedbranch can be Bcond, BconaD, BR, BRD, DBcond, DBcondD, CALL, CALLcond,TRAPcond, RETlcond, RETScond, RPTB, RPTS, or IDLE. (seeExample 6-4).Delayed branches disable interrupts until the three instructions following thedelayed branch are completed. This is independent of whether or not thebranch is taken.If delayed branches are used incorrectly, the PC will be undefined.Bl: BD LlNOPNOPB2: B L2 This branch is incorrectly placedNOPNOPNOP6-7
Calls,and Returns6.3 Calls, Traps, and ReturnsCalls and traps provide a means of executing a subroutine or function whileproviding a return to the calling routine.The CALL, CALLcond, and TRAPcond instructions store the value of the PCon the stack before changing the PC's contents. The stack thus provides areturn using either the RETScond or RETlcond instruction.QThe CALL instruction places the next PC value on the stack and placesthe src (source) operand into the PC. The src is a 24-bit immediate value.Figure 6-2 shows CALL response timing.Q The CALLcondinstruction is similar to the CALL instruction (above) exceptthat (1) it executes only if a specific condition is true (the 20 conditions- including unconditional- are listed in Section 10.2) and (2) thesrc is either a PC-relative displacement or in register addressing mode.The condition flags are set by a previous instruction only when the destinationregister is one of the extended-precision registers (RO-R7) or whenone of the compare instructions (CMPF, CMPF3, CMPI, CMPI3, TSTB, orTSTB3) is executed.QQQThe TRAPcondinstruction also executes only if a specific condition is true(same conditions as for the CALLcond instruction). When executing, (1)interrupts are disabled with 0 written to bit GIE of the ST, (2) the next PCvalue is stored on the stack, and (3) a vector is retrieved from one of theaddresses 20h to 3Fh and loaded into the PC. The particular address isidentified 9Y a trap number in the instruction. Using the RETlcondto returnre-enables interrupts.RETScond returns execution from any of the above three instructions bypopping the top of the stack to the PC. To execute, the specified conditionmust be true. Conditions are the same as for the CALLcond instruction.RETlcond retu rns from traps or calls sim ilar to the RETScond ( above) withthe addition that RETlcond also sets the GIE bit of the Status Registerwhich thus enables all interrupts whose enabling bit is set to 1. Conditionsare the same as for the CALLcond instruction.Functionally, calls and traps accomplish the same task (i.e., a subfunction iscalled, executed, and control then returned to the calling function. Traps offerseveral advantages:1) Interrupts are automatically disabled when a trap is executed. This allowscritical code to execute without risk of being interrupted. Thus, traps aregenerally terminated with a RETlcond instruction to re-enable interrupts.2) You can use traps to indirectly call functions. This is particularly beneficialwhen a kernel of code contains the basic subfunctions to be used by applications.In this case, the functions in the kernel can be modified and relocatedwithout recompiling each application.6-8Program Flow Control
Calls,ReturnsFigure 6-2. CALL Response TimingH3I Fetch CALLStore PCon StackFetch FirstInstruction ofCALL RoutineH1ADDR ----------------------------------~(~~~S~ta_ck~JX_ Address . .1})-_Fi_rs_i_~d_S;_~~_~tionData-------------------~(~--~~-6-9
Interlocked UDeratror7S6.4 Interlocked OperationsTable 6-2. Interlocked OperationsOne of the most common multiprocessing configurations is the sharing of globalmemory by multiple processors. In order for multiple processors to accessthis global memory and share data in a coherent manner, some sort of arbitrationor handshaking is necessary. This requirement for arbitration is the purposeof the TMS320C3x interlocked operations.The TMS320C3x provides a flexible means of multiprocessor support with fiveinstructions, referred to as interlocked operations. Through the use of externalsignals, these instructions provide powerful synchronization mechanisms.They also guarantee the integrity of the communication and result in a highspeedoperation. The interlocked-operation instruction group is listed inTable 6-2.Mnemonic Description OperationLOFI Load floating-point value into a register, Signal interlockedinterlockedsrc ----7 dstLOll Load integer into a register, interlocked Signal interlockedsrc ----7 dstSIGI Signal, interlocked Signal interlockedClear interlockSTFI Store floating-point value to memory, src ----7 dstinterlockedClear interlockSTII Store integer to memory, interlocked src ----7 dstClear interlockThe interlocked operations use the two external flag pins, XFO and XF1. XFOmust be configured as an output pin, and XF1 as an input pin. When configuredin this manner, XFO signals an interlock operation request, and XF1 acts as anacknowledge signal forthe requested interlocked operation. In this mode, XFOand XF1 are treated as active-low signals.The external timing for the interlocked loads and stores is the same as for standardload and stores. The interlocked loads and stores may be extended likestandard accesses by using the appropriate ready signal (RDYint or XRDYint).(RDYint and XRDYint are a combination of external ready input and softwarewait states. Refer to Chapter 7, External Bus Operation, for more informationon ready generation.)The LDFI and LDII instructions perform the following actions:1) Simultaneously set XFO to 0 and begin a read cycle. The timing of XFOis similar to that of the address bus during a read cycle.6-1 0 Program Flow Control
Interlocked Um~ratJ'Ons2) Execute an LOF or LOI instruction and extend the read cycle until XF1is set to 0 and a ready (ROYint or XROYint) is signalled.3) Leave XFO set to 0 and end the read cycle.The read/write operation is identical to any other read/write cycle except for thespecial use of XFO and XF1. The srcoperand for LOFI and LOll is always a director indirect memory address. XFO is setto 0 only if the srcis located off-chip;i.e., STRB, MSTRB, or IOSTRB is active, orthe srcis one of the on-chip peripherals.If on-chip memory is accessed, then XFO is not asserted, and the operationis as an LOF or LOI from internal memory.The STFI and STII instructions perform .the following operations:1) Simultaneously set XFO to 1 and begin a write cycle. The timing of XFOis similar to that of the address bus during a write cycle.2) Execute an STF or STI instruction and extend the write cycle until a ready(ROYint or XROYint) is signaled.As in the case for LOFI and LOll, the dst of STFI and STII affects XFO. If dstis located off-chip (STRB, MSTRB, or IOSTRB is active) or the dst is one ofthe on-chip peripherals, XFO is set to a 1 . If on-chip memory is accessed, thenXFO is not asserted and the operations are as an STF or STI to internalmemory.The SIGI instruction functions as follows:1) Sets XFO to O.2) Idles until XF1 is set to O.3) Sets XFO to 1 and ends the operation.While the LOFI, LOll, and SIGI instructions are waiting for XF1 to be set to 0,you can interrupt them. LOFI and LOll require a ready signal (ROYint orXROYint) in order to be interrupted. Because interrupts are taken on bus cycleboundaries (see Section 6.6), an interrupt may be taken any time after a validready. This allows you to implement protection mechanisms against deadlockconditions by interrupting an interlocked load that has taken too long. Upon returnfrom the interrupt, the next instruction is executed. The STFI and STII instructionsare not interruptible. Since the STFI and STII instructions completewhen ready is signaled, the delay until an interrupt can occur is the same asfor any other instruction.Interlocked operations can be used to implement a busy-waiting loop, to manipulatea multiprocessor counter, to implement a simple semaphore mechanism,orto perform synchronization between two TMS320C3xs. The followingexamples illustrate the usefulness of the interlocked operations instructions.6-11
InterlockedExample 6-5. Busy-Waiting LoopExample 6-5 shows the implementation of a busy-waiting loop. If locationLOCK is the interlock for a critical section of code, and a nonzero means thelock is busy, the algorithm for a busy-waiting loop can be used as shown.LDI 1,ROL1: LDII @LOCK,R1STIIBNZRO,@LOCKExample 6-6. Multiprocessor Counter ManipulationLlPut 1 in RO'Interlocked operation begunContents of LOCK ~ R1Put RO (= 1) into LOCK, XFO 1Interlocked operation endedKeep trying until LOCK = 0Example 6~6 shows how a location COU NT may contain a cou nt of the nu mberof times a particular operation needs to be performed. This operation may beperformed by any processor in the system. If the count is zero, the processorwaits until it is nonzero before beginning processing. The example also showsthe algorithm for modifying COUNT correctly.CT: ORLDIIBZSUBISTII4,IOF@COUNT,RlCT1,RlRl,@COUNTXFO = 1Interlocked operation endedInterlocked operation begunContents of COUNT ~ RlIf COUNT = 0, keep tryingDecrement Rl(= COUNT)Update COUNT, XFO = 1Interlocked operation endedFigure 6-3 illustrates multiple TMS320C3xs sharing global memory and usingthe interlocked instructions as in Example 6-7, Example 6-8, andExample 6-9.6-.12Program Flow Control
Interlocked Op,eratfor7SFigure 6-3. Multiple TMS320C3x5 Sharing Global MemoryGlobal Memory...~ ~ .~.....Ja:0 ~ a:0 « I-
Interlocked nn,CI,.~tin,.,,,,Example 6-7. Implementation of V(S)The TMS320C3x code for V(S) is shown in Example 6-7, and code for P(S)is shown in Example 6-8. Compare the code in Example 6-8 to the code inExample 6-6.V: LDII @S,ROADDI 1,ROSTII RO,@S; Interlocked read of S begins (XFO 0); Contents of S ~ RO; Increment RO (= S); Update S, end interlock (XFO 0)Example 6-8. Implementation of P(S)P: OR 4,IOFLDII @S,ROBZSUBISTIIP1,RORO,@S; End interlock (XFO = 1); Inter~ocked read of S begins; Contents of S ~ RO; If S = 0, go to P and try again; Decrement RO (= S); Update S, end interlock (XFO = 1)The SIGI operation may be used to synchronize, at an instruction level, multipleTMS320C3xs. Consider two processors connected as shown inFigure 6-4. The code for the two processors is shown in Example 6-9.Figure 6-4. Zero-Logic Interconnect of TMS320C3xsTMS320C3x #1 TMS320C3x #2~ ______ ~_:_~~~. ___ ~1~~:~:0~1 ______ ~Processor #1 runs until it executes the SIGI. It then waits until processor #2executes a SIGI. At this point, the two processors have synchronized and continueexecution.6-14Program Flow Control
Reset Operation6.5 Reset OperationTable 6-3. Pin Operation at ResetThe TMS320C3x supports a nonmaskable external reset signal (RESET),which is used to perform system reset. This section discusses the reset operation.At powerup, the state of the TMS320C3x processor is undefined. You can usethe RESET signal to place the processor in a known state. This signal mustbe asserted low for 10 or more H1 clock cycles to guarantee a system reset.H1 is an output clock signal generated by the TMS320C3x (see Chapter 13 formore information).Reset affects the other pins on the device in either a synchronous or asynchronousmanner. The synchronous reset is gated by the TMS320C3x's internalclocks. The async~ronous reset directly affects the pins, and is faster than thesynchronous reset.Table 6-3 shows the state of the TMS320C3x's pins afterRESET = O. Each pin is described according to whether the pin is reset synchronouslyor asynchronously.tSignal # Pins Operation at ResetPrimary Interface (61 Pins)031-00 32 Synchronous reset. Placed in high-impedance state.A23-AO 24 Synchronous reset. Placed in high-impedance state.R/W 1 Synchronous reset. Placed in high-impedance state.STRB 1 Synchronous reset. Deasserted by going to a high level.ROY 1 Reset has no effect.HOLD 1 Reset has no effect.HOLDA 1 Reset has no effect.Expansion Interface (49 Pins)tXD31-XDO 32 Synchronous reset. Placed in high-impedance state.XA12-XAO 13 Synchronous reset. Placed in high-impedance state.XRIW 1 Synchronous reset. Placed in high-impedance state.MSTRB 1 Synchronous reset. Deasserted by going to a high level.IOSTRB 1 Synchronous reset. Deasserted by going to a high level.XROY 1 Reset has no effect.Control Signals (9 Pins)RESET 1 Reset input pinINT3-INTO 4 Reset has no effect.lACK 1 Synchronous reset. Deasserted by going to a high level.MC/MP or 1 Reset has no effect.MCBUMPXF1-XFO 2 Asynchronous reset. Placed in high-impedance state.Present only on TMS320C306-16 Program Flow Control
Reset UDjgrairJOnTable 6-3.Pin Operation at Reset (Continued)Signal # Pins Operation at ResetSerial Port 0 Signals (6 Pins)ClKXO 1 Asynchronous reset. Placed in high-impedance state.OXO 1 Asynchronous reset. Placed in high-impedance state.FSXO 1 Asynchronous reset. Placed in high-impedance state.CLKRO 1 Asynchronous reset. Placed in high-impedance state.ORO 1 Asynchronous reset. Placed in high-impedance state.FSRO 1 Asynchronous reset. Placed in high-impedance state.Serial Port 1 Signals (6 Pins) tClKX1 1 Asynchronous reset. Placed in high-impedance state.OX1 1 Asynchronous reset. Placed in high-impedance state.FSX1 1 Asynchronous reset. Placed in high-impedance state.ClKR1 1 Asynchronous reset. Placed in high-impedance state.OR1 1 Asynchronous reset. Placed in high-impedance state.FSR1 1 Asynchronous reset. Placed in high-impedance state.Timer 0 Signal (1 Pin)TClKO 1 Asynchronous reset. Placed in high-impedance state.Timer 1 Signal (1 Pin)TClK1 1 Asynchronous reset. Placed in high-impedance state.Supply and Oscillator Signals (29 Pins)VOO(3-0) 4 Reset has no effect.IOOVOO (1,0) 2 Reset has no effect.AOVOO (1,0) 2 Reset has no effect.POVOO 1 Reset has no effect.OOVOO (1,0) 2 Reset has no effect.MOVOO 1 Reset has no effect.VSS(3-0) 4 Reset has no effect.OVSS(3-0) 2 Reset has no effect.CVSS (1,0) 2 Reset has no effect.IVSS 1 Reset has no effect.VBBP 1 Reset has no effect.SUBS 1 Reset has no effect.Xi 1 Reset has no effect.X2/ClKIN 1 Reset has no effect.Hi 1 Synchronous reset. Will go to its initial state when RESETmakes a 1 to ° transition. See Appendix A.H3 1 Synchronous reset. Will go to its initial state when RESETmakes a 1 to ° transition. See Appendix A.t Present only on TMS320C306-17
Reset nnlp.r;~ti(llnTable 6-3.Pin Operation at Reset (Continued)tSignal #Plns Operation at ResetEmulation, Test, and Reserved (18 Pins)EMUO 1 Undefined.EMU1 1 Undefined.EMU2 1 Undefined.EMU3 1 Undefined.EMU4/SHZ 1 Undefined.EMust 1 Undefined.EMust 1 Undefined.RSVot 1 Undefined.RSV1t 1 Undefined.RSV2t 1 Undefined.RSV3t 1 Undefined.RSV4t 1 Undefined.RSVSt 1 Undefined.Rsvst 1 Undefined.RSV7t 1 Undefined.Rsvat 1 Undefined.RSV9t 1 Undefined.RSV10t 1 Undefined.Present only on TMS320C306-18 Program Flow Control
Reset nn.Q"""~;"nAt system reset, the following additional operations are performed:Q The peripherals are reset. This is a synchronous operation. The peripheralreset is described in Chapter 8.QQCiThe following CPU registers are loaded with zero:11 ST (CPU status register)• IE (CPU/DMA interrupt enable flags)II IF (CPU interrupt flags)I! 10F (I/O flags)The reset vector is read from memory location Oh and loaded into the PC.This vector contains the start address of the system reset routine.Execution begins. Refer to Section 11.1 for an example of a processorinitialization routine.Multiple TMS320C3xs driven by the same system clock may be reset and synchronized.When the 1 to 0 transition of RESET occurs, the processor is placedon a well-defined internal phase, and all of the TMS320C3xs will come up onthe same internal phase.6-19
6.6 InterruptsFigure 6-5. Interrupt Logic Functional DiagramThe TMS320C3x supports multiple internal and external interrupts, which canbe used for a variety of applications. This section discusses the operation ofthese interrupts.A functional diagram of the logic used to implement the external interrupt inputsis shown in Figure 6-5; the logic for internal interrupts is similar. Additional informationregarding internal interrupts can be found in Chapter 8.Internal InterruptSet SignalEINTn(CPU)GIE(CPU)H1 H3 H1RESETInternal InterruptClear/Acknowledge GIE(DMA)SignalEINTn(DMA)InternalInterruptProcessorToControlSectionExternal interrupts are synchronized internally, as illustrated by the three flipflopsclocked by H 1 and H3. Once synchronized, the interrupt input will set the, corresponding interrupt flag register (IF) bit if the interrupt is active.External interrupts are latched internally on the falling edge of H1 (see the datasheet for timing information). An external interrupt must be held low for at leastone H1/H3 cycle to be recognized by the TMS320C3x. Interrupts should beheld low for only one or two H 1 falling edges. If the interrupt is held low for threeor more H1 falling edges, multiple interrupts may be recognized.6.6.1 Interrupt Control BitsWhen a particular interrupt is processed by the CPU or DMAcontroller, the correspondinginterrupt flag bit is cleared by the internal interrupt acknowledgesignal. It should be noted, however, that if INTn is still low when the interruptacknowledge signal ,occurs, the interrupt flag bit will be cleared only for onecycle and then set again because INTn is still low. Accordingly, it is theoreticallypossible that, depending on when the IF register is read, this bit may be zeroeven though INTn is zero. When the TMS320C3x is reset, zero is written to theinterrupt fla'g register, thereby clearing all pending interrupts.6-20Program Flow Control
The interrupt flag register bits may be read and written under software control.Writing a 1 to an IF register bit sets the associated interrupt flag to 1. Similarly,writing a 0 resets the corresponding interrupt flag to O. In this way, all interruptsmay be triggered and/or cleared through software. Since the interrupts flagsmay be read, the interrupt pins may be polled in software when an interrupt-driveninterface is not required.Internal interrupts operate in a similar manner. In the IF register, the bit correspondingto an internal interrupt may be read and written through software.Writing a 1 sets the interrupt latch, and writing a 0 clears it. <strong>Al</strong>l internal interruptsare one H1/H3 cycle in length.The CPU global interrupt enable bit (GIE), located in the CPU status register(ST), controls all CPU interrupts. <strong>Al</strong>l DMA interrupts are controlled by the DMAglobal interrupt enable bit, which is not dependent upon ST(GIE) and is localto the DMA. The DMA global interrupt enable bit is dependent, in part, uponthe state of the DMA SYNCH bits. It is not directly accessible through software(see Chapter 8). The AND of the interrupt flag bit and the interrupt enables isthen connected to the interrupt processor.To provide for maximum performance in servicing interrupts, the interrupt acknowledge(lACK) instruction is provided. lACK drives the lACK pin and performsa dummy read. The read is performed from the address specified by thelACK instruction operand. When lACK is used, it typically is placed in the earlyportion of an interrupt service routine. For certain applications, it may be bettersuited at the end of the interrupt service routine or be totally unnecessary.6.6.2 TMS320C3x Interrupt ConsiderationsGive careful consideration to TMS320C3x interrupts, especially if user modificationsare made to the status register when the global interrupt enable (GIE)bit is set. This can result in the GIE bit being erroneously set or reset as describedin the following paragraphs.The GIE bit is setto 0 (zero) by an interrupt. This may cause a processing errorif any code following within two cycles of the interrupt recognition attempts toread or modify the status register. For example, if the status register is beingpushed onto the stack, it will be stored incorrectly if an interrupt was acknowledgedtwo cycles before the store instruction.When an interrupt signal is recognized, the TMS320C3x continues executingthe instructions already in the read and decode phases in the pipeline. However,because the interrupt is acknowledged, theGIE bit is reset to 0, and thestore instruction already in the pipeline will store the wrong status register value.For example, if the program is something like:6-21
InterruptsNOPinterrupt recognized --> LDIMPYIPUSHPOP@V ADDR, ARl*AR1, ROSTSTthe PUSH ST instruction will save the ST contents in memory, which includesGIE = O. Since the programmer expects GIE = 1, the POP ST instruction willput the wrong status register value into the ST.A similar situation may occur if the GIE bit=1 and an instruction executes thatintends to modify the other status bits and leave the GIE bit set. In the aboveexample, this erroneous setting would occur if the interrupt is recognized twocycles before the POP ST instruction. In that case, the interrupt would clearthe GIE bit, butthe execution ofthe POP instruction would setthe GIE bit. Sincethe interrupt has been recognized, the interrupt service routine will be enteredwith interrupts enabled, rather than disabled as expected.One solution is to make use of traps. For example, you can use TRAP 0 to resetGIE and use TRAP 1 to set GIE. This is accomplished by making TRAP 0 andTRAP 1 be the instructions RETS and RETI, respectively.Another alternative incorporates the following code fragment, which protectsfrom modifying or saving of the status register by disabling interrupts throughthe interrupt enable register:PUSHLDI-NOPNOPANDPOPIE0, IEODFFFh, STIESave IE registerClear IE registerSet GIE 0• Added instructions toavoid pipeline problems.• 2 NOPs or useful instructions• Instruction that reads orwrites to ST register.Added instructionto avoid pipelineproblems.6.6.3 TMS320C30 Interrupt ConsiderationsThe TMS320C30 has two additional exceptions to the interrupt operation.1) The status register global interrupt enable (GIE) bit may be erroneouslyreset to 0 (disabled setting) if all of the following conditions are true:Q a conditional trap instruction (TRAPcond) has been fetched,Q' the condition for the trap is false, andQa pipeline conflict has occurred, resulting in a delay in the decode orread phases of the instruction.During the decode phase of a conditional trap, interrupts are temporarilydisabled to guarantee that the trap will execute prior to a subsequent inter-6-22Program Flow Control
upt. If a pipeline conflict occurs, causing a delay in execution of the conditionaltrap, the interrupt disabled condition may become the last knowncondition of the GIE biLln the case that the trap condition is false, interruptswill be permanently disabled until the GIE bit is intentionally set. Thecondition does not present itself when the trap condition is true, becausenormal operation of the instruction causes the GIE to be reset, and standardcoding practice will set the GIE to a one before the trap routine is exited.Several instruction sequences that may cause pipeline conflicts havebeen found:a)b)c)d) STII ILDITRAPcondLDINOPTRAPcondSTITRAPcondLDILDITRAPcondmem, SPnmem,SPnSP,memnRz,*ARy*ARz,Ry*ARz,RwnOther similar conditions may also cause a delay in the execution. Therefore,the following solution is recommended to avoid or rectify the problem.Insert two NOP instructions immediately prior to the TRAPcond instruction.One NOP is insufficient in some cases, as illustrated in case 2 above.This eliminates opportunity for any pipeline conflicts in the immediatelypreceding instructions and enables the conditional trap instruction to ex- ,ecute without delays.2) Asynchronous accesses to the interrupt flag register (IF) may cause theTMS320C3x to fail to recognize and service an interrupt. This may occurwhen an interrupt is generated and is ready to be latched into the IF registeron the same cycle that the IF is being written to by the CPU.The logic currently gives the CPU write priority; consequently, the assertedinterrupt may be lost. This is particularly true if the asserted interrupt hasbeen generated internally, such as a DMA interrupt. This situation mayarise as a result of a decision to poll certain interrupts or a desire to clearpending interrupts due to a long pulse width. Forthe case of the long pulsewidth, the interrupt may be generated after the CPU responds to the interruptand attempts to automatically clear it by the interrupt vector process.The recommended solution is not to use the int'errupt polling technique butto design the external interrupt inputs to have pulse widths between 1 and2 instruction cycles in length. The alternative to strict polling is to periodicallyenable and disable' the interrupts that would be polled, thereby allow-6-23
ing the normal interrupt vectoring to take place; that automatically clearsthe interrupt flag without affecting other interrupts. In the event there is aneed to clear a pending interrupt, it is recommended that a memory locationbe used to indicate that the interrupt is invalid. Then the interrupt serviceroutine can read that location, clear it (if the pending interrupt is invalid),and return immediately. The following code fragments show how adummy interrupt due to a long interrupt pulse might be handled:ISR_n: PUSHPUSHSTDPPUSH ROLDI 0, DPLDI @DUMMY INT, ROBNN ISR n STARTSTI DP, -@DUMMY_INTPOP ROPOP DPPOP STRETIISR n START: .ISR n END:LDIANDBZLDILDISTIPOPPOPPOPRETIINT Fn, ROIF, -ROISR n END0, DPOFFFFh, RORO, @DUMMY_INTRODPSTSave registersClear Data Page PointerIf DUMMY INT is 0 or positive,go to ISR n STARTSet DUMMY-INT = 0Housekeeping, return from interruptnormal interrupt service routinecode goes hereIf ones in IF reg matchINT Fn, exit ISROtherwise clearDP and set, DUMMY_I NT negative & e:·:itExit ISR6-24Program Flow Control
6.6.4 Prioritization and ControlThe CPU controls all prioritization of interrupts (see Table 6-4 for reset and interrupt vector locations and priorities). If the DMA is not using interrupts for synchronizationof transfers, it will not be affected by the processing of the CPUinterrupts. If the CPU is involved in a pipeline conflict (branch, register, ormemory), it will not respond to the interrupts until that conflict is resolved. It istherefore possible to interrupt the CPU and DMA simultaneously with the sameor different interrupts and, in effect, synchronize their activities. For example,it may be necessary to cause a high-priority DMA transfer that avoids bus conflictswith the CPU, i.e., make the DMA higher priority than the CPU. This maybe accomplished by using an interrupt that causes the CPU to trap to an interruptroutine that contains an I DLE instruction. Then if the same interrupt is usedto synchronize DMA transfers, the DMA transfercountercan be used to generatean interrupt and, thus to return control to the CPU following the DMA transfer.Since the DMA and CPU share the same set of interrupt flags, the DMA mayclearan interruptflag before the CPU can respond to it. Forexample, if the CPUinterrupts are disabled, the DMA can respond to interrupts and thus clear theassociated interrupt flags.Table 6-4. Reset and Interrupt Vector LocationsReset or Vector Priority FunctionInterruptLocationRESET Oh a External reset signal input on the RESETpin.INTO 1h 1 External interrupt input on the INTO pin.INT1 2h 2 External interrupt input on the INT1 pin.INT2 3h 3 External interrupt input on the INT2 pin.INT3 4h 4 External interrupt input on the INT3 pin.XINTO 5h 5 Internal interrupt generated when serial-porta transmit buffer is empty.RINTO 6h 6 Internal interrupt generated when serial-porta receive buffer is full.XINT1 t 7h 7 Internal interrupt generated when serial-port1 transmit buffer is empty.RINT1 t 8h 8 Internal interrupt generated when serial-port1 receive buffer is full.TINTO 9h 9 Internal interrupt generated by timer O.TINT1 OAh 10 Internal interrupt generated by timer 1.DINT aSh 11 Internal interrupt generated by DMA controllerO.t Reserved on TMS320C316-25
If there is a delayed branch in the pipeline, interrupts are held pending until afterthe branch. If the interrupt occurs in the first cycle of the fetch of an instruction,the fetched instruction is discarded (not executed), and the address of that instructionis pushed to the top of the system stack. If the interrupt occurs afterthe first cycle of the fetch, in the case of a multicycle fetch due to wait states,that instruction is executed and the address of the next instruction to be fetchedis pushed to the top of the system stack. If no program fetch is occurring, thenno new fetch is performed. After the address of the appropriate instruction hasbeen pushed, the interrupt vector is fetched and loaded into the PC, and executioncontinues.The TMS320C3x allows the CPU and DMA to respond to and process interruptsin parallel. Figure 6-6 shows interrupt processing flow. The interrupts arepolled and the CPU and DMA begin processing them. In the interrupt flow pertainingto the CPU, the interrupt flag corresponding to the highest-priority enabledinterrupt is cleared, and GIE is set to o. The CPU completes all fetchedinstructions. The interrupt vector is fetched and loaded into the PC, and theCPU continues execution. The DMA cycle is similar to that for the CPU. Afterthe pertinent interrupt flag is cleared, the DMA proceeds according to the statusof the SYNCH bits in the DMA global control register.6-26Program Flow Control
Figure 6-6. Interrupt ProcessingNoIf EnabledInterrupt IsA CPU InterruptIf EnabledInterrupt IsA DMA InterruptClear Interrupt Flag CPUGIE f- 0Clear Interrupt FlagComplete <strong>Al</strong>l FetchedInstructionsDMA Proceeds BasedUpon Synch BitPC ~ *(++SP)Fetch Interrupt VectorDMA ContinuesCPU Continues6-27
6-28 Program Flow Control
External Bus Operation'.",;";'
_External Bus Operation"------------------'
External Interface Control Registers~;(~~~««~~.(..xx..,,*~~.x:~~&..::.z:-.:"~..xx:;:~::.:x.,,*~~~::~~,*,.x:;*;.;(.X::-.::;(~.::x::::=,«::::-.c::~~.(,,*:a-.x:::
External Interface Control Registers::;~:;:;~;:;:,=;:;:;:;:;:;:;:;::~.:;:;:;:"-:::;:;:;:;:::;:;:;:;:::::::;:;:::::'.:::::;:::;:;:;:::::::::"~;:::::::::;:::;:::~::::;:;:;:::::::~~;,,"!;:;:::;:;:.:::;:;.;:.::.;:;:.:::::::;:::;:::::;:.:::::::~~:«-:::::;:;:;w.'(,:::;:::::;o;o;O:::::::::::~:::::::::;:::::::~:::;:::;6::~;:::::~~;:;:"'::O;:::::;::"Q::;O:;O:::"'::'~';O/.;:::;::~:~::::;~::",,:::::,:,:: ::::;.;.::;«.;::.:.:.;.;.:.;::::.::;.:.;o:.~.::::::;o.;.;.;~::::;o;:;':::::';:::::;:;:::"";':';S';:;:;:::::;9;';Y;::%:::;O;O;O::::~:::,,::;::9,'::::;::';O;:~::;:::::::~:::::;:;:;::~::::7.1.2 Expansion-Bus Control RegisterFigure 7-3. Expansion-Bus Control RegisterThe expansion bus control register is a 32-bit register that contains control bitsfor the expansion bus (see Figure 7-3 and Table 7-2).15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0NOTE: xx = reserved bit, read as O.R = read, W = write.RIW RIW R/W RIW RIWTable 7-2. Expansion-Bus Control Register Bits SummaryBit Name Reset FunctionValue2- 0 Reserved 000 Read as O.4-3 SWW 11 Software wait-state generation. In conjunction with the WTQNT,this 2-bit field defines the mode of wait-state generation. It is setto 1 1 at reset.7-5 WTCNT 111 Software wait mode. This 3-bit field specifies the number of cyclesto use when in software wait mode for the generation of internalwait states. The range is zero (WTCNT. = 0 0 0) to seven( WTCNT = 1 1 1) H 1/H3 clock cycles. It is set to 1 1 1 at reset.31-8 Reserved 0--0 Read as O.7-4 External Bus Operation
External Interface7.2 Externallnteiiace TimingThis section discusses functional timing of operations on the primary bus andthe expansion bus, the TMS320C3x's two independent parallel buses. Detailedtiming specifications for all TMS320C3x signals are contained in Chapter13, TMS320C3x Signal Descriptions and Electrical Characteristics.The parallel buses implement three mutually exclusive address spaces distin- -guished through the use of three separate control signals: STRB, MSTRB, andIOSTRB. The SfRi3 signal controls accesses on the primary bus, and theMSTRB and IOSTRB control accesses on the expansion bus. Since the twobuses are independent, two accesses may be made in parallel.With the exception of bank switching and the external HOLD function (discussedlater in this section), timing of primary bus cycles and MSTRB expansionbus cycles are identical and are discussed collectively. The acronym(M)STRB is used in references that pertain equally to STRB and MSTRB. Similarly,(X)RIW, (X)A, (X)D, and (X)RDY are used to symbolize the equivalentprimary and expansion bus signals. The IOSTRB expansion bus cycles aretimed differently and are discussed independently.7.2.1 Primary-Bus Cycles<strong>Al</strong>l bus cycles comprise integral numbers of H1 clock cycles. One H1 cycle isdefined to be from one falling edge of H1 to the next falling edge of H1. Forfullspeed(zero wait-state) accesses, writes take two H1 cycles and reads takeone cycle; however, if the read follows a write, the read takes two cycles.Thisapplies to both the primary bus and the MSTRB expansion bus access. Recallthat, internally (from the perspective of the CPU and DMA), writes require onlyone cycle if no accesses to that interface are in progress. The following discussionspertain to zero wait-state accesses unless otherwise specified.The (M)STRB signal is lowforthe active portion of both reads and writes, whichlasts one H1 cycle. Additionally, before and after the active portion-(M)STRBlow-of writes only, there is a transition cycle of H1. Duringthis transition cycle, the following occur:1) (M)STRB is high.2) If required, (X}RIW changes state on H1 rising.3) If required, address changes on H1 rising if the previous H1 cycle was theactive portion of a write. If the previous H1 cycle was a read, addresschanges on H1 falling.7-5
External InterfaceFigure 7-5. Write-Write-Read for (M)STRB = 0Figure 7-5 illustrates a write-write-read sequence for (M)STRB active and nowait states. The address and data written are held valid approximately one-halfcycle after (M)STRB changes.H3H1(M)STRB,(X)R/W~/." /. ,A(X)A: X X(X)D Write Data Write Data(X)RDY \:1 \;1I/.II,-----....----->cI7-7
External InterfaceFigure 7-6 illustrates a read cycle with one wait state. Since (X)RDY = 1, theread cycle is extended. (M)STRB, (X)R/W, and (X)A are also extended onecycle. The next time (X)RDY is sampled, it is o.Figure 7-6. Use of Wait States for Read for (M)STRB = 0H3XR/WIXA =x:\--~----~--~z==~:--I~_--a.:--:""'--"'----'--->CXD~~------~(~--_W_, r-ite-D-a~ta--~>---I I I~ __ ~: __ ~:~-JIXRDY 7 ~ \ : ~: L : : ~: L : :I I I~ Extra -JCycleII7-8External Bus Operation
External Interface Timing~;s:.:~!::;='."::O:;:';:;:;:;:;:;:;::S:;:">~':;="~:''':~==,'' .....:;.. y.;:;:;~::>.~;:>:;:".:::::;:;~:~:::::o:;:~:::;::::x;...::::: .';:;:;:;:;:;:>:"o!:::::'O;::::S:;::::',*::::="'('::~~~:::::::'«:;''';:-o!::::::;~:~'';fo!;:::::.'!:X::::::;::.':::::::::::::::~~::'~
External InterfaceFigure 7-9 illustrates a read with one wait state when IOSTRB is active, andFigure 7-10 illustrates a write with one wait state when IOSTRB is active. For. each wait state added, IOSTRB, XR/W, and XA are extended one clock cycle.Writes hold the data on the bus one additional cycle. The sampling of XRDYis repeated each cycle.Figure 7-9. Read With One Wait State for !OSTRB = 0H3H1,\'-------XR/W ~\'--_......: _____-I I IXA ==x-----.--:.------.-.:.-----:-X--:----IXD----~--------------------~: ~~--------------........ ---XRDY __ ~ __ ~~~7 \~.~:-~~;~/-__ --------I I Ib-- Extra -JCycle7-11
External InterfaceFigure 7-11 through Figure 7-21 illustrate the various transitions betweenmemory reads and writes, and I/O writes over the expansion bus.Figure 7-11. Memory Read and liD Write for Expansion BusH3J1\'\1I 1'\ I 1'\ ;-11Hi '\ /. '\ /. '\1/. '\ I1 1~MSTRB ~I10STRB\ IXRIW'\111: Memory Ad:dress~XA~1 1I 1110 A~dressXD< Re~d > :
External Interface Timing~.:;:>.o;.::~~:r.:;::~~:w,,::::~:;~:;:;y'o::s::--,,:::::o:;%::,:::::::;:::-,:;':O%,::>::::::-:::;:;:;:-~~::o;.::~;:.;::::s-::-..,::::~YO.:'.::::::~'::Y'hW.':::v..:'.::::::::~««~~~~::;.:;,;~::::~:::;·;::w .. ~,:::~::",,;ow,o;~««y~~·;o;o;.·x·;Y.O«s~ ...... ~ ...:»,;·;o;sm~o;::~~o;."..:-m::y:::~.. ~s:."""~?M~~..,; .. :::;,;~s::.m:v.oS$::'s:;:-"!'(.~::~::s::=:>wH,::::WS!Figure 7-13. Memory Write and 110 Write for Expansion BusH3H1MSTRB~I, '-------~-------' ,\,--_~lXRNJy--'\'" T--------~------------------~--------' , '---------------------------~--------# ,XA ______ ~---M-e-m-o~~-A-d-d-r-es-s~:------~~----~---I/O--A~~_d-re-s-s--~------~,XD----
External Interface Timing~»,;:,;:~y.~:;9.>:::~.:-~;:~;s:;.sSW4~;.~;,~:~;,;o;=:!O~y.:y.:Y,;:o:~:~~~~~m::>:.::o:.:,:sy-#..m:sy.~y.;s~~:~~:;:;%:~~~~~~~~y.:~:,:y.:y'::.::.:~::.: ..... ms:,:y';O~y.~~%:~.,Y.;~~:':~:"'h~::-~"';~;O;SS'£«~S~~:::O:;SFigure 7-14. Memory Write and liD Read for Expansion BusH3H1MSTRB~II '-------~-------' IXRAN ____ ~ ______ ~ ______ ~ __ __J~\'---_---1IXA ______ ~---M-e-m~~~rY-A-d-d-re-s-s~:----~~------~---I/O--A~~~d-re-s-s--~----~~IXD----
External Interface Timing::';:;:'"S:"..-;S:;9.;:O::!'i:>::~;:::::;:::;!-:;::;;:;:::.~:;::~:::::::"..~::::;:::;:::~:::::i:;:::;:'::;:;:::-~~:::!'-:::::-~:::-Y-:;:"":;:;::"~~::"'"?~':~::--..:::;!'.::-.::::::::::~:::::;:::i:;:::;:::::::::;:."!::;::;:::::;:~::!'«;:.~:;:::;:;O:?;::::::::::::O .."!::~:~::::::::!,'('(':i:;:;::('Z:;:;:::;"~:!'k"";-':::::!''';';:':~::::!'.(.'::::::'~!'~;·;S::':O;·:''::::·;:;:;-;,::y;:::;:::,::::~~:;,;::~~*;:;:;:;:;:o~::;:o:·~::;:;:::;%s::::.."O!:::::!,6*-;:~:::::;:;O;:~:;:;'::::::s.:~~o$S~:':~Figure 7-15. 110 Write and Memory Write for Expansion BusH3H1\----"1XA~ ______ ~ ___ I/O __ A~~_d_re_s_s __ ~ ______ ~ ______ ~_M_e_m_o_~~:_Ad_d_r_es_s __ ~ _____IXD ---ro----{ I/O Write Memory Write7-17
External Interface Timing;';=~;:';:;';O;:;:;O;:;:;:;:;:;~'::;:::;~::::-;:;:~::':--/.«~«:l(:::~..;:;::::::y':%:::::;:;%::~~.(...::::;:;:.::;c:%:;ss.:::;S:;:;:'$;~«'.:.~-::;-~~";:"~~~:;:;:::~W~;':'::::::;:;:::::::;:~~;:;:;S:::::;y'>!"~%:;O;:~~6::-;:;~::'~;~~);::W~:::~y..(
___________________External Interface Timing~~~::m,;S!Ii:~5$';''':;:;~W. ...;s:;-~~:~s.~»~'':;~';5»'?.:,;m~~;~~s.O;~:':S''';:;S~SY.«o"S::~~:':5Y»,;~,;,SS:OSS·~::;SSS:;'SY;:;';';'~;"5"~;":O::"::~;S.O;,;S:~;~';'».WY:*'''-';''~'''''':;-'5y.;so;S';::y"'S~SS~Y.>ssm~5:~m:oY~,;,;ss~s»'!:,;mss:;SY.O:O:O:O:i~XO'!:S';S:m5:;S';S~:Q!.Figure 7-17. liD Read and Memory Write for Expansion BusH3H1\"'__-:-__J1\ I-----~~--~~--~--~'1-------""1XRiW\~----------~~~~--- !XA ~ lID Address -J X'--__ 1 -..,-_M_e_m_O~rYr_A-d-d-r-es-s.,......--.,...---J~1 i1 ~~~~XD--~----~----~~Memory Write\;1 \;17-19
External Interface Timing~~ .. ~.y.;sw..e.Y.(~/.~~~o?"..:."!;(':':?'-~:09;:::"'(Q.;:;,::.:!o~~;:;:~;s..o>,.;Y"~:':9;~:~~~"%?;:,~.s:.'9lo~Qh~H.ow.~«;~~;~,,~«-'$!~~~w~~~~~;~~~~~::~::~.;,;mm~~s:>>>'!MSY.M~o;f~~~W~';'~«'.
External InterfaceFigure 7-21. liD Read and I/O Read for Expansion BusH3H1MSTRBJ'C1 1IOSTRB'\ I '\1-IXRiW1XA229
External InterfaceFigure 7-22. Inactive Bus States for IOSTRBFigure 7-22 and Figure 7-23 illustrate the signal states when a bus is inactive(after an IOSTRB or (M)STRB access, respectively). The strobes (STRB,MSTRB, IOSTRB) and (X)RIW) go to 1. The address is undefined, and theready signal (XROY or ROY) is ignored.H3H1IOSTRB ~ )(x)Riw(X)A(X)DWrite DataI>< IAddre~s undefin~d(X)RDY" / (Xl RD Y: Ig naredII~ Bus InactiveJ7-24 External Bus Operation
External InterfaceFigure 7-23. Inactive Bus States for STRB and MSTRBH3H1(M)STRB'\ I(X)RIW1I(X)AX: Address ~ndefined(X)D(X)RDY":LWrite Data(X)RDV:Ignored14 Bus Inactive J7-25
External Interface Timing:(~~~::-m.:e~-==::m:~::-»':::~!:'(o".Q.;~~::?,.Q.;w.:r.:;:::0:"«-:;~;:;:;:--:;:;:"».;?::;';(.:;::::9.:X%:::-'('('::!:?';:;::::::::~;:::"«-::Y.:o::~:;~m::-Q.:o!~~~:::;:;::s?"..v....."!"6:::"F.'(I.:~~:".(.::::::~:;:-~:w.~Q'/..(.:;::e;:::"F.Q.::"Q.'.(.:".(Q.:w.~;:::;o:f.:W':::;:"o!;w.:"@/.:"o':~&..(.O:::S·:Y.:o:~:;O;::?;:::;:~".:~;f.:::~~:;:::;:::".:~:;:-Q.::".r-Y.:::::::::::e:::::::?;::~w.~.. x.(.:::"«.:;:::::::;:w.;:;:;?;s:;::::Figure 7-24. HOLD and HOLDA TimingFigure 7-24 illustrates the timing for HOLD .and HOLDA. HOLD is an externalasynchronous input. There is a minimum of one cycle delay from the time whenthe processor recognizes HOLD = ° until HOLDA = 0. When HOLDA = 0, theaddress, data buses, and associated strobes are placed in a high-impedancestate. <strong>Al</strong>l accesses occurring over an interface are complete before a hold isacknowledged.H31 1H1 J. '\ 1 '\ I: '\ 1 \ 1 \...1 1HOLD\ 11HOLDA\71 1STRB~1R/WI~I11 -
Programmable Wait StatesWhen SWW = 00, ROYint is dependent only upon ROY. ROY wtcnt is ignored.The truth table for this mode is Table 7-3.Table 7-3. Wait-State Generation When SWW = 0 0RDY RDYwtcnt RDYint0 o . 00 1 01 0 11 1 1When SWW = 0 1, ROYint is dependent only upon RDY wtcnt. ROY is ignored.Table 7-4 is the truth table for this mode.Table 7-4. Wait-State Generation When SWW = a 1ROY RDYwtcnt ROYint0 0 00 1 11 0 01 1 1When SWW = 1 0, RDYint is the logical-OR (electrical-AND, since thesesignals are low true) of RDY and RDY wtcnt (see Table 7-5).Table 7-5. Wait-State Generation When SWW = 1 aRDY RDYwtcnt ROYint0 0 00 1 01 0 01 . 1 1When SWW = 1 1, ROYint is the logical-AND (electrical-OR, since thesesignals are low true) of RDY and ROYwtcnt. The truth·table for this mode isTable 7-6.Table 7-6. Wait-State Generation When SWW = 1 JROY RDYwtcnt ROYint0 0 00 1 11 0 11 1 17-28 External Bus Operation
Programmable Bank c:: .. ,.it,..h,i",.,7.4 Programmable Bank SwitchingFigure 7-25. BNKCMP ExampleProgrammable bank switching allows you to switch between external memorybanks without externally inserting wait states due to memories that require severalcycles to turn off. Bank switching is implemented on the primary bus andnot on the expansion bus.The size of a bank is determined by the number of bits specified to be examined.For example (see Figure 7-25), if BNKCMP =16, the 16 MSBs of theaddress are used to define a bank. Since addresses are 24 bits, the bank sizeis specified by the 8 LSBs, yielding a bank size of 256 words. If BNKCMP ~ 16,only the 16 MSBs are compared. Bank sizes from 2 8 = 256 to 224 = 16M areallowed. Table 7-7 summarizes the relationship between BNKCMP, the addressbits used to define a bank, and the resulting bank size.~I--------- 24-bit address ----------'~23 o~r------Number of bits to compare ---+- Defines bank size --tiTable 7-7. BNKCMP and Bank SizeBNKCMP MSBs Defining a Bank Bank Size (32-Bit Words)00000 None 224= 16M00001 23 223= 8M00010 23-22 . 222= 4M00011 23-21 221= 2M00100 23-20 220= 1 M00101 23-19 2 19 = 512K00110 23-18 2 18 = 256K00111 23-17 2 17 = 128K01000 23-16 2 16 = 64K01001 23-15 2 15 = 32K01010 23-14 2 14 = 16K01011 23-13 2 13 = 8K01100 23-22 212= 4K01101 23-11 211 = 2K01110 23-12 2 10 = 1 K01111 23-9 2 9 = 51210000 23-8 2 8 = 25610000 -11111 Reserved Undefined7-29
~ ______ p_e_ri_p_h_e_ra_l_s ________________________________________ ~II..:111111
Peripherals
Chapter 8Peri heralsThe TMS320C3x features two timers, two serial ports (one on theTMS320C31), and an on-chip Direct Memory Access (DMA) controller. Theseperipheral modules are controlled through memory-mapped registers locatedon the dedicated peripheral bus.The DMA controller is used to perform input/output operations without interferingwith the operation of the CPU. Therefore, it is possible to interface theTMS320C3x to slow external memories and peripherals (AIDs, serial ports,etc.) without reducing the computational throughput of the CPU. The result isimproved system performance and decreased system cost.Major topics discussed in this chapter on peripherals are listed below.Q Timers (Section 8.1 on page 8-2)• RegistersI!I Pulse generationEIOperation modes[J Serial Ports (Section 8.2 on page 8-12).. Registers.. Operation configurationsII Timing• Examples[J DMA Controller (Section 8.3 on page 8-38)• Registers• DMA memory transfer operation• Synchronization of DMA channels8-1
Timers8.1 TimersFigure 8-1. Timer Block DiagramThe TMS320C3x timer modules are general-purpose, 32-bit, timer/eventcounters, with two signaling modes and internal or external clocking (seeFigure 8-1). The timer modules can be used to signal to the TMS320C3x orthe external world at specified intervals, or to count external events. With aninternal clock, the timer can be used to signal an external A/D converter to starta conversion, or it can interrupt the TMS320C3x DMA controller to begin a datatransfer. The timer interrupt is one of the internal interrupts. With an externalclock, the timer can cou~t external events and interrupt the CPU after a specifiednumber of events. Available to each timer is an 110 pin that can be usedas an input clock to the timer, an output clock signal, or a general-purpose I/Opin.Period Register (31-0)Counter (32-bit)Counter Register(31-0)'f- External Clock\-INV32Comparator?Period = CounterPulse GeneratorINVTSTATTimer OutThree memory-mapped registers are used by each timer:[J Global-control register[J Period register[J Counter registerThe global-control register determines the operating mode of the timer,monitors the timer status, and controls the function of the I/O pin of the timer.8-2Peripherals
TimersFigure 8-2. Memory-Mapped Timer LocationsThe period register specifies the timer's signaling frequency. The counterregister contains the current value of the incrementing counter. The timer canbe incremented on the rising edge or the falling edge of the input clock. Thecounter is zeroed and can cause an internal interrupt whenever its value equalsthat in the period register. The pulse generator generates two types of externalclock signals: pulse or clock. The memory map for the timer modules is shownin Figure 8-2.RegisterPeripheral AddressTimer 0 Timer 1Timer Global Control (See Table 8-1) 808020h 808030hReserved 808021h 808031hReserved 808022h 808032hReserved 808023h 808033hTimer Counter (See subsection 8.1.2) 808024h 808034hReserved 808025h 808035hReserved 808026h 808036hReserved 808027h 808037hTimer Period (See subsection 8.1.2) 808028h 808038hReserved 808029h 808039hReserved 80802Ah 80803AhReserved 80802Bh 80803BhReserved 80802Ch 80803ChReserved 80802Dh 80803DhReserved 80802Eh 80803EhReserved 80802Fh 80803Fh8.1.1 Timer Global-Control RegisterThe timer global control register is a 32-bit register that contains the global andport control bits for the timer module. Table 8-1 defines the register bits,names, and functions. Bits 3 - 0 are the port control bits; bits 11 - 6 are thetimer global control bits. Figure 8-3 shows the 32-bit register. Note that at reset,all bits are set to 0 except for DATIN (set to the value read on TCLK).8-3
TimersFigure 8-3. Timer Global-Control Register31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16I xx I xx I xx I xx I xx xx xx xx xx xx I xx I xx I xx xx xx xx15 14 13 12 11 10 9 8 7 6 5 4 3 2 0I xx I xx I xx I xx I TSTAT I INV I CLKSRC I C/P HLD GO I xx I xx I DATIN DATOUT jlo FUNCR/W RIW RIW R/W R/W RIW R R/W R/W RIWNOTE: xx = reserved bit, read as O.R = read, W = write.Table 8-1. Timer Global-Control Register Bits SummaryBits Name Reset Value Function0 FUNC 0 FUNC controls the function of TCLK. If FUNC 0, TCLK is configuredas a general-purpose digital 1/0 port. If FUNC = 1, TCLK is configuredas a timer pin (see Figure 8-7 for a description of the relationshipbetween FUNC and CLKSRC).1 jlo 0 If FUNC = 0 and CLKSRC = 0, TCLK is configured as a general-purpose110 pin. In this sase, if jlo = 0, TCLK is configured as a generalpurposeinput pin. If 1/0 = 1 , TCLK is configured as a general-purposeoutput pin.2 DATOUT 0 DATOUT drives TCLK when the TMS320C3x is in 1/0 port mode.DATOUT can also be used as an input to the timer.3 DATIN xt Data input on TCLK or DATOUT. A write has no effect.5-4 Reserved 0-0 Read as O.6 GO 0 The GO bit resets and starts the timer counter. When GO = 1 and thetimer is not held, the counter is zeroed and begins incrementing on thenext rising edge of the timer input clock. The GO bit is cleared on thesame rising edge. GO = 0 has no effect on the timer.7 HLD 0 Counter hold signal. When this bit is zero, the counter is disabled andheld in its current state. If the timer is driving TCLK, the state of TCLKis also held. The internal divide-by-two counter is also held so that thecounter can continue where it left off when HLD is set to 1. The timerregisters can be read and modified while the timer·ig being held.RESET has priority over HLD. Table 8-2 shows the effect of writingto GO and HLD.8 C/P 0 Clock/Pulse mode control. When C/P = 1, clock mode is chosen, andthe signaling of the status f!?g and external output will have a 50percent duty cycle. When C/P = 0, the status flag and external outputwill be active for one H1 cycle during each timer period (seeFigure 8-4).9 CLKSRC 0 Specifies the source of the timer clock. When CLKSRC = 1, an internalclock with frequency equal to one-half the H1 frequency is used to incrementthe counter. The INV bit has no effect on the internal clocksource. When CLKSRC = 0, an external signal from the TCLK pin canbe used to increment the counter. The external clock is synchronizedinternally, thus allowing external asynchronous clock sources that donot exceed the specified maximum allowable external clock frequency.This will be less than f(H1 )/2. (See Figure 8-7 for a description ofthe relationship between FUNC and CLKSRC).t x = 0 or 18-4 Peripherals
TimersTable 8-1. Timer Global-Control Register Bits Summary (Continued)Bits101131'-12Name Reset Value FunctionINV 0 Inverter control bit. If an external clock source is used and INV = 1, theexternal clock is inverted as it goes into the counter. If the output of thepulse generator is routed to TCLK and INV = 1, the output is invertedbefore it goes to TCLK (see Figure 8-1). If INV = 0, no inversion isperformed on the input or output of the timer. The INV bit has no effect,regardless of its value, when TCLK is used in I/O port mode.TSTAT 0 This bit indicates the status of the timer. It tracks the output of theuninverted TCLK pin. This flag sets a CPU interrupt on a transition fromo to 1 . A write has no effect.Reserved 0-0 Read as O.Table 8-2 shows the result of a write using specified values of the GO and HLDbits in the global control register.Table 8-2. Result of a Write of Specified Values of GO and HLDGO HLD Result0 0 <strong>Al</strong>l timer operations are held. No reset is performed. (Reset value)0 1 Timer proceeds from state before write.1 0 <strong>Al</strong>l timer operations are held, including zeroing of the counter. The GO bitis not cleared until the timer is taken out of hold.1 1 Timer resets and starts.8-5
Timers8.1.2 Timer Period and Counter RegistersThe 32-bit timer period register is used to specify the frequency of the timer signaling.The timer counter register is a 32-bit register. which is reset to zerovvhenever it increments to the value of the period register. Both registers areset to 0 at reset.Certain boundary conditions affect timer operation, such as a zero in tHe periodregister and an overflow of the counter. These conditions are listed as follows:Q When the period and counter registers are zero, the operation of the timeris dependent upon the cif5 mode selected. In pulse mode (Cif5 = 0),TSTAT is set and remains set. In clock mode (Cif5 = 1), the width of thecycle is 2/f(H1), and the external clocks are ignored.QWhen the counter register is not 0 and the period register = 0, the counterwill count, roll over to 0, and then behave as described above.Q When the counter register is set to a value greater than the period register,the counter may overflow when being incremented. Once the counterreaches its maximum 32-bit value (OFFFFFFFFh), it simply clocks over too and continues.Writes from the peripheral bus override register updates from the counterand new status updates to the control register.8.1.3 Timer Pulse GenerationThe timer pulse generator (see Figure 8-1) can generate several different externalsignals. These signals may be inverted with the INV bit. The two basicmodes are pulse mode and clock mode, as shown in Figure 8-4. In bothmodes, an internal clock source has a frequency of f(H1 )/2, and an externalclock source has a maximum frequency of f(H1 )/2.6. Refer to timer timing inAppendix A. In pulse mode (Cip = 0), the width of the pulse is 1/f(H1).8-6Peripherals
TimersFigure 8-4. Timer Timing14 ~ 2/f(H1)---.j 14 11/f(H1)I I II I 1Jl n rr1.:1 1 1 1/f(CLKSRC) I14 III period register/f(CLKSRC)i i iTINT TINT TINT(a) TSTAT and Timer Output (INV = 0) When cip = 0 (Pulse Mode)14 ~ 1/f(CLKSRC)14 ~ I 2/f(H1 )I I I1 1 .1Jr1 1 1~ ~ period register/f(CLKSRC) III14 2 x period register/f(CLKSRC) IIIi i iTINT TINT TINT(b) TSTAT and Timer Output (INV = 0) When cip = 1 (Clock Mode)The rate of timer signaling is determined by the frequency of the timer inputclock and the period register. The following equations are valid with either aninternal or an external timer clock:f(pulse mode) = f(timer clock) / period registerf(clock mode) = f(timer clock) / (2 x period register)Figure 8-5 provides some examples of the TCLKx output when the period registeris set to various values and clock or pulse mode is selected.8-7
TimersFigure 8-5. Timer Output Generation Examples(a)INV = 0, cif.i = 0 (Pulse Mode)Timer Period = 1Hi -.!IO-~ --D*-~- 3HiII(b)INV = 0, C/P = 0 (Pulse Mode)Timer Period = 2H14 ~14- 4Hi -JiIJl n ___ ~n___~n__~r(c)INV = 0, C/P = 0 (Pulse Mode)Timer Period ::= 3I4l- 4Hi ~4 2Hira- I(d)INV = 0, C/P = 1 (Clock Mode)Timer Period = 0r.-- 4Hi ~14-8f;1i---~IJ I ~I----~ ____ ~(e)INV = 0, C/P = 1 (Clock Mode)Timer Period = 1~ 12Hi--~~1j.-6Hi~J _I__ ~II(f)INV = 0, cif.i = 1 (Clock Mode)Timer Period = 28-8Peripherals
Timers8.1.4 Timer Operation ModesThe timer can receive its input and send its output in several different modes,depending upon the setting of CLKSRC, FUNC, and 110. The four timer modesof operation are defined as follows:QIf CLKSRC = 1 and FUNC = 0, the timer input comes from the internalclock. The internal clock is not affected by the INV bit. In this mode, TCLKis connected to the I/O port control and can be used as a general-purposeI/O pin (see Figure 8-6). If 110= 0, TCLK is configured as a general-purposeinput pin whose state can be read in DATIN. DATOUT has no effecton TCLK or DATIN. If 110 = 1, TCLK is configured as a general-purposeoutput pin. DATOUT is placed on TCLK and can be read in DATIN.Figure 8-6. Timer 110 Port ConfigurationsInternalII ExternalIDATOUT (NC) ----0 rt-TCLKDATINTlo = a(a)IInternal___I ExternalIJATOUT --tII.~ !-I."--r-1-DATINTlo = 1(b)TCLKQQQIf CLKSRC = 1 and FUNC = 1, the timer input comes from the internalclock, and the timer output goes to TCLK. This value may be inverted usingINV, and the value output on TCLK can be read in DATIN.If CLKSRC = ° and FUNC = 0, the timer is driven according to the statusof the Tlo bit. If Tlo = 0, the timer input comes from TCLK. This value canbe inverted using INV, and the value of TCLK can be read in DATIN. If I/O= 1, TCLK is an output pin. Then, TCLK and the timer are both driven byDATOUT. <strong>Al</strong>l O-to-1 transitions of DATOUT increment the counter. INV hasno effect on DATOUT. The value of DATOUT can be read in DATIN.If CLKSRC = ° and FUNC = 1, TCLK drives the timer. If INV = 0, all O-to-1transitions of TCLK increment the counter. If INV = 1, aIl1-to-0 transitionsof TCLK increment the counter. The value of TCLK can be read in DATIN.8-9
TimersFigure 8-7 shows the four timer modes of operation.Figure 8-7. Timer Modes as Defined by CLKSRC and FUNCTimerInternal I ExternalIII TClKIITimer...... ~--= .....TSTATInternal ExternalIIf--ilI"--"4Ir-__ ,-1-I> TClKDATINClKSRC = 1 (Internal)FUNC = 0 (I/O Pin)(a)ClKSRC = 1 (Internal)FUNC = 1 (Timer Pin)(b)TimerInternal I External_-o---cl---;.:____ TClKITimerInternal I External~---o-----+-: ~ TClKITSTATTSTATDATINClKSRO = 0 (External)FUNC = 0 (I/O Pin)(c)ClKSRC = 0 (External)FUNC = 1 (Timer Pin)(d)8.1.5 Timer InterruptsA timer interrupt is generated whenever the timer automatically resets the timercounter register to zero. The timer counter register is automatically reset tozero whenever it is equal to or greaterthan the value in the timer period register.The timer interrupt can be used to interrupt either the CPU or the DMA. Interruptenable control for each timer, for either the CPU or the DMA, is found inthe CPU/DMA interrupt enable register. Refer to subsection 3.1.8 for more informationon the CPU/DMA interrupt enable register.When a timer interrupt occurs, a change in state of the corresponding TCLKpin will be observed if the FUNC = 1 and CLKSRC = 1 inthetimerglobal-controlregister. The exact change of state depends on the state of the ciP" bit.8-10Peripherals
Timers8.1.6 Timer Initialization/ReconfigurationThe timers are controlled through memory-mapped registers located on thededicated peripheral bus. A general procedure for initializing and/or reconfiguringthe timers follows:1) Halt the timer by clearing the GO/HLD bits ofthe timer global-control register.This can be accomplished by writing a 0 to the timer global-control register.Note that the timers are halted on RESET.2) Configure the timer via the timer global-control register (with GO = HLD= 0 ), as well as the timer counter register and timer period register, if nec·essary.3) Start the timer by setting the GO/HLD bits of the timer global-control register.8-11
Serial Ports8.2 Serial PortsThe TMS320C30 has two totally independent bidirectional serial ports. Bothserial ports are identical with a complementary set of control registers in eachone. Only one serial port is available on the TMS320C31. Each serial port canbe configured to transfer 8, 16, 24, or 32 bits of data per word simultaneouslyin both directions. The clock for each serial port can originate either internally,via the serial port timer and period registers, or externally, via a supplied clock.An internally generated clock is a divide-down of the clockout frequency, f(H1).A continuous transfer mode is available, which allows the serial port to transmitand receive any number of words without new synchronization pulses.Eight memory-mapped registers are provided for each serial port:QGlobal-control registerQ Two control registers for the six serial 110 pinsQThree receive/transmit timer registersQ Data-transmit registerQData-receive registerThe global-control register controls the global functions of the serial port anddetermines the serial-port operating mode. Two port control registers controlthe functions of the six serial port pins. The transmit buffer contains the nextcomplete word to be transmitted. The receive buffer contains the last completeword received. Three additional registers are associated with the transmit/receivesections of the serial-port timer. A serial-port block diagram is shown inFigure 8-8, and the memory map of a serial port is shown in Figure 8-9.8-12Peripherals
Serial PortsFigure 8-8. Serial-Port Block DiagramrReceive Section -, r-Transmit Section ---,~--------~ CLKR CLKXReceiveTimer (16)TSTAT CLKR TSTAT TransmitTimer (16)RINTXINTROR ORRSR(32)ORR(32)LoadXSR. (32)OXR(32)OXOX~DX8-13
Serial PortsFigure 8-9. Memory-Mapped Locations for the Serial PortRegisterPeripheral AddressSerialSerialPort 0Port 1tSerial-Port Global Control (See Table 8-3) 808040h 808050hReserved 808041h 808051hFSX/OX/CLKX Port Control (See Table 8-4) 808042h 808052hFSR/OR/CLKR Port Control (See Table 8-5) 808043h 808053hR/X Timer Control (See Table 8-6) 808044h 808054hR/X Timer Counter (See Figure 8-13) 808045h 808055hR/X Timer Period (See Figure 8-14) 808046h 808056hReserved 808047h 808057hData Transmit (See Figure 8-15) 808048h 808058hReserved 808049h 808059hReserved 80804Ah 80805AhReserved 80804Bh 80805BhData Receive (See Figure 8-16) 80804Ch 80805ChReserved 808040h 80805DhReserved 80804Eh 80805EhReserved 80804Fh 80805Fht Reserved locations on the TMS320C318.2.1 Serial-Port Global-Control RegisterThe serial-port global-control register is a 32-bit register that contains the globalcontrol bits for the serial port. Table 8-3 defines the register bits, bit names,and bit functions. The register is shown in Figure 8-10.8-14Peripherals
Serial PortsFigure 8-10. Serial-Port Global-Control Register31 30 29 28 27 26 25 24 23 22 21 20 19 18RIW R!W R!W RlW R/W RlW R!W RlW RlWXLENR!W R!W R!W R!W RNI R!W R!W R!W RIW RNI RlW R R R!W R RNOTE: xx = Reserved bit, read as O.R = read, W = write.Table 8-3. Serial-Port Global-Control Register Bits SummaryBit Name Reset Value Function0 RROY 0 If RROY = 1, the receive buffer has new data and is ready to be read. A three H1/H3cycle delay occurs from the reading of ORR to RROY = 1. The rising edge of this signalsets RINT. If RROY= 0 at reset, the receive buffer does not have new data sincethe last read. RROY = 0 at reset and after the receive buffer is read.1 XROY 1 If XROY = 1, the transmit buffer has written the last bit of data to the shifter and isready for a new word. A three H 1 IH3 cycle delay occurs from the loading of the transmitshifter until XROY is setto 1. The rising edge ofthis signal sets XINT. If XROY = 0,the transmit buffer has not written the last bit of data to the transmit shifter and is notready for a new word. XROY = 1 at reset.2 FSXOUT 0 This bit configures the FSX pin as an input (FSXOUT = 0) or an output (FSXOUT = 1).3 XSREMPTY 0 If XSREMPTY = 0, the transmit shift register is empty. If XSREMPTY = 1 , the transmitshift register is not empty. Reset or XRESET causes this bit to = O.4 RSRFULL 0 If RSRFULL = 1, an overrun of the receiver has occurred. In continuous mode,RSRFULL is set to 1 when both RSR and ORR are full. In noncontinuous mode,RSRFULL is set to 1 when RSR and ORR are full and a new FSR is received. A readcauses this bit to be set to O. This bit can be set to 0 only by a system reset, a serialport receive reset (RRESET = 1), or a read. When the receiver tries to set RSRFULLto a 1 at the same time that the global register is read, the receiver will dominate andRSRFULL is set to 1. If RSRFULL = 0, no overrun of the receiver has occurred.5 HS 0 If HS = 1, the handshake mode is enabled. If HS = 0, the handshake mode is disabled.6 XCLKSRCE 0 If XCLKSRCE = 1 , the internal transmit clock is used. If XCLKSRCE = 0, the externaltransmit clock is used.7 RCLKSRCE 0 If RCLKSRCE = 1 , the internal receive clock is used. If RCLKSRCE = 0, the externalreceive clock is used.8 XVAREN 0 This bit specifies fixed (XVAREN = 0) or variable (XVAREN = 1) data rate signalingwhen transmitting. With a fixed data rate, FSX is active for at least one XCLK cycleand then goes inactive before transmission begins. With variable data rate, FSX isactive while all bits are being transmitted. When you use an external FSX and variabledata rate signaling, the OX pin is driven by the transmitter when FSX is held activeor when a word is being shifted out.9 RVAREN 0 This bit specifies fixed (RVAREN = 0) or variable (RVAREN = 1) data rate signalingwhen receiving. With a fixed data rate, FSR is active for at least one RCLK cycle andthen goes inactive before the reception begins. With variable data rate, FSR is activewhile all bits are being received.8-15
Serial PortsTable 8-3.Serial-Port Global-Control Register Bits Summary (Continued)Bit Name Reset Value Function10 XFSM 0 Transmit frame sync mode. Configures the port for continuous mode operation(XFSM= 1) or standard mode (XFSM = 0). In continuous mode, only the first wordof a block generates a sync pulse, and the rest are simply transmitted continuouslyto the end of the block. In standard mode, each word has an associated sync pulse.11 RFSM 0 Receive frame sync mode. Configures the port for continuous mode (RFSM =1) orstandard mode (RFSM = 0) operation. In continuous mode, only the first word of ablock generates a sync pulse, and the rest are simply received continuously withoutexpectation of another sync pulse. In standard mode, each word received has anassociated sync pulse.12 CLKXP 0 CLKX polarity. If CLKXP = 0, CLKX is active high. If CLKXP = 1, CLKX is active low.13 CLKRP 0 CLKR polarity. If CLKRP = 0, CLKR is active high. If CLKRP =1, CLKR is active low.14 DXP 0 DX polarity. If OXP = 0, OX is active high. If OXP = 1, OX is active low.15 DRP 0 DR polarity. If DRP = 0, DR is active high. If DRP = 1, DR is active low.16 FSXP 0 FSX polarity. If FSXP = 0, FSX is active high. If FSXP = 1, FSX is active low.17 FSRP 0 FSR polarity. If FSRP = 0, FSR is active high. If FSRP = 1, FSR is active low.19 -18 XLEN 00 These two bits define the word length of serial data transmitted. <strong>Al</strong>l data is assumedto be right-justified in the transmit buffer when fewer than 32 bits are specified.o 0 --- 8 bits 1 0 --- 24 bitso 1 --- 16 bits 1 1 --- 32 bits21-20 RLEN 00 These two bits define the word length of serial data received. <strong>Al</strong>l data is right-justifiedin the receive buffer.o 0 --- 8 bits 1 0 --- 24 bitso 1 --- 16 bits 1 1 --- 32 bits22 XTINT 0 Transmit timer interrupt enable. If XTINT = 0, the transmit timer interrupt is disabled.If XTINT = 1, the transmit timer interrupt is enabled.23 XINT 0 Transmit interrupt enable. If XINT = 0, the transmit interrupt is disabled. If XINT = 1,the transmit interrupt is enabled. Note that the CPU transmit interrupt flag XINT isthe logical OR of the enabled transmit timer interrupt and the enabled transmit interrupt.24 RTINT 0 Receive timer interrupt enable. If RTINT = 0, the receive timer interrupt is disabled.If RTINT = 1, the receive timer interrupt is enabled.25 RINT 0 Receive interrupt enable. If RINT = 0, the receive interrupt is disabled. If RINT = 1,the receive interrupt is enabled. Note that the CPU receive interrupt flag RINT is theOR of the enabled receive timer interrupt and the enabled receive interrupt.26 XRESET 0 Transmit reset. If XRESET = 0, the transmit side of the serial port is reset. To takethe transmit side of the serial port out of reset, set XRESET to 1. However, do notset XRESET to 1 until at least three cycles after XRESET goes inactive. This appliesonly to system reset. Setting XRESET to 0 does not change the contents of any ofthe serial-port control registers. It places the transmitter in a state corresponding tothe beginning of a frame of data. Resetting the transmitter generates a transmit interrupt.Reset this bit during the time the mode of the transmitter is set. XFSM can betoggled without resetting the global-control register.8-16 Peripherals
Serial PortsTable 8-3.Serial-Port Global-Control Register Bits Summary (Concluded)Bit Name Reset Value Function27 RRESET 0 Receive reset. If RRESET = 0, the receive side of the serial port is reset. To takethe receive side of the serial port out of reset, set RRESET to 1. Setting RRESETto 0 does not change the contents of any of the serial-port control registers. It placesthe receiver in a state corresponding to the beginning of a frame of data. Reset thisbit at the same time the mode of the receiver is set. RFSM can be toggled withoutresetting the global-control register.31-28 Reserved 0-0 Read as O.8.2.2 FSX/OX/CLKX Port Control RegisterFigure 8-11. FSXIOXlCLKX Port Control RegisterThis 32-bit port control register controls the function of the serial port FSX, OX,and CLKX pins. At reset, all bits are set to O. Table 8-4 defines the register bits,bit names, and functions. Figure 8-11 shows this port control register.31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16xx xx xx xx xx xx xx xx xx xx xx I xx xx xx xx xx15 14 13 12 11 10 9 8 7 5 3 2NOTE: xx = reserved bit, read as O.R = read, W = write.R RIW RlW RIW R R/W RIW R/W R RIW RIW RIWTable 8-4.FSXIOXlCLKX Port Control Register Bits SummaryBit Name Reset Value Function0 CLKXFUNC 0 CLKXFUNC controls the function of CLKX. If CLKXFUNC = 0, CLKX is configuredas a general-purpose digital 110 port. If CLKXFUNC = 1, CLKX is a serialport pin.1 CLKXIIO 0 If CLKX I/O = 0, CLKX is configured as a general-purpose input pin. If CLKX1/0 = 1, CLKX is configured as a general-purpose output pin.2 CLKXDATOUT 0 Data output on CLKX.3 CLKXDATIN x Data input on CLKX. A write has no effect.4 DXFUNC 0 DXFUNC controls the function of DX. If DXFUNC = 0, DX is configured as ageneral-purpose digital I/O port. If DXFUNC = 1, DX is a serial port pin.5 DX T/o 0 If DX I/O = 0, DX is configured as a general-purpose input pin. If DX T/o = 1,DX is configured as a general-purpose output pin.6 DXDATOUT 0 Data output on DX.7 DXDATIN xt Data input on DX. A write has no effect.8 FSXFUNC 0 FSXFUNC controls the function of FSX. If FSXFUNC = 0, FSX is configuredas a general-purpose digital 1/0 port. If FSXFUNC = 1, FSX is a serial port pin.t x = 0 or 18-17
Serial PorisTable 8-4. FSXJOXlCLKX Port Control Register Bits Summary (Continued)Reset Value. Bit Name Functiont x = 0 or 10 9 FSX ilo If FSX]/O = 0, FSX is configured as a general-purpose input pin.If FSX 1/0 = 1, FSX is configured as a general-purpose output pin.0 10 FSXDATOUT Data output on FSX.xt 11 FSXDATIN Data input on FSX. A write has no effect.0-0 31-12 Reserved Read as O.8.2.3 FSR/DR/CLKR Port Control RegisterFigure 8-12. FSRIORlCLKR Port Control RegisterThis 32-bit port control register is controlled by the function of the serial portFSR, DR, and CLKR pins. At reset, all bits are set to O. Table 8-5 defines theregister bits, the bit names, and functions. Figure 8-12 illustrates this port controlregister.31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx15 14 12 11 7 6 5 4 3 2 0NOTE: xx = reserved bit, read as O.R = read, W = write.R R/W R/W R/W R R/W RNY R/W R R/W R/W RNITable 8-5. FSRIORICLKR Port Control Register Bits SummaryBit Name Reset Value Function0 CLKRFUNC 0 CLKRFUNC controls the function of CLKR. If CLKRFUNC = 0, CLKR isconfigured as a general-purpose digital 1/0 port. If CLKRFUNC = 1,CLKR is a serial port pin.1 CLKRilo 0 If CLKRYO = 0, CLKR is configured as a general-purpose input pin.If CLKRI/O = 1, CLKR is configured as a general-purpose output pin.2 CLKRDATOUT 0 Data output on CLKR.3 CLKRDATIN x Data input on CLKR. A write has no effect.4 DRFUNC 0 DRFUNC controls the function of DR. If DRFUNC = 0, DR is configuredas a general-purpose digital 1/0 port. If DRFUNC = 1 , DR is a serial portpin.S DR.l/O 0 If DRI/O = 0, DR is configured as a general-purpose input pin.If DRIIO = 1, DR is configured as a general-purpose output pin.6 DRDATOUT 0 Data output on DR.7 DRDATIN xt Data input on DR. A write has no effect.S FSRFUNC 0 FSRFUNC controls the function of FSR. If FSRFUNC = 0, FSR is configuredas a general-purpose digital 1/0 port. If FSRFUNC = 1, FSR is aserial port pin.t x = 0 or 18-18 Peripherals
Serial PortsTable 8-5. FSRIDRICLKR Port Control Register Bits Summary (Continued)Bit Name Reset Value Function9 FSR Tlo 0 If FSR ]10 = 0, FSR is configured as a general-purpose input pin.If FSR 1/0 = 1, FSR is configured as a general-purpose output pin.10 FSRDATOUT 0 Data output on FSR.11 FSRDATIN x Data input on FSR. A write has no effect.31-12 ReseNed 0-0 Read as O.8.2.4 Receive/Transmit Timer Control RegisterA 32-bit receive/transmit timer control register contains the control bits for thetimer module. At reset, all bits are set to O. Table 8-6 lists the register bits, bitnames,andfunctions. Bits5 - Ocontrol the transmitter timer. Bits 11 - 6controlthe receiver timer. Figure 8-13 shows the register. The serial port receive/transmit timer function is similar to timer module operation. It can be consideredas a 16-bit-wide timer. Referto Section 8.1 for more information on timers.Figure 8-13. ReceivelTransmit Timer Control Register31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16I xx I xx I I xx I xx xx xx xx xx xx xx I xx xx xx xx xx15 14 13 12 11 10 9 8 7 6 5 4 3 2 0NOTE: xx = reseNed bit, read as O., R = read, W = write.R AMI AMI R AMI RlW R RlW RtN AMITable 8-6. ReceivelTransmit Timer Control RegisterBit Name Reset Value Function0 XGO 0 The XGO bit resets and starts the transmit timer counter. When XGOis set to 1 and the timer is not held, the counter is zeroed and beginsincrementing on the next rising edge of the timer input clock. The XGObit is cleared on the same rising edge. Writing 0 to XGO has no effecton the transmit timer.1 XHLD 0 Transmit counter hold signal. When this bit is set to 0, the counter is disabledand held in its current state. The internal divide-by-two counteris also held so that the counter will continue where it left off when XHLDis set to 1. The timer registers may be read and modified while the timeris being held. RESET has priority over XHLD., 2 XC/P 0 XClocklPulse mode control. When XC/P = 1, theclockmodeis chosen.The signaling of the ~atus flag and external output has a 50-percentduty cycle. When XC/P = 0, the status flag and external output are activefor one CLKOUT'Cycle during each timer period.8-19
Serial PortsTable 8-6. Receive/Transmit Timer Control Register (Concluded)Bit Name Reset Value Function3 XCLKSRC 0 This bit specifies the source of the transmit timer clock. WhenXCLKSRC = 1, an internal clock with frequency equal to one-half theCLKOUTfrequency is used to increment the counter. When XCLKSRC= 0, an external signal from the CLKX pin can be used to increment thecounter. The external clock source is SYNChronized internally, thus allowingfor external aSYNChronous clock sources that do not exceedthe specified maximum allowable external clock frequency, i.e., lessthan f(H1 )/2.6.4 Reserved 0 Read as zero.5 XTSTAT 0 This bit indicates the status of the transmit timer. It tracks what wouldbe the output ofthe uninverted CLKX pin. This flag sets a CPU interrupton a transition from 0 to 1. A write has no effect.6 RGO 0 The RGO bit resets and starts the receive timer counter. When RGOis set to 1 and the timer is not held, the counter is zeroed and beginsincrementing on the next rising edge of the timer input clock. The RGObit is cleared on the same rising edge. Writing 0 to RGO has no effecton the receive timer.7 RHLD 0 Receive counter hold signal. When this bit is set to 0, the counter is disabledand held in its current state. The internal divide-by-two counteris also held so that the counter will continue where it left off when RHLDis set to 1. The timer registers may be read and modified while the timeris being held. RESET has priority over RHLD.8 RC/P 0 RClocklPulse mode control. When RC/P = 1 , the clock mode is chosen.The signaling of the slatus flag and external output has a 50-percentduty cycle. When RC/P = 0, the status flag and external output are activetorone CLKOUT cycle during each timer period.9 RCLKSRC 0 This bit specifies the source of the receive timer clock. When RCLKSRC= 1 , an internal clock with frequency equal to one-half the CLKOUT frequencyis used to increment the counter. When RCLKSRC = 0, an externalsignal from the CLKR pin can be used to increment the counter.The external clock source is SYNChronized internally, thus allowing forexternal aSYNChronous clock sources that do not exceed the specifiedmaximum allowable external clock frequency, i.e., less than f(H1 )/2.6.10 Reserved 0 Read as.zero.11 RTSTAT 0 This bit indicates the status of the receive timer. It tracks what would bethe output of the uninverted CLKR pin. This flag sets a CPU interrupton a transition from 0 to 1. A write has no effect.31-12 Reserved 0-0 Read as O.8-20 Peripherals
Serial Ports8.2.5 Receive/Transmit Timer Counter RegisterThe receive/transmit timer counter register. is a 32-bit register (seeFigure 8-14). Bits 15 - a are the transmittimercounter, and bits31 - 16arethe receive timer counter. Each counter is set to a whenever it increments tothe value of the period register (Section 8.2.6). It is also set to a at reset.Figure 8-14. ReceivelTransmit Timer Counter RegisterReceive Counter1615 oNOTE: <strong>Al</strong>l bits are read/write.Transmit Counter8.2.6 Receive/Transmit Timer Period RegisterThe receive/transmit timer period register is a 32-bit register (seeFigure 8-15). Bits 15 - a are the timer transmit period, and bits 31 - 16 arethe receive period. Each register is used to specify the period of the timer. Itis also set to a at reset.Figure 8-15. ReceivelTransmit Timer Period Register31Receive Period1615Transmit PeriodoNOTE: <strong>Al</strong>l bits are read/write.8.2. 7 Data-Transmit RegisterWhen the data-transmit register (DXR) is loaded, the transmitter loads theword into the transmit shift register (XSR), and the bits are shifted out. Thedelay from a write to DXR until an FSX occurs (orcan be accepted) is two CLKXcycles. The word is not loaded into the shift register until the shifter is empty.When DXR is loaded into XSR, the XRDY bit is set, specifying that the bufferis available to receive the next word. Four tap points within the transmit shiftregister are used to transmit the word. These tap points correspond to the fourdata word sizes and are illustrated in Figure 8-16 . The shift is a left-shift (LSBto MSB) with the data shifted out of the MSB corresponding to the appropriatetap point.8-21
Serial PortsFigure 8-16. Transmit Buffer Shift Operationf- Shift Direction f-3124 2316 15a 7oII32-bitword tap24-bitword tap16-bitword tapa-bitword tap8.2.8 Data-Receive RegisterWhen serial data is input, the receiver shifts the bits into the receive shift register(RSR). When the specified number of bits are shifted in, the data-receiveregister (ORR) is loaded from RSR, and the RROY status bit is set. The receiveris double-buffered. If the ORR has not been read and the RSR is full, the receiveris frozen. New data coming into the OR pin is ignored. The receive shifterwill not write over the ORR. The ORR must be read to allow new data in theRSR to be transferred to the ORR. When a write to ORR occurs at the sametime that a RSR to ORR transfer takes place, the RSR to ORR transfer haspriority.Data is shifted to the left (LSB to MSB). Figure 8-17 illustrates what happenswhen words less than 32 bits are shifted into the serial port. In this figure, it isassumed that an 8-bit word is being received and that the upper three bytesof the receive buffer are originally undefined. In the first portion of the figure,byte a has been shifted in. When byte b is shifted in, byte a is shifted to the left.When the data receive register is read, both bytes a and b are read.Figure 8-17.Receive Buffer Shift Operationf- Shift Direction f-After Byte a31 24 23 16 15 a 7 0IXIXIXIaIAfter Byte bIXIXIaIbI8-22Peripherals
Serial Ports8.2.9 Serial-Port Operation ConfigurationsFigure 8-18. Serial-Port Clocking in liD ModeSeveral configurations are provided for the operation of the serial port clocksand timer. The clocks for each serial port can originate either internally or externally.Figure 8-18 shows serial port clocking in the I/O mode (FUNC = 0) whenCLKX is either an input or an output. Figure 8-19 shows clocking in the serialportmode (FUNC = 1). Both figures use a transmit section for an example. Thesame relationship holds for a receive section.Internal I ExternalTSTATInternal Iinmer in \-.- Clock :.DATOU;SR : ~ I IDATINFUNC = 0 (1/0 Mode)ClKXI/O = 1 (ClKX, an Output)XClKSRC = 1 (Internal ClK for Timer)(a)DATAOUT--I~---'DATIN -.a-----'FUNC = 0 (110 Mode)Internal I ExternalClKXI/O = 1 (ClKX, an Output)XClKSRC = 0 (External ClK for Timer)(b)IITS~Internal I External. L._lnternal I---: Timer In r---- Clock II XSR I.. T : .. ClKXDATOUT (NC) --0 +DATIN --.4----'-FUNC = 0 (1/0 Mode)ClKXI/O = 0 (ClKX, an Input)XClKSRC = 1 (Internal ClK for Timer)(c)DATOUT (NC)--oDATIN --4-----'Internal I ExternalII..... ...--r4- ClKXFUNC = 0 (1/0 Mode)ClKXI/O = 0 (ClKX, an Input)XClKSRC = 0 (External ClK for Timer)(d)8-23
k.Serial PortsFigure 8-19. Serial-Port Clocking in Serial-Port ModeInternal I ExternalInterna\ ExternalInternal I Internal IClock I ~ Clock I~ I'L-./P'" ClKX ~tjt XSRI ClKXDATOUT (NC) -0 INV DATOUT (NC) -0DATIN --4-----1 DATIN INVFUNC = 1 (Serial-Port Mode)XClKSRCE= 1 (Output Serial-Port ClK)XClKSRC = 0 or 1(a)FUNC = 1 (Serial-Port Mode)XClKSRCE= 0 (Input Serial-Port ClK)XClKSRC = 1 (Internal ClK for Timer)(b)Internal I ExternalIIItjtClKXINVFUNC = 1 (Serial-Port Mode)XClKSRCE= 0 (Input Serial-Port ClK)XClKSRC = 0 (External ClK for Timer)(c)8.2.10 Serial-PortTimingThe formula for calculating the frequency of the serial-port clock with an inter. nally generated clock is dependent upon the operation mode of the serial-porttimers, defined asf (pulse mode) = f (timer c1ock)/period registerf (clock mode) = f (timer clock)/(2 x period register)An externally generated serial-port clock (CLKX or CLKR) has a maximum frequencyof less than f(H1 )/2.6. See serial port timing in Chapter 13. <strong>Al</strong>so, seesubsection 8.1.3 for information on timer pulse/clock generation.Transmit data is clocked out on the rising edge of the selected serial-port clock.Receive data is latched into the receive shift register on the falling edge of theserial-port clock. <strong>Al</strong>l data is transmitted and loaded MSB first and right-justified.If fewer than 32 bits are transferred, the data are right-justified in the 32-bittransmit and receive buffers. Therefore, the LSBs of the transmit buffer arethe bits that are transmitted.8-24Peripherals
Serial PortsThe transmit ready (XRDY) signal specifies that the data-transmit register(DXR) is available to be loaded with new data. XRDY goes active as soon asthe data is loaded into the transmit shift register (XSR). The last word may stillbe shifting out when XRDY goes active. If DXR is loaded before the last wordhas completed transmission, the data bits transmitted will be consecutive; i.e.,the LSB of the first word immediately precedes the MSB of the second, withall signaling valid as in two separate transmits. XRDY goes inactive when DXRis loaded and remains inactive until the data is loaded into the shifter.The receive ready (RRDY) signal is active as long as a new word.of data isloaded into the data receive register and has not been read. As soon as thedata is read, the RRDY bit is turned off.When FSX is specified as an output, the activity of the signal is determinedsolely by the internal state of the serial port. If a fixed data rate is specified, FSXgoes active when DXR is loaded into XSR to be transmitted out. One serialclockcycle later, FSX turns inactive, and data transmission begins. If a variabledata rate is specified, the FSX pin is activated when the data transmission begins,and remains active during the entire transmission of the word. Again, thedata is transmitted one clock cycle after it is loaded into the data transmit register.An input FSX in the fixed data rate mode should go active for at least one serialclock cycle and then inactive to initiate the data transfer. The transmitter thensends the number of bits specified by the LEN bits. In the variable data-ratemode, the transmitter begins sending from the time FSX goes active until thenumber of specified bits has been shifted out. In the variable data-rate mode,when the FSX status changes prior to all the data bits being shifted out, thetransmission completes, and the DX pin is placed in a high-impedance state.An FSR input is exactly complementary to the FSX.When using an external FSX, if DXR and XSR are empty, a write to DXR resultsin a DXR-to-XSR transfer. This data is held in the XSR until an FSX occurs.When the external FSX is received, the XSR begins shifting the data. If XSRis waiting for the externarFSX, a write to DXR will change DXR, but a DXR-toXSR transfer will not occur. XSR begins shifting when the external FSX is received,or when it is reset using XRESET.Continuous Transmit and Receive ModesWhen continuous mode is chosen, consecutive writes do not generate or expectnew sync pulse signaling. Only the first word of a block begins with an activesynchronization. Thereafter, data continues to be transmitted as long asnew data is loaded into DXR before the last word has been transmitted. Assoon as TXRDY is active and all of the data has been transmitted out of theshift register, the DX pin is placed in a high-impedance state, and a subsequentwrite to DXR initiates a new block and a new FSX.Similarly with FSR, the receiver continues shifting in new data and loadingORR. If the data-receive buffer is not read before the next word is shifted in,8-25
Serial Portssubsequent incoming data will be lost. The RFSM bit can be used to terminatethe receive-continuous mode.Handshake ModeThe handshake mode (HS = 1) allows for direct connection between processors.In this mode, all data words are transmitted with a leading 1 (seeFigure 8-20). For example, if an 8-bit word is to be transmitted, the first bit sentis a 1, folloWed by the 8-bit data word.In this mode, once the serial port transmits a word, it will not transmit anotherword until it receives a separately transmitted zero bit. Therefore, the 1 bit thatprecedes every data word is, in effect, a request bit.Figure 8-20. Data Word Format in Handshake ModeDX1
Serial PortsFigure 8-22. Direct Connection Using Handshake ModeTMS320C3x #1CLKXFSXOXCLKR ~FSRDRTMS320C3x #2.. CLKR... FSR.. DRCLKXFSXDX8.2.11 Serial-Port Interrupt Sources. A serial port has four interrupt sources:1) The transmit timer interrupt: The rising edge of XTSTAT causes a singlecycleinterrupt pulse to occur. When XTINT is 0, this interrupt pulse is disabled.2) The receive timer interrupt: The rising edge of RTSTAT causes a singlecycleinterrupt pulse to occur. When RTINT is 0, this interrupt pulse is disabled.3) The transmitter interrupt: Occurs immediately following a DXR-to-XSRtransfer. The transmitter interrupt is a single-cycle pulse. When theserial-port global-control register bit XINT is 0, this interrupt pulse is disabled.4) The receiver interrupt: Occurs immediately following a RSR to DRR transfer.The receiver interrupt is a single-cycle pulse. When the serial-port global-controlregister bit RINT is 0, this interrupt pulse is disabled.The transmit timer interrupt pulse is ORed with the transmitter interrupt pulse to createthe CPU transmit interrupt flag XINT. The receive timer interrupt pulse is ORed with thereceiver interrupt pulse to create the CPU receive interrupt flag RINT.8-27
Serial Ports8.2.12 Serial-Port Functional OperationThe following paragraphs and figures illustrate the functional timing of the variousserial-port modes of operation. The timing descriptions are presented withthe assumption that all signal polarities are configured to be positive, i.e.,CLKXP = CLKRP = OXP = ORP = FSXP = FSRP = O. Logical timing, in situationswhere one or more of these polarities are inverted, is the same exceptwith respect to the opposite polarity reference points, i.e. rising vs. fallingedges, etc.These discussions pertain to the numerous operating modes and configurationsof the serial-port logic. When it is necessary to switch operating modesor change configurations of the serial port, do this only when XRESET orRRESET are asserted (low), as appropriate. Therefore, when transmit configurationsare modified, XRESET should be low, and when receive configurationsare modified, RRESET should be low. When you use handshake mode,however, since the transmitter and receiver are interrelated, you should makeany configuration changes with XRESET and RRESET both low.<strong>Al</strong>l of the serial-port operating configurations can be broadly classified in twocategories: fixed data-rate timing and variable data-rate timing. The followingparagraphs discuss fixed and variable data-rate operation and all of their variations.Fixed Data-Rate Timing OperationFixed data-rate serial-port transfers can occur in two varieties: burst mode andcontinuous mode. In burst mode operation, transfers of single words are separatedby periods of inactivity on the serial port. In continuous mode, there areno gaps between successive word transfers; the first bit of a new word is transferredon the next CLKX/R pulse following the last bit of the previous word. Thisoccurs continuously until the process is terminated. .In burst mode with fixed data-rate timing, FSX/FSR pulses initiate transfers,and each transfer involves a single word. With an internally generated FSX(see Figure 8-23), transmission is initiated by loading OXR. In this mode, thereis a delay of approximately 2.5 CLKX cycles (depending on CLKX and H1 frequencies)from the time OXR is loaded until FSX occurs. With an external FSX,the FSX pulse initiates the transfer, and the 2.5-cycle delay effectively becomesa setup requirement for loading OXR with respect to FSX. Therefore,in this case, OXR must be loaded no later than 3 CLKX cycles before FSX occurs.Once the XSR is loaded from the OXR, an XINT is generated.8-28Peripherals
Serial PortsFigure 8-23. Fixed Burst ModeCLKX/RFSR/FSX (External) _________ _----------------DX/DR ----------------< A1 >C "--!.A~NU--------FSX (Internal)DXR Loaded XINT RINTIn receive operations, once a transfer is initiated, FSR is ignored until the lastbit. For burst mode transfers, FSR must be low during the last bit, or anothertransfer will be initiated. After a full word has been received and transferred tothe ORR, an RINT is generated.In fixed data rate mode, continuous transfers may be performed even ifR/XFSM = 0, as long as properly timed frame synchronization is provided, orif DXR is reloaded each cycle with an internally generated FSX (seeFigure 8-24).Figure 8-24. Fixed Continuous Mode With Frame SyncCLKX/RFSX (Internal) ________FSR/FSX (External) r,r----J r,r--JDR/DX ____________ ~~~r i ~:~i 1 ~1iDXR LoadedXINTDXR LoadedLoad D-XRRead DRRLoad DXRRead DRRFor receive operations and with externally generated FSX, once transfers havebegun, frame sync pulses are required only during the last bit transferred toinitiate another contiguous transfer. Otherwise, frame sync inputs are ignored.Therefore, continuous transfers will occur if frame sync is held high. With aninternally generated FSX, there is a delay of approximately 2.5 CLKX cyclesfrom the time DXR is loaded until FSX occurs. This delay occurs each timeDXR is loaded; therefore, during continuous transmission, the instruction that8-29
Serial Portsloads OXR must be executed by the N-3 bit for an N-bit transmission. Sincedelays due to pipelining may vary, a conservative margin of safety should beincorporated in allowing for this delay.Once the process begins, an XINT and an RINTare generated atthe beginningof each transfer. The XINT indicates that the XSR has been loaded from OXRand can be used to cause OXR to be reloaded. To maintain continuous transmissionin this mode, especially with an internally generated FSX, OXR mustbe reloaded early in the ongoing transfer.TheRINT indicates that a full word has been received and transferred into theORR. RINT is therefore commonly used to indicate an appropriate time to readORR.Continuous transfers are terminated by discontinuing frame sync pulses or,in the case of internally generated FSX, not reloading OXR.Continuous serial-port trans,fers can be accomplished without the use of framesync pulses if R/XFSM are set to one. In this mode, operation of the serial portis similar to continuous operation with frame sync except that a frame syncpulse is involved only in the first word transferred, and no further frame syncpulses are used. Followingthe first word transferred (see Figure 8-25), no internalframe sync pulses are generated, and frame sync inputs are ignored.Additionally, R/XFSM should be set prior to or during the first word transferredand must be set no later than the transfer of the N-1 bit of the first word, exceptfor transmit operations. For transmit operations in the fixed data-rate mode,XFSM must be set no later than the N-2 bit. Clearing R/XFSM must be performedno later than the N-1 bit to be recognized in the current cycle.Figure 8-25. Fixed Continuous Mode Without Frame SyncCLKX/RFSR/FSX (External)FSX (Internal)IIJJOR/OX -------------GDC~~1OXR LoadedI i I iXINT Set XINT XINTR/XFSM RINT RINTOXR Loaded Load OXR Load OXRRead ORRRead ORRTiming of RINT and XINT and data transfers to and from OXR and ORR, respectively,are the same as in fixed data-rate continuous mode with frame8-30Peripherals
Serial Portssync. This mode of operation also exhibits the same delay of 2.5 CLKX cyclesafter DXR is loaded before an internal FSX is generated. As in the case of continuousoperation in fixed data-rate mode with frame sync, DXR must be reloadedno later than transmission of the N-3 bit.When you use continuous operation in fixed data-rate mode, R/XFSM may beset and cleared as desired, even during active transfers, to enable or disablethe use of frame sync pulses as dictated by system requirements. Under mostconditions, the effect of changing the state of R/XFSM occurs during the transferin which the R/XFSM change was made, provided the change was madeearly enough in the transfer. For transmit operations with internal FSX in fixeddata-rate mode, however, a one-word delay occurs before frame sync pulsegeneration resumes when clearing XFSM to zero (see Figure 8-26). Therefore,one additional word is transferred in this case before the next FSX pulseis generated. <strong>Al</strong>so note that, as discussed previously, clearing XFSM will berecognized during the transmission of the current word being transmitted aslong as XFSM is cleared no laterthan the N-1 bit. Setting XFSM is recognizedas long as XFSM is set no later than the N-2 bit.Figure 8-26. Exiting Fixed Continuous Mode Without Frame Sync, FSX InternalI I I I III15t Word II2nd Word II3rd Word 14th WordI I5th Word IICLKX JLrLn..rLhJu-U-uu-U-uu-U-uu-U-uu-U-uULFSX I I I I I(Internal) n I In· n n rI I I I I IDX--------~~~~~~O
Serial PortsFigure 8-27. Variable Burst ModeCLKX/RFSR/FSX (External) _________ ---'2) Data transfer begins during the CLKX/R cycle in which FSX/R occurs, ratherthan the CLKXlR cycle following FSX/R, as is the case with fixed dataratetiming.3) With variable data-rate timing, frame sync inputs are ignored until the endof the last bit transferred, rather than the beginning of the last bit transferredas is the case with fixed data-rate timing.FSX (Internal) _________ ---'Dx/DR --------------~~-----------i i iDXR Loaded XINT RINTWhen you transmit continuously in variable data-rate mode with frame sync,timing is the same as for fixed data-rate mode, except for the differences betweenthese two modes as described under burst mode operation with variabledata-rate timing. The only other exception to this is that DXR must be reloadedno later than the N-4 bit to maintain continuous operation of the variable dataratemode (see Figure 8-28); no later than the N-3 bit for fixed data-ratemode.Figure 8-28. Variable Continuous Mode With Frame SyncCLKX/RFSR/FSX (External) ________ ---'FSX (Internal) ________ ---'';\'DX/DR --------------
Serial PortsContinuous operation in variable data rate mode without frame sync is alsosimilarto continuous operation without frame sync in fixed data-rate mode. Aswith variable data-rate mode continuous operation with frame sync (seeFigure 8-29), DXR must be reloaded no later than the N-4 bit to maintain continuousoperation. Additionally, when R/XFSM is set or cleared in the variabledata-rate mode, the modification must be made no later than the N-1 bit forthe result to be affected in the current transfer.Figure 8-29. Variable Continuous Mode Without Frame SyncCLKX/RFSR/FSX (External)FSX (Internal)----------------~----------------~OX/DR ----________ ~~r X!T It xITDXR Loaded R/XFSM RINTXINTRINTDXR LoadedLoad DXRRead ORRLoad DXRRead ORR8.2.13 TMS320C3x Serial Port Interface Examples8.2.13.1 Handshake Mode ExampleWhen handshake mode is used, both the transmit (FSX/DS/CLKX) and receive(FSR/DR/CLKR) signals are used to transmit and receive data, respectively.In other words, even if the TMS320C3x serial port is receiving data onlywith handshake mode, the transmit signals are still needed to transmit the acknowledgesignal. The serial port registers, setup for the TMS320C3x serialport handshake communication, as shown in Figure 8-22 are shown below:Global control011 xOxOxxxxOOOOOOOOxx011 001 OObTransmit port control 0111 hReceive port control 0111 hS_port timer control ·OFhS_port timer count OhS_port timer period ~ 01 h (if two C3xs have the samesystem clock)Note: x = user configurable.Since the FSX is set as an output and continuous mode is disabled when handshakemode is selected, the SFSM and RFSM bits should be set to 0 and the8-33
Serial PortsFSXOUT bit should be set to 1 in the global control register. The XRESET,RRESET, and HS bits should also be set to 1 in order to start the handshake.communication. It is recommended that the polarity of the serial port pins beset to active high for simplification. <strong>Al</strong>though the CLKX/CLKR can be set as eitherinput or output, it is recommended to set the CLKX as output and the CLKRas input. The rest of the bits are user configurable as long as both serial portshave the consistent setup.The serial port timer Is needed only if the CLKX or CLKR is configured as anoutput. In the above case, since only the CLKX is configured as an output, thetimer control register should be set to OFh. When the serial port timer is used,the serial timer period register must also be set to the proper value for the clockspeed. The serial porttimerclockspeed setup is similarto the TMS320C3xtimer.Refer to Section B.1 for detailed information on timer clock generation.The maximum clock frequency for serial transfers is F(CLKIN)/4 if the internalclock is used and F(CLKIN)/5.2 if an external clock is used. Therefore, if twoTMS320C3xs have the same system clock, as in the the case above., the timerperiod register should be set to be equal to or greater than 1 which make theclock frequency equal to F(CLKIN)/B. . .Examples of serial port register setups for the above case are shown below.(Assume two TMS320C3xs have the same system clock.)Setup 1:Global controlTransmit port controlReceive port controlS_port timer controlS_port timer countS_port timer periodSetup 2:Global controlTransmit port controlReceive port controlS_port timer controlS_port timer countS_port timer periodOEBC0064h0111 h0111 hOFhOh;;:: 01hOC000364h= 0111 h0111 h= OFhOh;;:: 01h; 32 bits, fixed data rate, burst mode,; FSX (output), CLKX (output) = F(CLKIN)/8; CLKR (input), handshake mode, transmit; and receive interrupt is enabled.; B bits, variable data rete, burst mode,; FSX (output), CLKX (output) = f(CLKIN)/24; CLKR (input), handshake mode, transmit; and receive interrupt is disabled.Since the data has a leading 1 and the acknowledge signal is a 0 in the handshakemode, the TMS320C3x serial port can distinguish the signals betweenthe data and the acknowledge signal. Therefore, even if the TMS320C3x serialport receives the data before the acknowledge signal, the data will not be misinterpretedas the acknowledge signal and be lost. In addition, the acknowledgesignal is not generated until the data is read from the data receive register,ORR. Therefore, the TMS320C3x will not transmit the data and the acknowledgesignal simultaneously.8-34Peripherals
Serial Ports8.2.13.2 Serial <strong>Al</strong>e Interface ExampleThe TlC320C4x analog interface chips (AIC) from Texas Instruments offer azero glue-logic interface to the TMS320C3x family of DSPs. The interface isshown in Figure 8-30. This interface is used as an example of the TMS320C3xserial port configuration and operation. .Figure 8-30. TMS320C3x Zero Glue-Logic Interface to TLC3204x ExampleTMS320C3x-TMS320C4xXFO RESET WORDClKRO SClKClKXO f-JOUT+FSRO FSR OUT-ORO t..DRf-FSXO ~ FSX IN+DXO..OX IN-TClKO..MClK -f-r-.~GNDVCCAnalogOutAnalogInThe TMS320C3x resets the AIC through the external pin XFO. It also generatesthe master clock for the AIC through the timer 0 output pin, TClKO. (Preciseselection of a sample rate may require the use of an external oscillator ratherthan the TClKO outputto drive the AIC MClK input.) In turn, the AIC generatesthe ClKRO and ClKXO shift clocks as well as the FSRO and FSXO frame synchronizationsignals.A typical use of the AIC requires an 8 kHz sample rate of the analog signal. Ifthe clock input frequency to the TMS320C3x device is 30 MHz, the followingvalues should be loaded into the serial port and timer registers.Serial Port:Port global control register:FSX/DXlClKX port control registerFSR/DR/ClKR port control registerTimer:Timer global control registerTimer period registerOE970300h00000111h00000111h000002C1h00000001h8.2.13.3 Serial AID and DIA Interface ExampleThe DSP201/2 and DSP1 01/2 family of D/As and AIDs from Burr Brown alsooffer a zero glue-logic interface to the TMS320C3x family of DSPs. The interfaceis shown in Figure 8-31. This interface is used as an example of theTMS320C3x serial port configuration and operation.8-35
Serial PortsFigure 8-31. TMS320C3x Zero Glue-Logic Interface to Burr Brown AID and DIA ExampleBurr Brown OSP102 NOBurr Brown OSP202 Of ACASC r--- +5V+5V- CASC-'--22pF TTMS320C3xXCLK ~ CLKRO CLKXO XCLKSOUTA ORO OXO SINA±2.75 V-t VINAVOUTA r-. ±3VSYNCSINBFSRO±2.75 V-t VINBFSXO ~ SYNCVOUTB ~ ±3V1 MOhmr-OSCOOSC1SSF f- +5VL+5V- SSF+5V- SWLCONV TCLKO CONVJy"y"y12.29 MHzT 1~Tu-1D~·V- -T 22pFThe DSP1 02 AID is interfaced to the TMS320C3x serial port receive side; theDSP202 D/A is interfaced to the transmit side. The AIDs and D/As are hardwired to run in cascade mode. In this mode, when the TMS320C3x initiates aconvert command to the AID, via the TCLKO pin, both analog inputs are convertedinto two 16-bit words which are concatenated to form one 32-bit word.The AID signals the TMS320C3x, via the AID's SYNC signal (connected to theTMS320C3x FSRO pin), that serial data is to be transmitted. The 32-bit wordis then serially transmitted, MSS first, out the SOUTA serial pin of the DSP1 02to the ORO pin of the TMS320C3x serial port. The TMS320C3x is programmedto drive the analog interface bit clock from CLKXO pin of the TMS320C3x. Thebit clock drives both the AID's and 01 A's XC LK input. The TMS320C3x transmitclock also acts as the input clock on the receive side of the TMS320C3x serialport. Since the receive clock is synchronous to the internal clock of theTMS320C3x, the receive clock can run at full speed (that is, f(H1 )/2).Similarly, upon receiving a convert command, the pipe lined D/A converts thelast word received from the TMS320C3x and signals the TMS320C3x, via theSYNC signal (connected to the TMS320C3x FSXO pin), to begin transmittinga 32-bit word representing the two channels of data to be converted. The data,transmitted from the TMS320C3x DXO pin is input to both the SINA and SINSinputs of the D/A as shown in the figure.8-36Peripherals
Serial PortsThe TMS320C3x is set up to transfer bits at the maximum rate of about 8 Mbpswith a dual channel sample tate of about 44.1 kHz. This standard mode, fixeddata rate signaling interface is configured by setting the following registers asdescribed below:Serial Port:Port global control register:FSX/DX/CLKX port control registerFSR/DR/CLKR port control registerReceive/transmit timer control registerTimer:Timer global control registerTimer period registerOEBC0040h00000111h00000111hOOOOOOOFh000002C1 h0000005Ah8.2.14 Serial Port Initialization/ReconfigurationThe serial ports are controlled through memory-mapped registers located onthe dedicated peripheral bus. A general procedure for initializing and/or reconfiguringthe serial ports follows:1 ) Halt the serial po rt by cleari ng the X RESET and/or R R ES ET bits of the se ria-port global-control register. This can be accomplished by writing a 0 tothe serial-port global-control register. Note that the serial ports are haltedon RESET.2) Configure the serial port via the serial-port global-control register (withXRESET = RRESET = 0), FSX/DX/CLKX and FSR/DR/CLKR port controlregisters, as well as the receive/transmit timer control register (with XHLD= RHLD = 0, receive/transmit timer counter register and the receive/transmittimer period register, if necessary. Refer to subsection 8.2.13,"TMS320C3x Serial Port Interface Examples."3) Start the serial port by setting the XRESET and RRESET bits of the serialportglobal-control register and the XHLD and RHLD bits of the serial portreceive/transmit timer control register, if necessary.8-37
DMA Controller8.3 DMA ControllerThe TMS320C3x has an on-chip Direct Memory Access (DMA) controller thatreduces the need forthe CPU to perform inpuVoutputfunctions. The DMA controllercan perform inpuVoutput operations without interfering with the operationof the CPU. Therefore, it is possible to interface the TMS320C3x to slowexternal memories and peripherals (AIDs, serial ports, etc.) without reducingthe computational throughput of the CPU. The result is improved system performanceand decreased system cost.A DMA transfer consists of two operations: a read from a memory location anda write to a memory location. The DMA controller can read from and write toany location in the TMS320C3x memory map. This includes allmemory-mapped peripherals. The operation of the DMA is controlled with thefollowing set of memory-mapped registers:QQDMA global-control registerDMA source address registerQ DMA destination address registerQDMA transfer counter registerThese registers, their memory-mapped addresses, and their functions areshown in Figure 8-32. Each of these DMA registers is discussed in thesucceeding subsections.8-38Peripherals
Figure 8-32. Memory-Mapped Locations for a DMA ChannelRegisterDMA Global Control (See Table B-7)ReservedReservedReservedDMA Source Address (subsection B.3.2)ReservedDMA Destination Address (subsection B.3.2)ReservedDMA Transfer Counter (subsection B.3.3)ReservedReservedReservedReservedReservedReservedReservedPeripheralAddressBOBOOOhBOB001hBOB002hBOB003hBOB004hBOB005hB08006h808007h808008h808009hB0800AhB0800Bh80800ChB0800Dh80800Eh80800Fh8.3.1 DMA Global-Control RegisterThe global-control register controls the state in which the DMA controller operates.This register also indicates the status of the DMA, which changes everycycle. Source and destination addresses can be incremented, decremented,or SYNChronized using specified global-control register bits. At system reset,all bits in the DMA control register are set to O. Table 8-7 lists the register bits,names, and functions. Figure 8-33 shows the bit configuration of the globalcontrolregister.8-39
DMA ControllerFigure 8-33. DMA Global-Control Register31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16I xx I xx I xx I xx I xx xx xx I xx xx xx xx xx xx xx xx xx15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0xx xx xx xx I TCINT I TC SYNC I DECDSTI INCDST I DECSRC I INCSRC I STAT STARTRIW RIW RIW R/W R/W R/W R/W R/W R R R/W RIWNOTE: xx = Reserved bit, read as O.R = read, W = write.Table 8-7. DMA Global-Control Register BitsBit Name Reset Value Function0-1 START 0-0 These bits control the state in which the DMA starts and stops. TheDMA may be stopped without any loss of data (see Table 8-8).2-3 STAT 0-0 These bits indicate the status of the DMA and change every cycle(see Table 8-9).4 INCSRC 0 If INCSRC = 1, the source address is incremented after every read.5 DECSRC 0 If DECSRC = 1, the source address is decremented after everyread. If INCSRC = DECSRC, the source address is not modified aftera read.6 INCDST 0 If INCDST = 1, the destination address is incremented after everywrite.7 DECDST 0 If DECDST = 1, the destination address is decremented after everywrite. If INCDST = DECDST, the destination address is not modifiedafter a write.9-8 SYNC 0-0 The SYNC bits determine the timing synchronization between theevents initiating the source and the destination transfers. The interpretationof the SYNC bits is shown in Table 8-10.10 TC 0 The TC bit affects the operation of the transfer counter. If TC = 0,transfers are not terminated when the transfer counter becomeszero. If TC = 1, transfers are terminated when the transfer counterbecomes zero.11 TCINT 0 If TCINT = 1, the DMA interrupt is set when the transfer countermakes a transition to zero. If TCINT = 0, the DMA interrupt is not setwhen the transfer counter makes a transition to zero.31-12 Reserved 0-0 Read as zero.8-40 Peripherals
DMA ControllerTable 8-8. START Bits and Operation of the DMA (Bits 0-1)STARTFunction00 DMA read or write cycles in progress will be completed; any data read will be ignored.Any pending read or write will be cancelled. The DMA is reset so that whenit starts, a new transaction begins; i.e., a read is performed. (Reset value)01 If a read or write has begun, it is completed before it stops: for example, in themiddle or at the end of a DMA transfer. If a read or write has not begun, no reador write is started.1 0 If a DMA transfer has begun, the entire transfer is completed (including both readand write operations) before stopping. If a transfer has not begun, none is started.1 1 DMA starts from reset or restarts from the previous state.Table 8-9. STAT Bits and Status of the DMA (Bits 2-3)STATFunction00 DMA is being held between DMA transfer (between a write and read). This is thevalue at reset. (Reset value)01 DMA is being held in the middle of a DMA transfer, i.e., between a read and a write.1 0 Reserved.1 1 DMA busy; i.e., DMA is performing a read or write.Table 8-10. SYNC Bits and Synchronization of the DMA (Bits 8-9)SYNCFunction00 No synchronization. Enabled interrupts are ignored. (Reset value)01 Source synchronization. A read is performed when an enabled interrupt occurs.1 0 Destination synchronization. A write is performed when an enabled interrupt occurs.1 1 Source and destination synchronization. A read is performed when an enabled interruptoccurs. A write is then performed when the next enabled interrupt occurs.8-41
DMA Controller8.3.2 Destination and Source Address RegistersThe DMA destination and source address registers are 24-bit registers whosecontents specify destination and source addresses. As specified by control bitsDECSRC, INCSRC, DECDST, and INCDST olthe DMA global control register,these registers are incremented and decremented at the end of the correspondingmemory access, that is, the source register for a read, the destinationregister for a write. On system reset, 0 is written to these registers.8.3.3 Transfer Counter RegisterThe transfer counter register is a 24-bit register, controlled by a 24-bit counterthat counts down. The counter decrements at the beginning of a DMA memorywrite. In this way, it can be used to control the size of a block of data transferred.The transfer counter register is set to 0 at system reset. When TCINT bit ofDMA global control register is set, the transfer counter register will cause aDMA interrupt flag to be set upon count down to zero.8.3.4 CPU/DMA Interrupt Enable RegisterThe CPU/DMA interrupt enable register (IE) is a 32-bit register located in theCPU register file. The CPU interrupt enable bits are in locations 10- 1. TheDMA interrupt enable bits are in locations 26 - 16. A 1 in a CPU/DMA interruptenable register bit enables the corresponding interrupt. A 0 disables the correspondinginterrupt. At reset, 0 is written to this register.Table 8-11 lists the bits, names, and functions of the CPU/DMA interrupt enableregister. Figure 8-34 shows the IE register. The priority and decodingschemes of CPU and DMA interrupts are identical. Note that when the DMAreceives an interrupt, this interrupt is acted upon according to the SYNC fieldof the DMA control register. <strong>Al</strong>so note that an interrupt may affect the DMA butnot the CPU and may affect the CPU but not the DMA. Refer to Chapter 6 andto subsection 3.1.8.8-42Peripherals
DMA ControllerFigure 8-34. CPUIDMA Interrupt Enable Register31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16RJW RJW RJW RfW RJW RJW ANI RJW RJW RJW RJW15 14 13 12 11 10 9 8 7 6 5 4 3 2 0NOTE: xx = Reserved bit, read as O.R = read, W = write.RJW RJW RJW RJW RJW RJW ANI RJW RJW RJW RJWTable 8-11. CPUIDMA Interrupt Enable Register BitsBit Name Function0 EINTO Enable external interrupt 0 (CPU)1 EINT1 Enable external interrupt 1 (CPU)2 EINT2 Enable external interrupt 2 (CPU)3 EINT3 Enable external interrupt 3 (CPU)4 EXINTO Enable serial-port 0 transmit interrupt (CPU)5 ERINTO Enable serial-port 0 receive interrupt (CPU)6 EXINT1 Enable serial-port 1 transmit interrupt (CPU)7 ERINT1 Enable serial-port 1 receive interrupt (CPU)8 ETINTO Enable timer 0 interrupt (CPU)9 ETINT1 Enable timer 1 interrupt (CPU)10 EOINT Enable OMA controller interrupt (CPU)15-11 Reserved Read as 016 EINTO Enable external interrupt 0 (OMA)17 EINT1 Enable external interrupt 1 (OMA)18 EINT2 Enable external interrupt 2 (OMA)19 EINT3 Enable external interrupt 3 (OMA)20 EXINTO Enable serial-port 0 transmit interrupt (OMA)21 ERINTO Enable serial-port 0 receive interrupt (OMA)22 EXINT1 Enable serial-port 1 transmit interrupt (OMA)23 ERINT1 Enable serial-port 1 receive interrupt (OMA)24 ETINTO Enable timer 0 interrupt (OMA)25 ETINT1 Enable timer 1 interrupt (OMA)26 EOINT Enable OMA controller interrupt (OMA)31-27 Reserved Read as 08-43
DMA Controller8.3.5 DMA Memory Transfer OperationEach DMA memory transfer consists of two parts:1) Read data from the address specified by the DMA source register.2) Write data that has been read to the address specified by the DMA destinationregister.A transfer is complete only when the read and write are complete. A transfermay be stopped by setting the START bits to the desired value. When the DMAis restarted (START = 1 1), it completes any pending transfer.At the end of a DMA read, the source address is modified as specified by the .SRCINC and SRCDEC bits of the DMA global control register. At the end ofa DMA write, the destination address is modified as specified by the DSTINCand DSTDEC bits of the DMA global control register. At the end of every DMAwrite, the DMA transfer counter is decremented.DMA on-chip reads and writes (reads and writes from on-chip memory and peripherals)are single cycle. DMA off-chip reads are two cycles. The first cycleis the external read, and the second cycle loads the DMA register. The externalread cycle is identical to a CPU read cycle. DMA off-chip writes are identicalto CPU off-chip writes. If the DMA has been started and is transferring dataover either external bus, the bus control register associated with that busshould not be modified. If the bus control register (see Chapter 7) needs to bemodified, the DMA should be stopped, modification made, and then the DMArestarted. Failure to do so may produce an unexpected zero-wait-state bus access.Through the 24-bit source and destination registers, the DMA is capable of accessingany memory-mapped location in the TMS320C3x memory map.Figure 8-35 through 8-34 show the number of cycles a DMA transfer requires,depending upon whether the source and destination are on-chip memory andperipherals, the external port, or the I/O port. Trepresents the number of transfersto be performed, Cr represents the number of wait-states for the sourceread, and C w represents the number of wait-states for the destination write.Each entry in the table represents the total cycles required to do the T transfers,assuming that there are no pipeline conflicts.Accompanying each table is a figure illustrating the timing of the DMA transfer.IRI and IWI represent single-cycle reads and writes, respectively. IR.RI andIW.WI represent multicycle reads and writes. ICrl and ICwl show the numberof wait cycles for a read and write.8-44Peripherals
DMA ControllerFigure 8-35.Timing and Number of Cycles for DMA Transfers When Destination Is On-ChipCycles (H1) 1 1213141516171819110111112113114115116117118119Source On-Chip RI IR I IR I : : : : : : : : : : : : :: : : : : : : : : : : : : : : : : :Destination On-Chip Iwl Iwl Iwl : : : : : : : : : : : :Source Primary Bus R.R.R: I I I R.R. R: I I I R.R. R :11 : : : :I C r I : : I C r I : : I C r I : : : : :: : : : : : : : : : : : : : : : : :Destination On-Chip : : : Iwl : : : Iwl : : : Iwl : : :Source Expansion Bus R .R .R: II I R .R. R: II I R.R. R: II : : : :: I C r I : : I C r I : : I C r I : : : : :: : : : : : : : : : : : : : : : : :Destination On Chip : : : Iwl : : : Iwl : : : Iwl : : :SourceOn-ChipPrimary BusExpansion BusDestination On-Chip(1+1) T(2+Cr+1)T(2+Cr+1)TLegend:TC rC wIRIIWIIR.RIIW.WII IINumber of transfersSource-read wait statesDestination-write wait statesSingle-cycle readsSingle-cycle writesMulticycle readsMulticycle writesInternal register cycle8-45
DMA ControllerFigure 8-36. DMA Timing When Destination Is a Primary BusCycles (H1) 1 1213141516171819110111112113114115116117118119Source On-Chip RI IR I : : IR I : : : : : : : : : : :: : : : : : : : : : : : : : : : : :Iw.w.w.wlw.w.W.WIW.W.w.wl : : : : :Destination Primary Bus : : I C w I : I Cw I : I C w I : : : : :Source Primary Bus R.R.R: I I : : : .R .R .R : II : : : : : :I C r I : : : : I C r I : : : : : :: : : : : : : : : : : : : : : : :: : : Iw.w.W.W : : : Iw.w.w.wl : :Destination Primary Bus : : : : : I Cw : : : : : I Cw I : :Source Expansion Bus R .R.R : II I R. R. R II IR.R .R : II : : : :I C r I : : I C r : : I C r I : : : : :: : : : : : : : : : : : : : : : :: : : Iw.w.w,.W Iw.w.w.wl Iw.w.w.wlDestination Primary Bus: : : : : I Cw : : I C w I : : I C w ISourceOn-ChipPrimary BusExpansion BusDestination Primary Bus1+(2+Cw)T(2+Cr+2+Cw) T(2+ Cr+2+ Cw)+(2+Cw+max(O, Cr Cw+1))(T-1)Legend:TC rC WIRIIWIIR.RIIW.WIIIINumber of transfersSource-read wait statesDestination-write wait statesSingle-cycle readsSingle-cycle writesMulticycle readsMulticycle writesInternal register cycle8-46Peripherals
DMA ControllerFigure 8-37. DMA Timing When Destination Is an Expansion BusCycles (H1) 1 1213141516171819110111112113114115116117118119Source On-Chip RI IR I IR I : : : : : : : : :: : : : : : : .' : : : : : : : : : :Iw.w.w.wlw.w.w.wlw.w.w.wl : : : : :Destination Expansion Bus : : I Cw I : I Cw I : I Cw : : : : :Source Primary Bus R.R.RI II IR.R .R I I IR.R.R ": : : :I C r I : : I C r : : I C r : : : : :: : : : : : : : : : : : : : : :: : : Iw.w.W.W Iw.w.w.W Iw.w.w.wlDestination Expansion Bus : : : : : I Cw : : I C w : : I C w ISource Expansion Bus R .R.R: I I : : : R.R .R: II : : : : :I C r I : : : : I C r I : : : : : :: : : : : : : : : : : : : : : :: : : Iw.w.w.W : : : Iw.w.w.wl : :Destination Expansion Bus : : : : : I Cw : : : : : I C w I : :Legend:SourceDestination Expansion BusOn-Chip 1+(2+Cw )TPrimary BusExpansion Bus(2+ Cr+2+ Cw)+(2+Cw+max(O,Cr Cw+1))(T-1)(2+Cr+2+Cw) TTC rCwIRIIWIIR.RIIW.WII I INumber of transfersSource-read wait statesDestination-write wait statesSingle-cycle readsSingle-cycle writesMulticycle readsMulticycle writesInternal register cycle8-47
DMA ControllerTable 8-12 shows the maximum DMA transfer rates, assuming that there areno wait states (Cr = Cw = 0). Table 8-13 shows the maximum DMA transferrates, assuming there is one wait state for the read (Cr = 1) and no wait statesfor the write (Cw = 0). Table 8-14 shows the maximum DMA transfer rates,assuming there is one wait state for the read (Cr = 1) and one wait state for thewrite (Cw = 1).In each table, the time for the complete transfer (the read and the write) is considered.Since one bus access is required forthe read and anotherforthe write,internal bus transfer rates will be twice the DMA transfer rate. It is also assumedthat no conflicts with the CPU exist.Table 8-12. Maximum DMA Transfer Rates When C r = Cw = 0SourceDestinationInternal Primary ExpansionInternal 33.3 Mbytes/sec 33.3 Mbytes/sec 33.3 Mbytes/secPrimary 22.2 Mbytes/sec 16.7 Mbytes/sec 22.2 Mbytes/secExpansion 22.2 Mbytes/sec 22.2 Mbytes/sec 16.7 Mbytes/secTable 8-13. Maximum DMA Transfer Rates When Cr = 1, Cw = 0SourceDestinationInternal Primary ExpansionInternal 33.3 Mbytes/sec 33.3 Mbytes/sec 33.3 Mbytes/secPrimary 16.7 Mbytes/sec 13.3 Mbytes/sec 16.7 Mbytes/secExpansion 16.7 Mbytes/sec 16.7 Mbytes/sec 13.3 Mbytes/secTable 8-14. Maximum DMA Transfer Rates When Cr = 1, Cw = 1DestinationSourceInternal Primary ExpansionInternal 33.3 Mbytes/sec 22.2 Mbytes/sec 22.2 Mbytes/secPrimary 16.7 Mbytes/sec 11.1 Mbytes/sec 16.7 Mbytes/secExpansion 16.7 Mbytes/sec 16.7 Mbytes/sec 11.1 Mbytes/sec8-48 Peripherals
DMA Controller8.3.6 Synchronization of DMA ChannelsA DMA channel may be synchronized through the use of interrupts. Refer toTable 8-10 forthe relationship between the SYNC bits of the DMA global controlregister and the synchronization performed. This section describes the followingfour synchronization mechanisms:[:'I No synchronization (SYNC = 0 0)Q Source synchronization (SYNC = 0 1)Q Destination synchronization (SYNC = 1 0)Q Source and destination synchronization (SYNC = 1 1)No SynchronizationFigure 8-38. No DMA SynchronizationWhen SYNC = 0 0, no synchronization is performed. The DMA performs readsand writes whenever there are no conflicts. <strong>Al</strong>l interrupts are ignored and,therefore, are considered to be globally disabled. However, no bits in the DMAinterrupt enable register are changed. Figure 8-38 shows the synchronizationmechanism when SYNC = 0 O.Disable DMA Interrupts GloballyDMA Channel Performs a ReadDMA Channel Performs a WriteSource SynchronizationWhen SYNC = 0 1, the DMA is synchronized to the source (see Figure 8-39).A read will not be performed until an interrupt is received by the DMA. Then,all DMA interrupts are disabled globally. However, no bits in the DMA interruptenable register are changed.8-49
DMA ControllerFigure 8-39. DMA Source SynchronizationDestination SynchronizationFigure 8-40. DMA Destination SynchronizationWhen SYNC = 1 0, the DMA is synchronized to the destination. First, all interruptsare ignored until the read is complete. Though the DMA interrupts are beconsidered to be globally disabled, no bits in the DMA interrupt enable registerare changed. A write will not be performed until an interrupt is received by theDMA. Figure 8-40 shows the synchronization mechanism when SYNC = 1 O.DMA Interrupts Are Enabled GloballyIdle Until Enabled Interrupt Is ReceivedDisable DMA Interrupts GloballySource and Destination SynchronizationWhen SYNC = 1 1, the DMA is synchronized to both the source and destination.A read is performed when an interrupt is received. A write is performedon the following interrupt. Source and destination synchronization when SYNC= 1 1 is shown in Figure 8-41.8-50Peripherals
DMA ControllerFigure 8-41. DMA Source and Destination SynchronizationIdle Until Enabled Interrupt is ReceivedDisable DMA Interrupts GloballyDMA Channel Performs a ReadEnable DMA Interrupts GloballyIdle Until Enabled Interrupt Is ReceivedDisable DMA Interrupts GloballyDMA Channel Performs a WriteEnable DMA Interrupts Globally8.3.7 DMA InterruptsA DMA interrupt to the CPU may be generated whenever the transfer countreaches zero, indicating that the last transfer has taken place. The TCINT bitin the DMA global control register determines whether the interrupt will be generated.If TCINT = 1, the DMA interrupt is generated. If TCINT = 0, the DMAinterrupt is not generated. If the DMA interrupt is generated, the EDINT bit, bit10 in the interrupt enable register, must also be set to enable the CPU to beinterrupted by the DMA.A second bit in the DMA global control register, the TC bit, is also generally associatedwith the state of the TCINT bit and the interrupt operation. The TC bitdetermines if transfers are terminated when the transfer counter becomes zeroor if they are allowed to continue. If TC = 1, transfers are terminated when thetransfer count becomes zero. If TC = 0, transfers are not terminated when thetransfer count becomes zero.In general, if TCINT is ° then TC should also be set to 0. Otherwise, the DMAtransfer will terminate and the CPU will not be notified. If TCINT is 1 then inmost cases TC should also be 1. In this case, the CPU will be notified whenthe transfer completes and the DMA will be halted and ready to start a newtransfer.8-51
DMA Controller8.3.8 DMA Setup and Use ExamplesTransfer a 256-word block of data from off-chip memory to on-chip memoryand generate an interrupt on completion. the order of memory is to be maintained.DMA source address: 800000hDMA destination address: 809800hDMA transfer counter: 00000100hDMA global control:00000C53hCPU/DMA interrupt enable (IE): 00000400hTransfer a 128-word block of data from on-chip memory to off-chip memoryand generate an interrupt on completion. The order of memory is to be inverted,i.e., the highest addressed member of the block is to become the lowestaddressed member.DMA source address: 809800hDMA destination address: 800000hDMA transfer counter: 00000080hDMA global control:00000C93hCPU/DMA interrupt enable (IE): 00000400hTransfer a 200-word block of data from the serial port 0 receive register to onchipmemory and generate an interrupt on completion. The transfer is to besynchronized with the serial port 0 receive interrupt.DMA source address: 80804ChDMA destination address: 809COOhDMA transfer counter: 000000C8hDMA global control:OOOOOD43hCPU/DMA interrupt enable (IE): 00200400hTransfer a 200-word block of data from off-chip memory to the serial port 0transmit register and generate an interrupt on completion. The transfer is to besynchronized with the serial port 0 transmit interrupt.DMA source address:809COOhDMA destination address: 808048hDMA transfer counter:OOOOOOC8hDMA global control:OOOOOE13hCPU/DMA interrupt enable (IE): 00400400h8-52Peripherals
DMA ControllerTransfer data continuously between the serial port 0 receive register and theserial port 0 transmit register to create a digital loop back. The transfer is to besynchronized with the serial port 0 receive and transmit interrupts.DMA source address:BOB04ChDMA destination address: BOB04BhDMA transfer counter:OOOOOOOOhDMA global control:00000303hCPU/DMA interrupt enable (IE): 00600000h8.3.9 DMA Initialization/ReconfigurationThe DMA is controlled through memory-mapped registers located on the dedicatedperipheral bus. A general procedure for initializing and/or reconfiguringthe DMA follows:1) Halt the DMA by clearing the START bits of the DMA global-control register.This can be accomplished by writing a 0 to the DMA global-control register.Note that the DMA is halted on RESET.2) Configure the DMA via the DMA global-control register (with START = 00),as well as the DMA source, destination, and transfer-counter registers, ifnecessary. Refer to subsection B.3.B, "DMA Setup and Use Examples."3) Start the DMA by setting the START bits of the DMA global-control registeras necessary.8-53
8-54 Peripherals
~ ______ p_iP_e_li_n_e_o_p_e_r_a_ti_o_n __________________________________ ~'f__-I11III
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Pipeline Structure;:;';:;:;:;:;:;-;:;';:;s::::::::';':';-;';:::;~:::::';::'::;';:::;::::'::-::::::::::m:::;::::~;::::::~::;o;::::::,~;:;:::;:::::;:;::::::,;,;:::;,;y;.:.;.;.;-;:;::.;.::: ...-:-;.;«:".-x-:.;o;.;-;-:::::-:o;.;-; .... ;:;.,;«-;-;.;o;o;.~:';-;0;';';0;0;,,';-;0;':0;-:';0;';';';';0;';';';';':';';';';-:';-;';';':';':";-;-;-;':':';:;';',';';';';';';0;';';';';';':';0;';';';';':"';';';':0;';';';';';';';':0;';' .. :0;';';';';';';.;.;.:.;.;.,;.:.;0; .... ;0:.;.;0;.;.; ... ; ••• :.:.;.;.;.;.;.; ••• ;.;';';';';';';';0;';';-;';:;';';0;0;';',';';0;':';':';::::-;';::.;:::::::;:;::::::.:::.;.::::::;.::::::::::;::::::%9.1 Pipeline StructureThe five major units of the TMS320C3x pipeline structure and their functionsare as follows:Fetch Unit (F)Decode Unit (D)Read Unit (R)Execute Unit (E)DMA Channel (DMA)Fetches the instruction words from memory andupdates the program counter (PC).Decodes the instruction word and performs addressgeneration. <strong>Al</strong>so controls any modification ofthe auxiliary registers and the stack pointer.If required, reads the operands from memory.If required, reads the operands from the registerfile, performs the necessary operation, and writesresults to the registerfile. If required, results of previousoperations are written to memory.Reads and writes memory.A basic instruction has four levels: fetch, decode, read, and execute.Figure 9-1 illustrates these four levels of the pipeline structure. The levels areindexed according to instruction and execution cycle. The perfect overlap inthe pipeline, where all four units operate in parallel, occurs at cycle (m). Thoselevels about to be executed are at m + 1 , and those just executed are at m-1 .The TMS320C3x pipeline control allows a high-speed execution rate of one executionper cycle. It also manages pipeline conflicts so that they are transparentto the user. You do not need to take any special precautions to guaranteecorrect operation.9-2Pipeline Operation '
I-JtnClIt,-"Cl StructureFigure 9-1. TMS320C3x Pipeline StructureCYCLE F D R Em-3 wm-2 x wm-1 y x wm z y x W 4-4 --- Perfect overlapm+1 z y xm+2 z ym+3 zNotes: 1) W, X, Y, and Z represent instructions.2) F, 0, R, E = fetch, decode, read, and execute, respectively.Priorities from highest to lowest have been assigned to each of the functionalunits as follows:a Execute (highest)a Reada Decodea Fetcha DMA (lowest).When the processing of an instruction is ready to pass to the next higher pipelinelevel, but that level is not ready to accept a new input, a pipeline conflictoccurs. In this case, the lower priority unit waits until the higher priority unitcompletes its currently executing function.Despite the DMA controllers low priority, conflicts with the CPU can be minimizedor even eliminated by suitable data structuring because the DMA controllerhas its own data and address buses.9-3
i-Jlnt:llinQ Conflicts9.2 Pipeline ConflictsThe pipeline conflicts of the TMS320C3x can be grouped into the followingmain categories:Branch ConflictsRegister ConflictsMemory ConflictsInvolve most of those instructions or operationsthat read and/or modify the PC.Involve delays that can occur when reading from orwriting to registers that are used for address generation.Occur when the internal units of the TMS320C3xcompete for memory resources.Each of these three types is discussed in the following sections. Examples areincluded. Note in these examples, when data is refetched or an operation isrepeated, the symbol representing the stage of the pipeline is appended witha number. For example, if a fetch is performed again, the instruction mnemonicis repeated. When an access is detained multiple cycles because of not ready,the symbols RDY and RDY are used to indicate not ready and ready, respectively.9.2.1 Branch ConflictsThe first class of pipeline conflicts occurs with standard (non-delayed)branches, i.e., BR, Bcond, DBcond, CALL, IDLE, RPTB, RPTS, RETlcond,RETScond, interrupts, and reset. Conflicts arise with these instructions andoperations because during their execution, the pipeline is used only for thecompletion of the operation; other information fetched into the pipeline is discardedor refetched, or the pipeline is inactive. This is referred to as flushingthe pipeline. Flushing the pipeline is necessary in these cases to guaranteethat portions of succeeding instructions do not inadvertently get partially executed.TRAPcond and CALLcond are classified differently from the othertypes of branches and are considered later.Example 9-1 shows the code and pipeline operation for a standard branch.Note that one dummy fetch is performed (MPYF instruction), and then after thebranch address is available, a new fetch (OR instruction) is performed. Thisdummy fetch affects the cache.9-4Pipeline Operation
Pipeline ConflictsExample 9-2. Delayed BranchDelayed branches are implemented to guarantee the fetching of the next threeinstructions. The delayed branches include BRD, BconaO, and DBconaO.Example 9-2 shows the code and pipeline operation for a delayed branch.BRDMPYFADDSUBFANDTHREE; Unconditional delayed branch; Executed; Executed; Executed; Not executedTHREEMPYF; Fetched after SUBF is fetchedPIPELINE OPERATIONPCnn+1F D R EBRDMPYF BRD No execute delayn+2ADDF MPYF BRDn+3SUBF ADDF MPYF BRD)HREEMPYF SUBF ADDF MPYFTHREE~PC9.2.2Register ConflictsRegisterconflicts involve the reading orwriting of registers used for addressingpurposes. These conflicts occur when the pertinent register is not ready to beused. Some conditions under which register conflicts can be avoided are discussedin Section 9.3.The registers compose the following three functional groups:9-6Pipeline Operation
J.J/na/ir:la ConflictsGroup 1Group 2Group 3Auxiliary registers (ARO - AR7), index registers (IRO, IR1), andblock size register (SK)Data-page pointer (DP)System stack pointer (SP)If an instruction writes to one of these three groups, the decode unit cannot useany register within that particular group until the write is complete, i.e., instructionexecution is completed. In Example 9':"'3, an auxiliary register is loaded,and a different auxiliary register is used on the next instruction. Since the decodestage needs the result of the write to the auxiliary register, the decode ofthis second instruction is delayed two cycles. Every time the decode is delayed,a refetch of the program word is performed; i.e., the ADDF is fetched threetimes. Since these are actual refetches, they can cause not only conflicts withthe DMA controller but also cache hits and misses.Example 9-3. Write to an AR Followed by an AR for Address GenerationLDI 7,ARl i 7 -7 ARlNEXT MPYF *AR2,RO i Decode delayed 2 cyclesADDFFLOATPIPELINE OPERATIONPCFI DREnLOIn+1n+2MPYFADDFLOIMPYFLDrDecode/addressgeneration heldfor a new AR valuen+2ADDFMPYF(nap)LDr 7, ARlAR110adedn+2ADDFMPYF(nap)(nap)n+3FLOATADDFMPYF(nap)The case for reads of these groups is similar to the case for writes. If aninstruction must read a member of one of these groups, the use of that particulargroup by the decode for the following instruction is delayed until the readis complete. The registers are read at the start of the execute cycle and thereforerequire only a one-cycle delay of the following decode. For four registers(IRQ, IR1, SK, or DP) no delay is incurred. In all other cases, including the SPthe delay occurs.9-7
I-Jln~flr:l~ ConflictsIn Example 9-4, two auxiliary registers are added together with the result goingto an extended-precision register. The next instruction uses a different auxiliaryregister as an address register.Example 9-4. A Read of ARs Followed by ARs for Address GenerationADDI ARO,AR1,Rl ; ARO + ARl ~ RlNEXT MPYF *++AR2,RO ; Decode delayed 1 cycleADDFFLOATPIPELINE OPERATIONPCnn+1n+2n+2n+3F D R EADD!MPYF ADDIADDF~~ADDI ..ADDF MPYF (nop) ADD! ARO,AR1,ROFLOAT ADDF MPYF (nop)Decode/addressgeneration helduntil AR is readARs readThe DBR (decrement and branch) instruction's use of auxiliary registers forloop counters is treated the same as if the use were for addressing. Therefore,the operation shown in the two previous examples can also occur for this instruction.9-8Pipeline Operation
Pipeline Conflicts~::;~::;:;:;:o:;:~;:;:;:;:>:::;::x:::::::;:" ..;:::;:;;;:::;:;:::;:::::;:::;:;:;:;:;:;:::;:;:;:;:;:::;:;:::;.~;o;:;.;:;.;.:.;:;';';';';--':;":":;';';';'::::;0;,;,;,;,;:;,;,;,;,;:;,::;::,;,,';0;.;.;.::;.;.;0;.;.;.;.;.;-;.;.;.;,.;.;.;.;-;.;.,;.;.:.;.;.;.;.;•••;.;.;.;.;.;.;-:0;.:.;.;.;.;.;.;.;.;.....;.;.;.;.;.;.;.:.;0;.;.;.;.:--......;.;.;.;-;.;.;.;::.;.;.;.;.;.:.;.;.;.;.;.;.;.......;•••••••;•••;.:•••;...;.;•••;.;...;•••;•••;•••;•••;.;•••;.;.;.;•••••;•••;.;.;.;::.;...........;.....;.;0;.;.;0;...,;.:.;.;o;.:.......;:••;:;y:..:.:;:......;:•.;:::::::;••••:.:;:;:;:;:::;:::;:;:::;:;:::::::;:::::::::;:::::::::::0:9.2.3 Memory ConflictsMemory conflicts can occurwhen the memory bandwidth of a physical memoryspace is exceeded. For example, RAM blocks 0 and 1 and the ROM block cansupport only two accesses every cycle. The external interface can support onlyone access per cycle. Some conditions under which memory conflicts can beavoided are discussed in Section 9.4.Memory pipeline conflicts consist of the following four types:Program WaitProgram Fetch IncompleteExecute OnlyHold EverythingA program fetch is prevented from beginning.A program fetch has begun but is not yetcomplete.An instruction sequence requires three CPUdata accesses in a single cycle.A primary or expansion bus operation mustcomplete before another one can proceed.These fourtypes of memory conflicts are illustrated in examples and discussedin the paragraphs that follow.Program WaitTwo conditions can prevent the program fetch from beginning:I:l The start of a CPU data access when• Two CPU data accesses are made to an internal RAM or ROM block,and a program fetch from the same block is necessary.• One of the external ports is starting a CPU data access, and a programfetch from the same port is necessary.I:l A multicycle CPU data access or DMA data access over the external busis needed.9-9
Pipeline Conflicts~;.:>';:;::~«;:«-x::~;x:;:::-~::-«-:::::::~;:~~;:;::W~~~~~:9
Winc.It,.,c. ConflictsExecute OnlyThe Execute Only type of memory pipeline conflict occurs when a sequenceof instructions requires three CPU data accesses in a single cycle or when per':forming an interlocked load. There are three cases in which this occurs:QQAn instruction performs a store and is followed by an instruction that doestwo memory reads.An instruction performs two stores and is followed by an instruction thatperforms at least one memory read.Example 9-8. Single Store Followed by Two ReadsQ An interlocked load (LOll or LOFI) instruction is performed, and XF1 = 1.The first case is shown in Example 9-8. Since this sequence requires threedata memory accesses and only two are available, only the execute phase ofthe pipeline is allowed to proceed. The dual reads required by the LDF II LDFis delayed one cycle. Note that a refetch of the next instruction can occur.IISTFLDFLDFRO,*ARl*AR2,Rl*AR3,R2i RO ~ *ARli *AR2 ~ Rl in parallel withi *AR3 ~ R2PIPELINE OPERATIONPCF0 REnSTFn+1 LDFII LDFSTFn+2 wn+3 xn+4 xLDFII LDFwwSTFLDFII LDFLDFII LDF,/Write must complete,/ before the twoSTF RO,*ARl reads can complete.(nap)n+4 yx ~"1LDFII LDF*AR2,Rl and *AR3,R29-12Pipeline Operation
Pipeline Conflicts:!.:::::::::::::::::::;.::.::::::::::::::::::::::::::: ;:;:;:;.;:;:::;:::;:;:;:::::.:;:;.;:;-;.;:;.;.:o;:::::.~•••.••;:1..:::.·;·.·.:::.:::::::::::.· ..;·;·;..·.. n.: ...·;·u... I. ...·.·f..:;••::,.;:::•••••••••!••••••••; •••;•••••••••••••••••••••••••;•••••••••••••••••••••••••; •••••••••••••••••••••••;.;.;.........................................; •••••••••••;...............................................................................; •••;............................................................................................:•••••••••:•••:.:::•••••:.:::.:.:.:.:.:::.:.:.:::.:::::::::.:.:::.:.:::::::::::::Example 9-9 shows a parallel store followed by a single load or read. Sincethe two parallel stores are required, the next CPU data memory read must waita cycle before beginning. One program memory refetch may occur.Example 9-9. Parallel Store Followed by Single ReadSTF RO, *ARO'/I STF R2, *ARIADDF @SUM,RllACKASHi RO ~ *ARO in parallel withi R2 ~ *ARli Rl + @SUM ~ RlPIPELINE OPERATIONPC F 0 RnSTF// STFn+1 ADDF STFII STFEr arecompleten+2 lACK ADDF STF// STFn+3 ASH lACK ADDFSTFII STFRO, *ARO and R2,*ARln+4 ASH lACK ADDF(nap)n+4 ASH lACKADDF9-13
I-ilnalir.a ConflictsExample 9-10. Interlocked LoadThe final case involves an interlocked load (LOll or LOFI) instruction and XF1= 1. Since the interlocked loads use the XF1 pin as an acknowledge that theread can complete, they may need to extend the read cycle, as shown inExample 9-10. Note that a program refetch may occur.NOTLDIIADDICMPIRl,RO300h,AR2*AR2, R2RO, R2PIPELINE OPERATIONPC F. D R EnNOTn+1 LDII NOTn+2 ADDIn+3 eMF In+3 ~XF1 = 1LDII NOTADDI LDII XF1 =0eMF I ADDI LDIIn+4 eMF I ADDI LDII9-14 Pipeline Operation
IJIMOllrlO ConflictsExample 9-11. Busy External PortHold EverythingThere are three types of Hold Everything memory pipeline conflicts:El A CPU data load or store cannot be performed because an external portis busy.El An external load takes more than one cycle.El Conditional calls and traps.The first type of Hold Everything conflict occurs when one of the external portsis busy due to an access that has started but is not complete. In Example 9-11,the first store is a two-cycle store. The CPU writes the data to an external port.The port control then takes two cycles to complete the data-data write. TheLDF is a read over the same external port. Since the store is not complete, theCPU continues to attempt LDF until the port is available.STFLDFRO,@DM<strong>Al</strong>@DMA2,ROPIPELINE OPERATIONPCnF o R ESTFn+1LDFSTFn+2n+2n+2n+3n+4w LDF STFw LDF (nap) STF I"2-cycle external busw LDF (nap) (nop)J, write accessx w LDF (nop)y x W LDFThe second type of Hold Everything conflict involves multicycle data reads.The read has begun and continues until completed. In Example 9-12, the LDFis performed from an external memory that requires several cycles to complete.9-15
lJinalir:.a ConflictsExample 9-12. Multicycle Data ReadsLDF@DMA,ROPCnPIPELINE OPERATIONF D RLOFEILDFJ I LOFK I (dummy) I LOF2-cycle external bus.l.. read accessILDFThe final type of Hold Everything conflict deals with conditional calls and traps,which are different from the other branch instructions. Whereas the otherbranch instructions are conditional loads, the conditional calls and traps areconditional stores, which take one cycle more than a conditional branch (seeExample 9-13). The added cycle is used to push the return address after thecall condition is evaluated.Example 9-13.Conditional Calls and TrapsPIPELINE OPERATIONPC F D R EnCALLcondn+1 I CALLcondn+1 (nop) (nop) CALLcondn+1 (nap) (nap) (nap) CALLcondPC storen+1 (nap) (nap) (nap) CALLcond T cycle+n+2/CALLaddr I (nap) (nap) (nap)9-16Pipeline Operation
Resolving Memory ConflictsTable 9-2 shows how many accesses can be performed from the differentmemory spaces when it is necessary to do a program fetch and two data accesses,still achieving maximum performance (one cycle). Six cases achievethis maximization.Table 9-2.One Program Fetch and Two Data Accesses for Maximum PerformanceCase # Primary Bus Accesses From Expanslont OrAccesses Dual-Access Peripheral BusInternal MemoryAccesses2 from any1 1 combination -of internal memory2t 1 Program 1 Data 1 Data3t 1 Data 1 Data 1 Program4 -2 from same internalmemory block and1 from a different -internal memoryblock5 -3 from differentinternal memory -blocks2 from any6 - combination 1of internal memoryt Expansion bus available only on TMS320C30.9-20Pipeline Operation
Clocking of Memory Accesses~;:;:;:;:;:;:::;:;:;~:;:;:;:::::::::;:'Q:;:;:;:;:::;:;:;:
Clocking of Memory Accesses9.5.2 Data Loads and StoresFigure 9-2. Two-Operand Instruction WordFourtypes of instructions perform loads, memory reads, and stores: two-operandinstructions, three-operand instructions, multiplier/ALU operation withstore instructions, and parallel multiply and add instructions. See Chapter 5 fordetailed information on addressing modes.As discussed in Chapter 7, the number of bus cycles for external memoryaccesses differs in some cases from the number of CPU execution cycles. Forexternal reads, the number of bus cycles and CPU execution cycles is identical.For external writes, there are always at least two bus cycles, but unlessthere is a port access conflict, there is only one CPU execution cycle. In thefollowing examples, any difference in the number of bus cycles a'nd CPU cyclesis noted.Two-Operand Instruction Memory AccessesTwo-operand instructions include all those instructions with bits 31 - 29 being000 or 010 (see Figure 9-2). In the case of a data read, bits 15 - 0 representthe srcoperand. Internal data reads are always performed during H1. Externaldata reads always start at the beginning of H3 with the address being presentedon the external bus, and they complete with the latching of the data wordat the end of H1.In the case of a data store, bits 15 - 0 represent,the dstoperand. Internal datastores are performed during H3. External data stores always start at the beginningof H3 with the address and data being presented on the external bus.2423 1615 871 ,I1 1 11 11 I1 1Operation _ G dst(src) I isrc(dst)Three-Operand Instruction Memory ReadsThree-operand instructions include all instructions with bits 31 - 29 being 001(see Figure 9-3). The source operands, src1 and src2, come from either registersor memory. When one or more of the source operands are from memorythese instructions are always memory reads.If only one of the source operands is from memory (either src1 or src2) and islocated in internal memory, the data is read during H1. If the single memorysource operand is in external memory, the read starts at the beginning of H3,with the address being presented on the external bus, and completes with thelatching of the data word at the end of H1.9-22Pipeline Operation
9-26 Pipeline Operation
Assembly Language Instructions
1IIIPD"~ _____________________ A_s_s_e_m_b_IY __ L_a_ng_u_a_g_e __ ln_s_tr_u_c_ti_o_n_s ______ ~
Assembly Language Instructionsr:i Individual Instructions (Section 10.3 on page 10-12)• Symbols and abbreviations used in instructions• Optional assembler syntaxes• Individual instruction descriptions alphabetized and includingSyntaxOperationOperandsEncodingDescriptionCyclesStatus bitsMode bitExample(s)10-2 Assembly Language Instructions
Instruction Set10.1 Assembly Language Instructions - Instruction SetThe TMS320C3x instruction set is exceptionally well-suited to digital signal processingand other numeric-intensive applications. <strong>Al</strong>l instructions are a single machine word long,and most instructions take a single cycle to execute. In addition to multiply and accumulateinstructions, the TMS320C3x possesses a full complement of general-purpose instructions.The instruction set contains 113 instructions organized into the following functionalgroups:QQQQLoad-and-storeTwo-operand arithmetic/logicalThree-operand arithmetic/logicalProgram controlQ Interlocked operationsa Parallel operationsEach of these groups is discussed in the succeeding subsections.10.1.1 Load-and-Store InstructionsThe TMS320C3x supports 12 load-and-store instructions (see Table 10-1). These instructionscanQLoad a word from memory into a register,a Store a word from a register into memory, ora Manipulate data on the system stack.Two of these instructions can load data conditionally. This is useful for locating the maximumor minimum value in a data set. See Section 10.2 for detailed information on conditioncodes.Table 10-1. Load-and-Store InstructionsInstruction Description Instruction DescriptionLDE Load floating-paint exponent POP Pop integer from stackLDF Load floating-point value POPF Pop floating-point value from stackLDFcond Load floating-point value PUSH Push integer on stackconditionallyLDI Load integer PUSHF Push floating-point value on stackLDlcond Load integer conditionally STF Store floating-point valueLDM Load floating-point mantissa STI Store integer10-3
Instruction Set10.1.2 Two-Operand InstructionsThe TMS320C3x supports a complete set of 35 two-operand arithmetic and logical instructions.The two operands are the source and destination. The source operand maybe a memory word, a register, or a part of the instruction word. The destination operand isalways a register.These instructions provide integer, floating-point, or logical operations, and multiprecisionarithmetic. Table 10-2 lists these instructions.Table 10-2. Two-Operand InstructionsInstruction Description Instruction DescriptionABSF Absolute value of a floating- NORM Normalize floating-point valuepoint numberABSI Absolute value of an integer NOT Bitwise logical-complementADDCt Add integers with carry ORt Bitwise logical-ORADDFt Add floating-point values RND Round floating-point valueADDlt Add integers ROL Rotate leftANDt Bitwise logical-AND ROLC Rotate left through carryANDNt Bitwise logical-AND with ROR Rotate rightcomplementASHt Arithmetic shift RORC Rotate right through carryCMPFt Compare floating-point values SUBBt Subtract integers with borrowCMPlt Compare integers SUBC Subtract integers conditionallyFIX Convert floating-point value to SUBF Subtract floating-point valuesintegerFLOAT Convert integer to floating-point SUBI Subtract integervalueLSHt Logical shift SUBRB Subtract reverse integer withborrowMPVFt Multiply floating-point values SUBRF Subtract reverse floating-pointvalueMPVlt Multiply integers SUBRI Subtract reverse integerNEGB Negate integer with borrow TSTBt Test bit fieldsNEGF Negate floating-point value XORt Bitwise exclusive-ORNEGINegate integertTwo- and three-operand versions10-4 Assembly Language Instructions
Instruction Set10.1.3 Three-Operand InstructionsMost instructions have only two operands; however, some arithmetic and logical instructionshave three-operand versions. The 17 three-operand instructions allow theTMS320C3x to read two operands from memory or the CPU register file in a single cycleand store the results in a register. The following differentiates the two- and three-operandinstructions:QQTwo-operand instructions have a single source operand (or shift count) and a destinationoperand.Three-operand instructions may have two source operands (or one source operandand a count operand) and a destination operand. A source operand may be a memoryword or a register. The destination of a three-operand instruction is always a register.Table 10-3 lists the instructions that have three-operand versions. Note that the 3 in themnemonic can be omitted from three-operand instructions (see Section 10.3.2).Table 10-3. Three-Operand InstructionsInstruction Description Instruction . DescriptionADDC3 Add with carry MPYF3 Multiply floating-point valuesADDF3 Add floating-point values MPYI3 Multiply integersADDI3 Add integers OR3 Bitwise logical-ORAND3 Bitwise logical-AND SUBB3 Subtract integers with borrowANDN3 Bitwise logical-AND with complement SUBF3 Subtract floating-point valuesASH3 Arithmetic shift SUBI3 Subtract integersCMPF3 Compare floating-point values TSTB3 Test bit fieldsCMPI3 Compare integers XOR3 Bitwise exclusive-ORLSH3Logical shift10.1.4 Program Control InstructionsThe program-control instruction group consists of all of those instructions (16) that affectprogram flow. The repeat mode allows repetition of a block of code (RPTB) or of a singleline of code (RPTS). Both standard and delayed (single-cycle) branching are supported.Several of the program control instructions are capable of conditional operations (seeSection 11.2 for detailed information on condition codes). Table 10-4 lists the programcontrol instructions.10-5
Instruction SetTable 10-4. Program Control InstructionsInstruction Description Instruction DescriptionBcond Branch conditionally (standard) IDLE Idle until interruptBconaD Branch conditionally (delayed) NOP No operationBR Branch unconditionally (standard) RETlcond Return from interrupt conditionallyBRD Branch unconditionally (delayed) RETScond Return from subroutineconditionallyCALL Call subroutine RPTB Repeat block of instructionsCALLcond Call subroutine conditionally RPTS Repeat single instructionDBcond Decrement and branch SWI Software interruptconditionally (standard)DBconaD Decrement and branch TRAPcond Trap conditionallyconditionally (delayed)lACKInterrupt acknowledge10.1.5 Interlocked Operations InstructionsThe interlocked operations instructions support multiprocessor communication and theuse of external signals to allow for powerful synchronization mechanisms. They also guaranteethe integrity of the communication and result in a high-speed operation. Refer toChapter 7 for examples of the use of interlocked instructions.Table 10-5. Interlocked Operations InstructionsInstruction Description Instruction DescriptionLDFI Load floating-point value, interlocked STFI Store floating-point value, interlockedLDII Load integer, interlocked STII Store integer, interlockedSIGI Signal, interlocked10.1.6 Parallel Operations InstructionsThe parallel-operations instructions group makes a high degree of parallelism possible.Some of the TMS320C3x instructions can occur in pairs that will be executed in parallel.These instructions offer the following features:El Parallel loading of registers,QParallel arithmetic operations, orQ Arithmetic/logical instructions used in parallel with a store instruction.Each instruction in a pair is entered as a separate source statement. the second instructionin the pair must be preceded by two vertical bars (II). Table 1 0-6 lists the valid instructionpairs.10-6Assembly Language Instructions
Instruction SetTable 10-6. Parallel InstructionsMnemonicABSFII STFABSIII STIADDF3II STFADDI3IISTIAND3IISTIASH3IISTIFIXIISTIFLOATII STFLDFII STFLDIIISTILSH3IISTIMPYF3II STFMPYI3IISTINEGFII STFNEGIII STINOTII STIOR3II STISTFII STFSTIII STISUBF3II STFDescriptionParallel Arithmetic with Store InstructionsAbsolute value of a floating-point number and store floating-point valueAbsolute value of an integer and store integerAdd floating-point values and store floating-point valueAdd integers and store integerBitwise logical-AND and store integerArithmetic shift and store integerConvert floating-point to integer and store integerConvert integer to floating-point value and store floating-point valueLoad floating-point value and store floating-point valueLoad integer and store integerLogical shift and store integerMultiply floating-point values and store floating-point valueMultiply integer and store integerNegate floating-point value and store floating-point valueNegate integer and store integerComplement value and store integerBitwise logical-OR value and store integerStore floating-point valuesStore integersSubtract floating-point value and store floating-point value10-7
Instruction SetTable 10-6. Parallel Instructions (Concluded)MnemonicSUBI3II STIXOR3II STILDFII LDFLDIII LDIMPYF3II ADDF3MPYF3II SUBF3MPYI3II ADDI3MPYI3II SUBI3DescriptionParallel Arithmetic with Store Instructions (Concluded)Subtract integer and store integerBitwise exclusive-OR values and store integerParallel Load InstructionsLoad floating-pointLoad integerParallel Multiply and Add/Subtract InstructionsMultiply and add floating-pointMultiply and subtract floating-pointMultiply and add integerMultiply and subtract integer10-8 Assembly Language Instructions
Condition Codes and10.2 Condition Codes and FlagsThe TMS320C3x provides 20 condition codes (00000 - 10100 excluding 01 011) that canbe used with any of the conditional instructions, such as RETScondor LDFcond. The conditionsinclude signed and unsigned comparisons, comparisons to zero, and comparisonsbased on the status of individual condition flags. Note that all conditional instructions canaccept the suffix U to indicate unconditional operation.Seven condition flags provide information about properties of the result of arithmetic andlogical instructions. The condition flags are stored in the status register (ST) and are affectedby an instruction only when either of the following two cases occurs:Q The destination register is one of the extended-precision registers (R7 - RO). Thisallows for modification of the. registers used for addressing but does not affect the conditionflags during computation.QThe instruction is one of the compare instructions (CMPF, CMPF3, CMPI, CMPI3,TSTB, or TSTB3). This makesit possible to set the condition flags according to thecontents of any of the CPU registers.The condition flags may be modified by most instructions when either of the precedingconditions is established and either of the following two cases occurs:QQTable 10-7. Output Value FormatsA result is generated when the specified operation is performed to infinite precision.This is appropriate for compare and test instructions that do not store results in a register.It is also appropriate for arithmetic instructions that produce underflow or overflow.The output is written to the destination register as shown in Table 10-7. This is appropriatefor other instructions that modify the condition flags.Type Of OperationOutput Format, Floating-point 8-bit exponent, 1 sign bit, 31-bit fractionIntegerLogical32-bit integer32-bit unsigned integerFigure 10-1 shows the condition flags in the low-order bits of the status register. Followingthe figure is a list of status register condition flags and descriptions on how the flags areset by most instructions. For specific details of the effect of a particular instruction on thecondition flags, see the despription of that instruction in subsection 10.3.3.10-9
Condition Codes andTable 10-8 lists the condition mnemonic, code, description, and flag for each of the 19condition codes.Table 10-8. Condition Codes and FlagsCondition Code Description FlagtUnconditional ComparesU 00000 Unconditional Don't careUnsigned ComparesLO 00001 Lower than CLS 00010 Lower than or same as CORZHI 00011 Higher than -CAND-ZHS 00100 Higher than or same as -CEQ 00101 Equal to ZNE 00110 Not Equal to -ZSigned ComparesLT 00111 Less than NLE 01000 Less than or equal to NORZGT 01001 Greater than -NAND-ZGE 01010 Greater than or equal to -NEQ 00101 Equal to ZNE 00110 Not equal to -ZCompare to ZeroZ 00.101 Zero ZNZ 00110 Not zero -ZP 01001 Positive -NAND-ZN 00111 Negative NNN 01010 Nonnegative -NCompare to Condition FlagsNN 01010 Nonnegative -NN 00111 Negative NNZ 00110 Nonzero -ZZ 00101 Zero ZNV 01100 No overflow -VV 01101 Overflow VNUF 01110 No underflow -UFUF 01111 Underflow UFNC 00100 No carry -CC 00001 Carry CNLV 10000 No latched overflow -LVLV 10001 Latched overflow LVNLUF 10010 No latched floating-point underflow -LUFLUF 10011 Latched floating-point underflow LUFZUF 10100 Zero or floating-point underflow ZORUFt The - means logical complement (Unot true" condition).10-11
Individual Instructions10.3 Individual InstructionsThis section contains the individual assembly language instructions for the TMS320C3x.The instructions are listed in alphabetical order. Information for each instruction includesassembler syntax, operation, operands, encoding, description, cycles, status bits, modebit, and examples.Definitions of the symbols and abbreviations, as well as optional syntax forms allowed bythe assembler, precede the individual instruction description section. <strong>Al</strong>so, an example instructionshows the special format used and explains its content.A functional grouping of the instructions as well as a complete instruction set summarycan be found in Section 10.1. Appendix B lists the opcodes for all the instructions. Referto Chapter 6 for information on memory addressing. Code examples using many of theinstructions are given in Chapter 11, Software Applications.10.3.1 Symbols and AbbreviationsTable 10-9 lists the symbols and abbreviations used in the individual instruction descriptions.Table 10-9. Instruction SymbolsSymbolsrcSource operandsrc1 Source operand 1src2 Source operand 2src3 Source operand 3src4 Source operand 4dstDestination operanddst1 Destination operand 1dst2 Destination operand 2dispDisplacementcondConditioncountShift countGTPBARnIRnRnRCRERSSTMeaningGeneral addressing modesThree-operand addressing modesParallel addressing modesConditional-branch addressing modesAuxiliary register nIndex register nRegister address nRepeat count registerRepeat end address registerRepeat start address registerStatus register10-12 Assembly Language Instructions
Individual InstructionsTable 10-9.Instruction Symbols (Concluded)SymbolCGIENPCRMSPIxlx....:; yx(man)x(exp)Carry bitGlobal interrupt enable bitTrap vectorProgram counterRepeat mode flagSystem stack pointerMeaningAbsolute value of xAssign the value of x to destinat'ion yMantissa field (sign + fraction) of xExponent field of xop1IIop2 Operation 1 performed in parallel with operation 2xANDy Bitwise logical-AND of x and yxORyBitwise logical-OR of x and yxXORy Bitwise logical-XOR of x and y-x Bitwise logical-complement of xx «yShift x to the left y bitsx» y Shift x to the right y bits*++SPIncrement SP and use incremented SP as address*SP--Use SP as address and decrement SP10.3.2 Optional Assembler SyntaxesThe assembler allows a relaxed syntax form for some instructions. These optional formssimplify the assembly language so that special-case syntax can be ignored. The followingis a list of these optional syntax forms.Q The destination register can be omitted on unary arithmetic and logical operationswhen the same register is used as a source. For example,ABSI RO,RO can be written as ABSI ROInstructions affected: ABSI, ABSF, FIX, FLOAT, NEGB, NEGF, NEGI, NORM, NOT,RND.Q <strong>Al</strong>l 3-operand instructions can be written without the 3. For example,ADDI3 RO,Rl,R2 can be written as ADDI RO,Rl,R2Instructions affected: ADDC3, ADDF3, ADDI3, AND3, ANDN3, ASH3, LSH3,MPYF3, MPYI3, OR3, SUBB3, SUBF3, SUBI3, XOR3.This also applies to all the pertinent parallel instructions.Q <strong>Al</strong>l 3-operand comparison instructions can be written without the 3. For example,CMPI3 RO,*ARO can be written as CMPI RO,*AROInstructions affected: CMPI3, CMPF3, TSTB3.Q Indirect operands with an explicit 0 displacement are allowed. In 3-operand or parallelinstructions, operands with 0 displacement are automatically converted to no-displacementmode. For example:10-13
Individual InstructionsQQQQLDI<strong>Al</strong>so*+ARO (0) , Rl is legalADDI3*+ARO (0) , Rl, R2 is equivalent to ADDI3 *ARO, Rl, R2Indirect operands can be written with no displacement, in which case a displacementof one is assumed. For example,LDI *ARO++ (1) , RO can be written LDI *ARO++, RO<strong>Al</strong>l conditional instructions accept the suffix U to indicate unconditional operation.<strong>Al</strong>so, the U can be omitted from unconditional short branch instructions. For example:BU label can be written B labelLabels can be written with or without a trailing colon. For example:labelO:labelllabe12:NOPNOP(label assembles to next source line)Empty expressions are not allowed for the displacement in indirect mode:LDI *+ARO () ,RO is not legalQ Long immediate mode operands (destination of SR and CALL) can be written with anat sign:BR label can be written BR @labelQ The LOP pseudo-op can be used to load a register (usually OP) with the 8 MSSs ofa relocatable address as follows:QLDP addr, REG or LDP @addr,REGThe at sign is optional.Ifthe destination REG is the OP, the OP can be omitted in the operand. LOP generatesan LOI instruction with an immediate operand, and a special relocation type.Parallel instructions can be written in either order. For example:ADDIII STIcan be written asSTIII ADDIQ The parallel bars indicating part 2 of a parallel instruction can be written anywhere onthe line from column 0 to the mnemonic. For example:ADDIII STIcan be written asADDII I STIEl If the second operand of a parallel instruction is the same as the third (destination register)operand, the third operand can be omitted. This allows the writing of 3-operandparallel instructions that look like normal 2-operand instructions. For example,ADDI *ARO, R2, R2 can be written as ADD *ARO,R2I I MPYI *ARl,RO,ROI I MPYI *ARl, RO10-14Assembly Language Instructions
Individual InstructionsInstructions (applies to all parallel instructions that have a register second operand)affected: ADDI, ADDF, AND, MPYI, MPYF, OR, SUBI, SUBF, XOR.a <strong>Al</strong>l commutative operations in parallel instructions can be written in either order. Forexample, the ADD I part of a parallel instruction can be written in either of two ways:ADDI *ARO,Rl,R2 or ADDI Rl,*ARO,R2The instructions affected are parallel instructions containing any of the following:ADDI, ADDF, MPYI, MPYF, AND, OR, XOR.a Use the syntax in Table 10-10 to designate CPU registers in operands. Note the alternateform using designators RO - R27.10.3.3 Individual Instruction DescriptionsEach assembly language instruction for the TMS320C3x is described in this section in alphabeticalorder. The description includes the assembler syntax, operation, operands, encoding,description, cycles, status bits, mode bit, and examples.Table 10-10. CPU Register SyntaxAssemblers <strong>Al</strong>ternate Register AssignedSyntax Syntax FunctionRO RO Extended·precision registerR1 R1 Extended-precision registerR2 R2 Extended-precision registerR3 R3 Extended-precision registerR4 R4 Extended-precision registerR5 R5 Extended-precision registerR6 R6 Extended-precision registerR7 R7 Extended-precision registerARO R8 Auxiliary registerAR1 R9 Auxiliary registerAR2 R10 Auxiliary registerAR3 R11 Auxiliary registerAR4 R12 Auxiliary registerAR5 R13 auxiliary registerAR6 R14 Auxiliary registerAR7 R15 Auxiliary registerDP R16 Data-page pointerIRO R17 Index register 0IR1 R18 Index register 1BK R19 Block-size registerSP R20 Active stack pointerST R21 Status registerIE R22 CPU/DMA interrupt enableIF R23 CPU interrupt flags10F R24 110 flagsRS R25 Repeat start addressRE R26 Repeat end addressRC R27 Repeat counter10-15
SyntaxINST src, dstorINST1 src2, dst1II INST2 src3, dst2Each instruction begins with an assembler syntax expression. Labels may beplaced either before the command (instruction mnemonic) on the same line oron the preceding line in the first column. The optional comment field that concludesthe syntax is not included in the syntax expression. Space(s) are requiredbetween each field (label, command, operand, and comment fields).The syntax examples illustrate the common one-line syntax and the two-linesyntax used in parallel addressing. Note that the two vertical bars II that indicatea parallel addressing pair can be placed anywhere before the mnemonicon the second line. The first instruction in the pair can have a label, but the secondinstruction cannot have a label.OperationIsrc I -? dstorIsrc21 -? dst1II src3 -? dst2The instruction operation sequence describes the processing that takes placewhen the instruction is executed. For parallel instructions, the operation sequenceis performed in parallel. Conditional effects of status register specifiedmodes are listed for conditional instructions such as Bcond.Operandssrcgeneral addressing modes (G):0 register (Rn, 0 s; n s; 27)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0 s; n s; 27)orsrc2 indirect (disp = 0, 1, IRO, IR1)dst1 register (Rn1, 0 s; n1 s; 7)src3 register (Rn2, 0 s; n2 s; 7)dst2 indirect (disp = 0, 1, IRO, IR1)Operands are defined according to the addressing mode and/or the type of addressingused. Note that indirect addressing uses displacements and the indexregisters. Refer to Chapter 5 for detailed information on addressing.10-16Assembly Language Instructions
EXAMPLE~x;:'mnlp InstructionMode BitExampleOVM Overflow Mode Flag. In general, integer operations are affected by theOVM bit value (described in Table 3-2 on page 3-7).INST @98AEh,R5Before Instruction:DP = 80hR5 = 0766900000h = 2.30562500e+02Memory at 8098AEh = 5CDFh = 1.000011 07e + 00LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:DP = 80hR5 = 0066900000h = 1.80126953e + 00Memory at 8098AEh = 5CDFh = 1.000011 07e + 00LUF LV UF N Z V C = 0 0 0 0 0 0 0The sample code presented in the above format shows the effect of the codeon system pointers (e.g., DP or SP), registers (e.g., R1 or R5), memory at specificlocations, and the seven status bits. The values given for the registers includethe leading zeros to showthe exponent in floating-point operations. Decimalconversions are provided for all register and memory locations. The sevenstatus bits are listed in the order in which they appear in the assembler and simulator(see Table 10-8 and Section 10.2 on page1 0-9 for further informationon these seven status bits).10-18Assembly Language Instructions
Absolute Value of Floating-PointABSF;:;:;:::::::::;:::::::::::::::::::;:;:::::::::;:::::::;:;:::;:::::;:::::;:::;:;:;:::;:;:;:;:::::;:;:::::;:::::::;:::::::::;:;:;:::;:;:::;:;:;.;:;:;.;:::;.;.;:!:::;:;:::::;.;:.:;:;:::;:;:::;:::::;:;:;:::;.;:;.;:::;.;.;:;:••;:••;:;:;:;:;:;:;:;:;:;.;:;:;:.... ~ ••;:;:;:;:;:••;:;...;•••;.;••:;.;:;••:•••:;.;:•••:;...;.;.;.;:=:.:;•••;••••••:.:••;0.:;••:;:;••:.:;•••••;••:.:.....:.-...................................................................'...............:............ 0' ...............: •••:.:•••: •••••••: •••: •••:•••••:.:•••:.:.:.:.:.:;••:.:.:.:.:.:.:.:.:.:.:::;:;:;:;:.:;:,::;:;:.~;:;:;:;:::;:;:;:;:;:;:;=~;=::SyntaxOperationOperandsABSF src, dstIsrcl ~ dstsrc general addressing modes (G):o 0 register (Rn, 0 ::; n ::; 7)o 1 direct1 0 indirect1 1 immediatedst register (Rn, ::; 0 n::; 7)Encoding13 \ 1 1 1 1 1 124123100000 0000 Gi i116115,dst .87IsrcIDescriptionThe absolute value of the src operand is loaded into the dst register. The srcand dst operands are assumed to be floating-point numbers.An overflow occurs if src (man) = 80000000h and src (exp) = 7Fh. The resultis dst (man) = 7FFFFFFFh and dst (exp) = 7Fh.CyclesStatus BitsMode BitThese condition flags are modified only ifthe destination register is R7 -LUF Unaffected.LV 1 if a floating-point overflow occurs, unchanged otherwise.UF o.N o.ZVC1 if a zero result is generated, 0 otherwise.,1 if a floating-point overflow occurs, 0 otherwise.Unaffected.OVM Operation is not affected by OVM bit value.RO.ExampleABSFR4,R7Before Instruction:R4 = 05C8000F971 h = -9.90337307e + 27R7 = 0702511 OOAEh = 5.48527255e + 37LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R4 = 05C8000F971 h = -9.90337307e + 27R7 = 05C7FFF068Fh = 9.90337307e + 27LUF LV UF N Z V C = 0 0 0 0 0 0 010-19
j:\BSFIJSTF . Parallel ABSF and STF::.:.:.'.~.~.:.:.:.:.:.:.:.::.:••:.:.y.:;:.:.:.:.:;:.::::::!::::::::::::::::.:::::::::.:::::::.:::.:::::.:.:.:::::::.:::.:::::::::.:::::.:.:.:.:.:.:::.:::.:.:.:.:.:::::::::.:.:::.·~.:.:.:.:.:.:.:.:.:.·.:u.:.:.:.:::::::::::;:;:::::::::::::::::::::;:::::::::;:::::::::::::::::.:;0::;-;:::::::::::::;'::::::::::::;:::;-;::::y;,::.;::.:.:::.::::::;o;:~:::::o;:;::.;o;:••;:;:::::;:::;o;::::.:.::::;:;:::~:.:...:••::.;-;o.;.;:::::;::::::.:::::.::;:;:::.:;.;•• ~ •••••;::.~;.;::.;o;..;::.;O:::::';9'••:"y';y'::::~.;:::: :::::.:::::.!,f.::::::::::::::::::::::::::::::::::::::::::::;:.::;:::::-,o,::::::".::::::::::SyntaxOperationOperandsABSF src2, dst1II STF src3, dst2IIIsrc21 --7 dst1src3 --7 dst2src2 indirect (disp = 0, 1, IRO, IR1)dst1 register (Rn1, 0 :::; n1 :::; 7)src3 register (Rn2, 0 :::; n2 ~ 7)dst2 indirect (disp = 0, 1, IRO,. IR1)EncodingDescription31 2423 16 15· 1 · · · i 1 · · '10' O' 01 iii ·0 0 0 0 1 1 1 dst1 _ _ src3 • • • •••dst2src2A floating-point absolute value and a floating-point store are performed in parallel.<strong>Al</strong>l registers are read at the beginning and loaded at the end of the executecycle. This means that if one of the parallel operations (STF) reads from a registerand the operation being performed in parallel (ABSF) writes to the sameregister, then STF accepts as input the contents of the register before it is modifiedby the ABSF.If src2and dst2pointto the same location, src2is read before the write to dst2.If src3 and dst1 point to the same register, src3 is read before the write to dst1.An overflow occurs if src (man) = 80000000h and src (exp) = 7Fh. The resultis dst (man) = 7FFFFFFFh and dst (exp) = 7Fh.CyclesStatus BitsMode BitExampleLUFLVUFNZVCUnaffected.1 if a floating-point overflow occurs, unchanged otherwise.O.O.1 if a zero result is generated, 0 otherwise.1 if a floating-point overflow occurs, 0 otherwise.Unaffected.OVM Operation is not affected by OVM bit value.ABSF *++AR3 (IR1) ,R4II STF R4, *- AR7 (1)10-20Assembly Language Instructions
ABSI Absolute Value of Integer::::;:::;:::;:;:;.;:::;:::::::::;:;:::::;:;:;:::::::::::::;:;:;:::::::,;:;:;:;:;:;:;:::::::::;o;:::;:~;:::::::;:;:;:::;:;::::::';:::::;:::::::::::.:::::::::;:::;0;';:::;:;:.:.',:.-.".:.;:;:.:;.;:;.::;:::;:::::::::::;:::;::.; ••• ;.;:;~;.;:;::::::.:::.;::.:.;.;.;.;.;: •• ;-::;:;-;.::;.;:;.;.;.;.;.;.;.;.;.;.;:;.;:: •• :::;.;::.;.;.;.;.;.;.:.;.;.;.;.;.;.;.;.;.;::.;.:.;.:.;.:.:.;.;.;.;.;.:::.;.;:::;.;.;.;.;:::::;.;.;.;.;.;.;.; ••• :.;.;.;.; ••••• ;.;.;.;.:.;.;:;.; ••• ; •• ::.;.;0.:;.;.;0;.;.;.;.; ••• ; ••• : ••••• ;.;0;.;:: •• :.:;';';:;';';';';:;:::;:::.:;:::.:;:;:::::;:.:::::;:::::;:,;:::::;:::::::::::;:::;:::;:::::;::::::::::SyntaxOperationOperandsABSI src, dstIsrcl-7 dstsrc general addressing modes (G):o 0 register tRn, 0 $ n $ 27)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0 $ n $ 27)Encoding(1, , I 1 , , , 24,231i 16 15,87i i i i000000001 G dst _src1DescriptionThe absolute value of the src operand is loaded into the dst register. The srcand dst operands are assumed to be signed integers.An overflow occurs if src = 80000000h. If ST(OVM) = 1, the result isdst = 7FFFFFFFh. If ST(OVM) = 0, the result is dst = 80000000h.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 - RO.LUF Unaffected. 'LV 1 if an integer overflow occurs, unchanged otherwise.UF O.N O.ZVC1 if a zero result is generated, 0 otherwise.1 if an integer overflow occurs, 0 otherwise.Unaffected.OVM Operation is affected by OVM bit value.Example 1ABSIorABSIRO,ROROBefore Instruction:RO = OFFFFFFCBh = - 53After Instruction:RO = 035h = 5310-22Assembly Language Instructions
Absolute Value of IntegerASSI~;:;:;:;:::;:;:;:::::;:::::::::;:;:;:;:;:;:::::;:::::::::::::::::::::::::::::;:::::::::::::::::::::::::::::::::::;:::::.:.:::.:.:::::::::;.;.;:::.:::;::: ••;:::.:::;••:.:::::.:.:;.;:•••:;••:••;••:.:•••••:;.;.;:;.;.;.;:.:•••:.:•••••:•••:••;:•••••••:•••:••••••••••••••••;.;.;.••••••;.;••:••••••:••:•• ~;: •••••:•••:••••••••••;:••;.;••:.....:.:.:;•• ~ ••••.••••••:.:••;:.: ••••.;•••;............................................................."..................................................................................•••:.:.......:•••••••••••••:.......:•••:.:.:.:::::::::::;0:::.0;0;:::::::;'::::::::.:;':.:::::;':Example 2 ABSI *AR1,R3Before Instruction:AR1 = 20hR3 = OhData at 20h = OFFFFFFCBh = - 53After Instruction:AR1 = 20hR3 = 35h = 53Data at 20h = OFFFFFFCBh = - 5310-23
SyntaxASSIII STIsrc2, dst1src3, dst2OperationOperandsIIsrc2dst1src3dst2Isrc21 ~ dst1src3 ~ dst2indirect (disp = 0, 1, IRO, IR1)register (Rn1, 0 ::; 1 ::; 7)register (Rn2, 0 ::; n2 ::; 7)indirect (disp = 0, 1, IRO, IR1)Encodingiiidst2iiisrc2DescriptionAn integer absolute value and an integer store are performed in parallel. <strong>Al</strong>lregisters are read at the beginning and loaded at the end of the execute cycle.This means that if one of the parallel operations (STI) reads from a register andthe operation being performed in parallel (ABSI) writes to the same register,then STI accepts as input the contents of the register before it is modified bythe ABS!.If src2 and dst2 point to the same location, src2 is read before the write to dst2.An overflow occurs if src = 80000000h. If ST(OVM) = 1, the result is dst =7FFFFFFFh. If ST(OVM) = 0, the result is dst = 80000000h.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV 1, if an integer overflow occurs, unchanged otherwise.UF O.N O.Z 1 if a zero result is generated, 0 otherwise.V 1 if an integer overflow occurs, 0 otherwise.C Unaffected.OVM Operation is affected by OVM bit value.RO.10-24Assembly Language Instructions
Parallel ABSI and STIABSIIISTI;:~;:;:.:;:;:::;:;:;!;:;:;:;:;:;:;:;:::;::::::::::::~:::;::!;:;:;:;:::::::::::;:::;:;:::;:;:::;::=-:;:;:::.:.·;:.:;:;:;:.s:.:.=-·~!o:::':::6»:::;S!o:::h:.';:;:':.:':;::Y..~"~:':;O.:;:;:,:.:.·.:,:,:,:,:.·.y.·.·;:,..............:.•••..:.:.:.:,••:...:.:.:...:.:::•••:::.:.:.:.:.:.:.••••••••:.......:..... ~:. .............................................................................. ~ ..............·N.......•...•...•...•...•••...•••••••.....•••...•••.....•••...•••...·.:.........•...•••••...:.:.....:.:.).:;:.:::;:.:.:,y..:.:.v~::::!;::::w.:.:.:;::x::;,;:::::::::::;~Example ABSI *-AR5(1),R5I I STI Rl, *AR2--(IR1)Before Instruction:AR5 = 8099E2hR5 =OhR1 = 42h = 66AR2 = 8098FFhIR1 = OFhData at 8099E1 h = OFFFFFFCBh = - 53Data at 8098FFh = 2h = 2LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR5 = 8099E2hR5 = 35h = 53R1 = 42h = 66AR2 = 8098FOhIR1 = OFhData at 8099E1 h = OFFFFFFCBh = - 53Data at 8098FFh = 42h = 66LUF LV UF N Z V C = 0 0 0 0 0 0 0. 10-25
ADDC AddSyntaxADDCsrc, dstOperationOperandsdst+ src+ C ~ dstsrc general addressing modes (G):o 0 register (Rn, 0 ::::; n ::::; 27)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0 ::::; n ::::; 27)31 2423 87i I i idstsrcDescriptionThe sum of the dst and src operands and the C (carry) flag is loaded into thedst register. The dst and src operands are assumed to be signed integers.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV 1 if an integer overflow occurs, unchanged otherwise.UF O.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if an integer overflow occurs, 0 otherwise.C 1 if a carry occurs, 0 otherwise.OVM Operation is affected by OVM bit value.RO.ExampleADDCRl,R5Before Instruction:R1 = 00FFFF5C25h = - 41 ,947R5 = 00FFFF019Eh = - 65,122LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R1 = 00FFFF5C25h = - 41 ,947R5 = 00FFFE5DC4h = - 107,068LUF LV UF N Z V C = 0 0 0 0 0 0 010-26 Assembly Language Instructions
SyntaxADDC3sre2, sret, dstOperationOperandssre t + sre2 + C --7 dstsret three-operand addressing modes (T):o 0 register (Rn1, 0 ~ n1 ~ 27)o 1 indirect (disp = 0, 1, IRO, IR1)1 0 register (Rn1, 0 ~ n1 ~ 27)1 1 indirect (disp = 0, 1, IRO, IR1)sre2 three-operand addressing modes (T):o 0 register (Rn2, 0 ~ n2 ~ 27)o 1 register (Rn2, 0 ~ n2 ~ 27)1 0 indirect (disp = 0, 1, IRO, IR1)1 1 indirect (disp = 0, 1, IRO, IR1)dst register (Rn, ° ~ n ~ 27)EncodingDescriptionI' , I ' , , , , Ii31 2423 16 15 87 0i i i i ii i i i,001,000000, T dst src1 src2IThe sum of the sret and sre20perands and the C (carry) flag is loaded into thedst register. The sret, sre2, and dst operands are assumed to be signed integers.IICyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV 1 if an integer. overflow occurs, unchanged otherwise.U 0.N 1 if a negative result is generated, ° otherwise.Z 1 if a zero result is generated, otherwise.V 1 if an integer overflow occurs, ° otherwise.C 1 if a carry occurs, ° otherwise.DVM Operation is affected by OVM bit value.RO.10-27
Example 1ADDe3orADDe3*ARS++(IRO),RS,R2RS,*ARS++(IRO),R2Before Instruction:AR5 = 809908hIRO = 10hR5 = 066h = 102R2 = OhData at 809908h = OFFFFFFCBh = - 53LUF LV UF N Z V C = 0 0 0 0 0 0 1After Instruction:AR5 = 809918hIRO = 10hR5 = 066h = 1 02R2 = 032h = 50Data at 809908h = OFFFFFFCBh = - 53LUF LV UF N Z V C = 0 0 0 0 0 0 1Example 2ADDe3R2, R7, ROBefore Instruction:R2 = 02BCh = 700R7 = OF82h = 3970RO= OhLUF LV UF N Z V C = 0 0 0 0 0 0After Instruction:R2 = 02BCh = 700H7 = OF82h = 3970RO = 0123Fh = 4671LUF LV UF N Z V C = 0 0 0 0 0 0 010-28Assembly Language Instructions
SyntaxOperationOperandsADDF src, dstdst + src ~ dstsrc general addressing modes (G):0 register (Rn, 0 ~ n ~ 7)o 1 direct1 0 indirect1 1 immediateEncodingdst register (Rn, 0 ~ n ~ 7)(\ 1 I 1 1 1 1241231000000011G87i' i isrcDescriptionThe sum of the dstand srcoperands is loaded into the dstregister. The dstandsrc operands are assumed to be floating-point numbers.CyclesStatus BitsMode BitExampleThese condition flags are modified only if the destination register is R7 -LUF 1 if a floating-point underflow occurs, unchanged otherwise.LV 1 if a floating-point overflow occurs, unchanged otherwise.UF 1 if a floating-point underflow occurs, 0 otherwise.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if an floating-point overflow occurs, 0 otherwise.C Unaffected.OVM Operation is not affected by OVM bit value.ADDF *AR4++(IR1) ,RSBefore Instruction:AR4 = 809800hIR1 = 12BhR5 = 0579800000h = 6.23750e+01Data at 809800h = 86B2800h = 4.7031250e + 02LUF LV UF N Z V C =0 0 0 00 0 0After Instruction:AR4 = 80992BhIR1 = 12BhR5 = 09052COOOOh = 5.3268750e+02Data at 809800h = 86B2800h = 4.7031250e + 02LUF LV UF N Z V C = 0 0 0 0 0 0 0RO.10-29
ADDF3 Add Floating-Point, 3-0perand~!;~s:;s~;:;:;:;~::.;:;:;s:;:;:;s::~~;o;:::;:>:::a:;::»:;:;:;:::::::::::::;:::: ::~:::;:>:::::;:::;,::::::;:;:.:.:;:;:;:~;:;:;:;:::;:::::,=;:;:::;::::9>:;')!;y';:«;:, :~«::::;. ... ..:.w~:::;s~;:>!;s~~::Y.O:;s:~:;.m~:::;:;S:::;9~~::::;:;S:;:;:::;O;:;:::::~:;S~~·;,;o,;y';:;';O;:::;~·:y';O:y":~~v.:::s.Y.~~~;S::y';OX:;~~~~~~~~:~:;:'~SyntaxADDF3src2, src1, dstOperationOperandssrc1 + src2 ~ dstsrc1 three-operand addressing modes (T):o 0 register (Rn1, 0 ::;; n1 ::;; 7)o 1 indirect (disp = 0, 1, IRO, IRi)1 0 register (Rn1, 0 ::;; n1 ::;; 7)1 1 indirect (disp = 0,1, IRO, IR1)src2 three-operand addressing modes (T):o 0 register (Rn2, 0 ::;; n2 ::;; 7)o 1 register (Rn2, 0 ::;; n2 ::;; 7)1 0 indirect (disp = 0, 1, IRO, IR1)1 1 indirect (disp = 0, 1, IRO, IR1)dst register (Rn, 0 ::;; n ::;; 7)EncodingDescriptionI31 2423 16 15 87 0i i i i i i ii i i iIii Iii iii IT dst src1 src2>0
Add Floating-Point, 3-0perandADDF3;:;:"~o;:;:;:;~;::::::~;::::::::::!::::::::::::;:;:::::::;!::::::::;!::;:::;!::::::::::::::::::::::::;:::::::::::::::::::::::::::;0:::::::::::::::;:;:::::::::;:;:;:::::::::::;.;::::*:::::::::::.;::::::::::::~;:;::::::::.;:;:;:::::::::::::::::::::::::::::::::::::::::::::::::::;:;-'::::::::::;:::::::;::.::;.::::::::::;:::;:;:;::::::»:::::::::::::;:::::;:;:::::::;:.:.:.·.·... :.~~·.·.:.·.·.:.·.·.:.·.:.:.:.:.·.:.::lo:.:~W.:... lo:.·.·.lo:.lolo:.:.::·.:.lo:::.:.:::.y.·.:.:.:.:.:.:.:. ..:.:.:.:.lo":·::lo:.:;:::.:.::::lo:::::;"::::::::::~:::::::':::::;*::::::::~~::::::~::.;:::..o;.:After Instruction:R6 = 0868280000h = 4.7031250e + 02R5 = 0579800000h = 6.23750e + 01R1 = 09052COOOOh = 5.3268750e + 02LUF LV UF N Z V C = 0 0 0 0 0 0 0Exampie2ADDF3*+ARl(l),*AR7++(IRO),R4Before Instruction:AR1 = 809820hAR7 = 8099FOhIRO = 8hR4= OhData at 809821 h = 700FOOOh = 1.28940e + 02Data at 8099FOh = 34C2000h = 1.27590e + 01LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR 1 = 809820hAR7 = 8099F8hIRO = 8hR4 = 070D820000h = 1.41695313e + 02Data at 809821 h = 700FOOOh = 1.28940e + 02Data at 8099FOh = 34C2000h = 1.27590e + 01LUF LV UF N Z V C = 0 0 0 0 0 0 o.10-31
SyntaxIIADDF3STFsrc2, src1, dst1src3, dst2Operationsrc1 + src2 -7 dst1II src3 -7 dst2OperandsEncodingsrc1src2dst1src3dst2register (Rn1, 0 :s; n1 :s; 7)indirect (disp = 0, 1, IRO, IR1)register (Rn2, 0 :s; n2 ::; 7)register (Rn3, 0::; n3 ::; 7)indirect (disp = 0, 1, IRO, IR1)i isrc11615i I I Isrc3I I I Idst2src2DescriptionA floating-point addition and a floating-point store are performed in parallel. <strong>Al</strong>lregisters are read at the beginning and loaded at the end of the execute cycle.This means that if one of the parallel operations (STF) reads from a registerand the operation being performed in parallel (ADDF3) writes to the same register,then STF accepts as input the contents of the register before it is modifiedby the ADDF3.If src2 and dst2 point to the same location, src2 is read before the write to dst2.CyclesStatus BitsThese condition flags are modified only if the destination register is R7 -LUF 1 if a floating-point underflow occurs, unchanged otherwise.LV 1 if a floating-point overflow occurs, unchanged otherwise.UF 1 if a floating-point underflow occurs, 0 otherwise.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if an floating-point overflow occurs, 0 otherwise.C Unaffected.RO.Mode BitExampleOVM Operation is not affected by OVM bit value.ADDF3 *+AR3(IR1),R2,R5I I STF R4,*AR210-32Assembly Language Instructions
Before Instruction:AR3 = 809800hIR1 = OAShR2 = 070C800000h = 1 AOSOe + 02RS = OhR4 = OS78400000h = 6.2812S0e + 01AR2 = 8098F3hData at 8098ASh = 733COOOh = 1.797S0e + 02Data at 8098F3h = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR3 = 809800hIR1 = OAShR2 = 070C800000h = 1 AOSOe+02RS = 0820200000h = 3.202S0e + 02R4 = OS7B400000h = 6.2812S0e + 01AR2 = 8098F3hData at 8098ASh = 733COOOh = 1.797S0e + 02Data at 8098F3h = S7B4000h = 6.2812Se + 01LUF LV UF N Z V C = 0 0 0 0 0 0 010-33
ADDI AddSyntaxOperationOperandsADDI src, dstdst + src --7 dstsrcgeneral addressing modes (G):0 register (Rn, 0 :::; n :::; 27)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0:::; n :::; 27)EncodingDescriptionIii Iii iii I31 2423 87i i000000100 GsrcThe sum of the dst and src operands is loaded into the the dst register. The dstand src operands are assumed to be signed integers.Status BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV 1 if an integer overflow occurs, unchanged otherwise.UF o.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if an integer overflow occurs, 0 otherwise.C 1 if a carry occurs, 0 otherwise.OVM Operation is affected by OVM bit value.RO.ExampleADDIR3,R7Before Instruction:R3 = OFFFFFFCBh = - 53R7 = 35h = 53LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R3 = OFFFFFFCBh = - 53R7 = OhLUF LV UF N Z V C = 0 0 0 0 0 0 010-34 Assembly Language Instructions
SyntaxOperationOperandsADDI3 ,,src t + sre2 ~ dstsret three-operand addressing modes (T):o 0 register (Rn1, 0::; n1 ::; 27)o 1 indirect (disp = 0, 1, IRO, IR1)1 0 register (Rn1, 0 ::; n1 ::; 27)1 1 indirect (disp = 0, 1, IRO, IR1)sre2 three-operand addressing modes (T):o 0 register (Rn2, 0 ::; n2 ::; 27)o 1 register (Rn2, 0 ::; n2 ::; 27)1 0 indirect (disp = 0, 1, IRO, IR1)1 1 indirect (disp = 0, 1, IRO, IR1)dst register (Rn, 0 ::; n ::; 27)Encoding31 2423Iii Iii iii Io 0 1 0 0 0 0 10 Tiii i isrc1src2DescriptionThe sum of the sret and sre20perands is loaded into the dstregister.The sret,sre2, and dst operands are assumed to be signed integers.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV 1 if an integer overflow occurs, unchanged otherwise.UF O.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if an integer overflow occurs, 0 otherwise.C 1 if a carry occurs, 0 otherwise.OVM Operation is affected by OVM bit value.RO.Example 1ADDI3R4,R7,R5Before Instruction:R4 = ODCh = 220R7 = OAOh = 160RS = 10h = 16LUF LV UF N Z V C = 0 0 0 0 0 0 010-35
ADDI3 Add Integer, 3-0perand~;:;!;!;:;:;!>:;:;:;:"O!;:::;:;:;:~;:;:::::::;:::~:;:;:::::;:;::-:::::~:::;::::::~;:;:::;::::::~:::.:.:;:::::;:::::::::::6~.::·::;·::::.·;·.·;::::y.s·.:.:.·;·;:: ...... ·N:O::::;::s:::::::::::::;:;:::;::::::::~::·::::::::::;::::::::::::~.:;::.;·:::ss~::::::::::;':::::::-:'::';'::-,,:';::0:.::.;:::;.;.::::::::::::::::.,;.;.:::.::;-:-:.::::-:.:.;.;::.::::::-~:::.: ••• ::;.;.:.:e;.:.:.;.,-.. :.;o;.:.:.;..:;.: ..... ; ••• ; •••• ..;.;.;.;.;.;.»:.;.;.;.;.;.;.;.;: .. ;.;.;.;.;: •• ;·h·;·;·;y;·:·.·.:::;·.·~;·.·.· .. :::·::;·:·:::·;o:·:·;:::;.::::::::;sss:::;~~:s::::~"!:s:;::::::s:;::s:;:;:;sAfter Instruction:R4 = ODCh = 220R7 = OAOh = 160R5 = 017Ch = 380LUF LV UF N Z V C = 0 0 0 0 0 0 0Example 2ADDI3*-AR3(1),*AR6--(IRO),R2Before Instruction:AR3 = 809802hAR6 = 809930hIRO = 18hR2 = 10h = 16Data at 809801 h = 2AF8h = 11,000Data at 809930h = 3A98h = 15,000LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR3 = 809802hAR6 = 809918hIRO = 18hR2 = 06598h = 26,000Data at 809801 h = 2AF8h = 11,000Data at 809930h = 3A98h = 15,000LUF LV UF N Z V C = 0 0 0 0 0 0 01 0-36 Assembly Language Instructions
SyntaxOperationOperandsIIADDI3STIsrc2, src1, dst1src3, dst2src1 + src2 --) dst1II src3 --) dst2src1 register (Rn1, 0 ~ n1 ~ 7)src2 indirect (disp = 0, 1, IRO, IR1)dst1 register (Rn2, 0 ~ n2 ~ 7)src3 register (Rn3, 0 ~ n3 ~ 7)dst2 indirect (disp = 0, 1, IRO, IR1)Encodingi i iiio 1 0 0 1 1 1 dstl src1 dst2iiisrc2DescriptionAn integer addition and an integer store are performed in parallel. <strong>Al</strong>l registersare read at the beginning and loaded at the end of the execute cycle. Thismeans that if one of the parallel operations (STI) reads from a register. and theoperation being performed in parallel (ADDI3) writes to the same register, thenSTI accepts as input the contents of the register before it is modified by theADDI3.If src2 and dst2 point to the same location, src2 is read before the write to dst2.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV 1 if an integer overflow occurs, unchanged otherwise.UF O.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero resuit is generated, 0 otherwise.V 1 if an integer overflow occurs, 0 otherwise.C 1 if a carry occurs, 0 otherwise.OVM Operation is affected by OVM bit value.RO.10-37
ADDI311STI Parallel ADDI3 and STI;.;.;.;.; •••••••••• :; •••• :.:::::::;.; ••• -:;:.::: •• ;: •••• ;.;:::::::::::::::::::::::::::::::::::::::::;:::;::::::::::::::::: •• ;.;:.:;::.::;: ••••••• :; ••••• ;.; ...... :;0 •• ; ••• ; •• :; ••••• ; •••••••• :.:; ••••••••••••••••• ;.;0;:::::::.:::::;:::::;-.:;:;.;.;.;.;.;.;:;:;.;.; ••• ;0; ••••• ;.:::';';',-;';';';';';';';';';-;0;';';';:;';';'::;';';';';';.;.;.;.;.;.;.;.;.;.;.;.;0;.; ••••• ; ••••• ; ••• ;.;.;0. ..... ;.; ••• ; ••••• ;.; ......... :.; ••••• ; ••• ; ••••• ;.;0 .... ;.; ..... ;.;.;.;.;.;0; ••• ;0;.;.;0; ••• ; ... ;.; ••••• ; ••• ;.;.;.; ••• ; ••••• ;';';0;',';"':',';';';';'.';';0;';';:;',';';';';';-;0::';:;'::;0::';:;::';';';';:;:;:;:;';:;:;:.:::;:;:;:;::Example ADDI3 *ARO--(IRO),R5,ROII ' STI R3,*AR7Before Instruction:ARO = 80992ChIRO = OChR5 = ODCh = 220RO = OhR3 = 35h = 53AR7 = 80983BhData at 80992Ch = 12Ch = 300Data at 80983Bh = OhLUF LV UF N Z V C = 0 0 0 0 0, 0 0After Instruction:ARO = 809920hIRO = OChR5 = ODCh = 220RO = 208h = 520R3 = 35h = 53AR7 = 80983BhData at 80992Ch = 12Ch = 300Data at 80983Bh = 35h = 53LUF LV UF N Z V C = 0 0 0 0 0 0 010-38 Assembly Language Instructions
BitwiseANDSyntaxOperandsOperandsAND src, dstdst AND src ~ dstsrc general addressing modes (G):00 register (Rn, 0 $ n $ 27)o 1 direct1 0 indirect1 1 immediate (not sign-extended)dst register (Rn, 0 $ n $ 27)EncodingDescriptionI I I i I I I I I ii i iI31 2423 1615 87 0i i i i>0
SyntaxIIANDSTIsre2, sre1, dst1sre3, dst2Operationsret AND sre2 ~ dst1II sre3 ~ dst2OperandsEncodingsretsre2dst1sre3dst2register (Rn1, 0 ~ n1 ~ 7)indirect (disp = 0, 1, IRO, IR1)register (Rn2, 0 ~ n2 ~ 7)register (Rn3, 0 ~ n3 ~ 7)indirect (disp = 0, 1, IRO, IR1)I Isrc1I Idst2I I Isrc2DescriptionA bitwise logical-AND and an integer store are performed in parallel. <strong>Al</strong>l registersare read at the beginning and loaded at the end of the execute cycle. Thismeans that if one of the parallel operations (STI) reads from a register and theoperation being performed in parallel (AND3) writes to the same register, thenSTI accepts as input the contents of the register before it is modified by theAND3.If sre2and dst2point to the same location, sre2is read before the write to dst2.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV Unaffected.UF O.N MSB of the output.Z 1 if a zero result is generated, 0 otherwise.V O.C Unaffected.OVM Operation is not affected by OVM bit value.RO.10-42Assembly Language Instructions
Example AND3 *+ARl (IRQ) , R4, R7I I STI R3,*AR2Before Instruction:AR1 = 8099F1 hIRO = 8hR4 = OA323hR7 =OhR3 = 35h = 53AR2 = 80983FhData at 8099F9h = 5C53hData at 80983Fh = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR1 = 8099F1 hRO =8hR4 = OA323hR7 = 03hR3 = 35h = 53AR2 = 80983FhData at 8099F9h = 5C53hData at 80983Fh = 35h = 53LUF LV UF N Z V C = 0 0 0 0 0 0 010-43
SyntaxOperationOperandsANDN src, dstdst AND -src -7 dstsrc general addressing modes (G):o 0 register (Rn, 0 :::; n :::; 27)o 1 direct1 0 indirect1 1 immediate (not sign-extended)dst register (Rn, 0 :::; n :::; 27)Encoding13\ , 1 ' , , , 24,23187i . i i idstsrcDescriptionThe bitwise logical-AND between the dstoperand and the bitwise logical complement(-) of the src operand is loaded into the dst register. The dst and srcoperands are assumed to be unsigned integers.CyclesStatus BitsMode BitExampleThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV Unaffected.UF o.N MSB of the output.Z 1 if a zero result is generated, 0 otherwise.V O.C Unaffected.DVM Operation is not affected by OVM bit value.ANDN @980Ch,R2Before Instruction:DP = 80hR2 = OC2FhData at 80980Ch = OA02hLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:DP = 80hR2 = 042DhData at 80980Ch = OA02hLUF LV UF N Z V C = 0 0 0 0 0 0 0RO.10-44Assembly Language Instructions
SyntaxOperationOperandsANDN3 src2, src1, dstsrc 1 AN D -src2 --7 dstsrc1 three-operand addressing modes (T):o 0 register (Rn1 , O·~ n1 ~ 27)o 1 indirect (disp = 0, 1, IRO, IR1)1 0 register (Rn1 , 0 ~ n1 ~ 27)1 1 indirect (disp = 0, 1, IRO, IR1)src2 three-operand addressing modes (T):o 0 register (Rn2, 0 ~ n2 ~ 27)o 1 register (Rn2, 0 ~ n2 ~ 27)1 0 indirect (disp = 0, 1, IRO, IR1)1 1 indirect (disp = 0, 1,100, IR1)dst register (Rn, 0 ~ n ~ 27)Encodingidstiiiisrc1iiisrc2DescriptionThe bitwise logical-AND between the src1 operand and the bitwise logicalcomplement (-) of the src2 operand is loaded into the dst register. The src1,src2, and dst operands are assumed to be unsigned integers.CyclesStatus BitsMode BitExample 1These condition flags are modified only if the destination register is R7 -LUF Unaffected. .LV Unaffected.UF O.N MSB of the output.Z 1 if a zero result is generated, 0 otherwise.V O.C Unaffected.OVM Operation is not affected by OVM bit value.ANDN3 R5,R3,R7Before Instruction:R5 = OA02hR3 = OC2FhR7 = OhLUF LV UF N Z V C = 0 . 0 0 0 0 0 0RO.10-45
ANON3 Bitwise Logical-ANDN, 3-0perand;c;:;..:::::.:::::.:::::~:!~~;.:;-;.»m~;:;x:;::c;:::::;:;::>-;~:
ASH Arithmetic ShiftStatus BitsMode BitExample 1These condition flags are modified only if the destination register is R7 - RO.LUF Unaffected.LV 1 if an integer overflow occurs, unchanged otherwise.UF O.N MSB of the output.Z 1 if a zero result is generated, 0 otherwise.V 1 if an integer overflow occurs, 0 otherwise.C Set to the value of the last bit shifted out. 0 for a shift count of o.OVM Operation is not affected by OVM bit value.ASH Rl,R3Before Instruction:R1 = 10h = 16R3 = OAEOOOhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R1 = 10hR3 = OEOOOOOOOhLUF LV UF N Z V C = 0 o 1 010Example 2ASH @98C3h,R5Before Instruction:DP = 80hR5 = OAEC00001 hData at 8098C3h = OFFE8 = - 24LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:DP = 80hR5 = OFFFFFFAEhData at 8098C3h = OFFE8 = - 24LUF LV UF N Z V C = 0 0 0 1 0 0 110-48Assembly Language Instructions
ArithmeticASH3SyntaxOperationASH3 count, src, dstIf (count ~ 0):src « count ~ dstElse:src» I count I ~ dstOperandscount three-operand addressing modes (T):o 0 register (Rn2, 0 ~ n2 ~ 27)o 1 register (Rn2, 0 ~ n2 ~ 27)1 0 indirect (disp = 0, 1, IRa, IR1)1 1 indirect (disp = 0, 1, IRa, IR1)src three-operand addressing modes (T):o 0 register (Rn1, 0 ~ n1 :5 27)a 1 indirect (disp = 0, 1, IRa, IR1)1 0 register (Rn1, 0 ~ n1 ~ 27)1 1 indirect (disp = 0, 1, IRO, IR1)dst register (Rn, 0 ~ n ~ 27)EncodingDescriptionI i i i I i i i i i I312423 16 1587 0i i iIii, Iii iii I,001,000101, T dst src countThe seven least significant bits of the count operand are used to generate thetwos-complement shift count of up to 32 bits.If the count operand is greater than zero, the src operand is left-shifted by thevalue of the count operand. Low-order bits shifted in are zero-filled, and highorderbits are shifted out through the status register's C (carry) bit. 'Arithmetic left-shift:C ~ src~ 0If the count operand is less than zero, the src operand is right-shifted by the -absolute value of the countoperand. The high-order bits of the srcoperand aresign-extended as they are right-shifted. Low-order bits are shifted out throughthe C (carry) bit.Arithmetic right-shift:sign of src ~ src ~ CIf the count operand is zero, no shift is performed, and the C (carry) bit is setto O. The count, src, and dst operands are assumed to be signed integers.10-49
CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV 1 if an integer overflow occurs, unchanged otherwise.UF O.N MSB of the output.Z 1 if a zero result is generated, 0 otherwise.V 1 if an integer overflow occurs, 0 otherwise.C Set to the value of the last bit shifted out. 0 for a shift count of O.OVM Operation is not affected by OVM bit value.RO.ExampleASH3*AR3--(1),R5,ROBefore Instruction:AR3 = 809921 hR5 = 02BOhRO = OhData at 809921h = 10h = 16LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR3 = 809920hR5 = 000002BOhRO = 02BOOOOOhData at 809921h = 10h = 16LUF LV UF N Z V C = 0 0 0 0 0 0 0ExampleASH3 R1,R3,R5Before Instruction:R 1 = OFFFFFFF8h = - 8R3 = OFFFFCBOOhR5 = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R 1 = OFFFFFFF8h = - 8R3 = OFFFFCBOOhR5 = OFFFFFFCBhLUF LV UF N Z V C = 0 0 0 1 0 0 010-50Assembly Language Instructions
SyntaxOperationASH3 count, src2, dst1II STI src3, dst2If (count;;:: 0):src2 « count ---7 dst1Else:src2» Icoun~ ---7 dst1IIsrc3 ---7 dst2Operandscount register (Rn1, ° ~ n1 ~ 7)src2 indirect (disp = 0, 1, IRO, IR1)dst1 register (Rn2, ~ n2 ~ 7)src3 register (Rn3, ° ~ n3 ~ 7)dst2 indirect (disp = 0, 1, IRO, IR1)Encodingi icounti idst2iiisrc2DescriptionThe seven least significant bits of the countoperand register are used to generatethe twos-complement shift count of up to 32 bits.If the count operand is greater than zero, the dstoperand is left-shifted by thevalue of the count operand. Low-order bits shifted in are zero-filled, and highorderbits are shifted out through the C (carry) bit.Arithmetic left-shift:C~src2~0If the count operand is less than zero, the dst operand is right-shifted by theabsolute value of the countoperand. The high-order bits of the dstoperand aresign-extended as it is right-shifted. Low-order bits are shifted out through theC (carry) bit.Arithmetic right-shift:sign of src2 ---7 src2 ---7 CIf the count operand is zero, no shift is performed, and the C (carry) bit is setto 0. The count and dst operands are assumed to be signed integers.<strong>Al</strong>l registers are read at the beginning and loaded at the end of the executecycle. This means that if one of the parallel operations (STI) reads from a registerand the operation being performed in parallel (ASH3) writes to the sameregister, then STI accepts as input the contents of the register before it is modifiedby the ASH3.10-51
If src2 and dst2point to the same location, src2is read before the write to dst2.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 - RO.LUF Unaffected.LV 1 if an integer overflow occurs, unchanged otherwise.UF o.N MSB of the output.Z 1 if a zero result is generated, 0 otherwise.V 1 if an integer overflow occurs, 0 otherwise.C Set to the value of the last bit shifted out. 0 for a shift count of O.OVM Operation is not affected by OVM bit value.ExampleASH3I I STIRl,*AR6++(IR1),ROR5,*AR2Before Instruction:AR6 = 809900hIR1 = 8ChR1 = OFFE8h = - 24RO = Oh .R5 = 35h = 53AR2 = 8098A2hData at 809900h = OAEOOOOOOhData at 8098A2h = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR6 = 80998ChIR1 = 8ChR1 = OFFE8h = - 24RO = OFFFFFFAEhR5 = 35h = 53AR2 = 809'8A2hData at 809900h =OAEOOOOOOhData at 8098A2h = 35h = 53LUF LV UF N Z V C = 0 0 0 1 0 0 01 0-52 Assembly Language Instructions
Branch Conditionally (Standard)Bcond::::::;:::::::::::::::;;;:::::;:::::::;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;::::::::::::::S:::::::;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::%:::::::::::::::::::::::::.:::::::::::::::::::::::;:::::::::::::.:::::.:.:.: •••:;:.'•••:•••••••:;:::.:.:::.:.:::::.:.:.::::::'.:.:.:.:.:.:.'::.:;:::::;'.:.:.:.,.:.:.:::::::.:.:.:::::::::::.:::::::;:::::::;:::::::::;:::::::::::.:;:;:~::;:::;:;:;:::::::;:;:::::::::::::;:;:;:::::::::::::::;'0;:::::SyntaxOperationOperandsBcond srcIf cond is true:If src is in register addressing mode (Rn, 0 ~ n ~ 27),src --7 PC.If src is in PC-relative mode (label or address),displacement + PC + 1 --7 PC.Else, continue.src conditional-branch addressing modes (B):o register1 PC-relativeEncodingDescriptionBcondsignifies a standard branch that executes in four cycles. A branch is performedif the condition is true (since a pipeline flush also occurs on a true condition;see Section 9.2 on page 9-4). If the src operand is expressed in registeraddressing mode, the contents of the specified register are loaded into the PC.If the src operand is expressed in PC-relative mode, the assembler generatesa displacement: displacement = label- (PC of branch instruction + 1). This displacementis stored as a 16-bit signed integer in the 16 least significant bits ofthe branch instruction word. This displacement is added to the PC of the branchinstruction plus 1 to generate the new PC.The TMS320C3x provides 20 condition codes that can be used with this instruction(see Section 10.2 on page1 0-9 for a list of condition mnemonics, encoding,and flags). Condition flags are set on a previous instruction only whenthe destination register is one of the extended-precision registers (R7-RO) orwhen one of the compare instructions (CMPF, CMPF3, CMPI, CMPI3, TSTB,or TSTB3) is executed.CyclesStatus BitsMode Bit4LUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM bit value.10-53
Bcond Branch Conditionally (Standard)~s.:~~·".I.~/';'.I';:'~;O».l. ...'.lo'.~y.l.i/.i;:;:~~~$'''''h~:':-I.~::'~,i.::-,:$'':::%:;::~.:::::;::::.:,;!.:;:;:;:;:-»:.~.:;:.y,.:.::y.-=;:.:I..:.:.:.:.:.:.:.~'::.:.:.:.:.!-:.:.:~:...:.:.:.:.:.:;:.::!>!.:.:U.·.:I..:.!.·',::::~.:::::::;:::::;:&:::::::::::y.::::::ih:::::::::;·:::::·::::::::;:::::::::••:::~:::::;:;:;.::;::::.:::.:::.:::.::;:;•••;:;:::;:;:;';';';';':::::::'::::;';';';';';••:.'.:";'..;:;.;.;.,.::••;••••:•.;.;.;.;••:;.;.;•••••;:;..:::.;.;::.;-:.;0;.;:;.;••• ;.::;::.:::.:::.:.~:.;~.:.;.;.;.;.;.;.;.::~;:;:::::::;:::::;:;:::::::;:::;::::.::::::::~:::;:::::::::;::::ExampleBZ ROBefore Instruction:pc= 2BOOhRO = 0003FFOOhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:PC = 3FFOOhRO = 0003FFOOhLUF LV UF N Z V C = 0 0 O' 0 0 0 010-54 Assembly Language Instructions
Branch Conditionally (Delayed)BcondD';:;:':;:::;:::::::::::::::;:::;:::;:::::;:.:::;:::;:::::::;:;:;:::::;:::;:;:::;:::;:.:;:::::::::;:::::::::::;:::;:::::0:;:.:::::::;:;'::;';:;'::::::::::::::::::::;:;:::;:.:::::;:;:;';';'::::;'.:;:::;'.:.:;:::::.',:.:;';::';''';'''::'';',';••:;.;.;:;......:.:;:.:........;.;::::.;.;.;.;:;.••;.;:;:.........:;.;•••;:••;..:••;:.:;•••;••••:::;••:;...:....::;.;.;:.:••••••••••;............................:......................:............................................................................................... ~ .... ~ ..... ~y.:.~~:.:; ... :4:.:.:.:O:;:.,;,;:;:.:O,;:;:,6:.:;=-:.,;:~:>s,;s:.,;::::SyntaxOperationOperandsBcondD srcIf cond is true:If src is in register addressing mode (Rn, 0 ~ n ~ 27),src~ PC.If src is in PC-relative mode (label or address),displacement + PC + 3 ~ PC.Else, continue.src conditional-branch addressing modes (B):o register1 PC-relativeEncodingDescriptionBcond 0 signifies a delayed branch that allows the three instructions after thedelayed branch to be fetched before the PC is modified. The effect is a singlecyclebranch, and the three instructions following Bcond 0 will not affect thecondoA branch is performed if the condition is true. If the src operand is expressedin register addressing mode, the contents of the specified register are loadedinto the PC. If the srcoperand is expressed in PC-relative mode, the assemblergenerates a displacement: displacement = label- (PC of branch instruction +3). This displacement is stored as a 16-bit signed integer in the 16 least significantbits of the branch instruction. This displacement is added to the PC of thebranch instruction plus 3 to generate the new PC. The TMS320C3x provides20 condition codes that can be used with this instruction (see Section 10.2 onpage 10-9 for a list of condition mnemonics, encoding, and flags). Conditionflags are set on a previous instruction only when the destination register is oneof the extended-precision registers (R7-RO) or when one of the compare instructions(CMPF, CMPF3, CMPI, CMPI3, TSTB, or TSTB3) is executed.CyclesStatus BitsMode BitLUF Unaffected.LV Unaffected.UF Unaffected.N Unaffected.Z Unaffected.V Unaffected.C Unaffected._OVM Operation is not affected by OVM bit value.10-55
Example BNZD 36 (36 = 24h)Before Instruction:PC = 50hLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:PC = 77hLUF LV UF N Z V C = 0 0 0 0 a 0 010-56 Assembly Language Instructions
SyntaxOperationOperandsEncodingDescriptionCyclesStatus BitsMode BitExampleBR srcsrc~ PCsrc long-immediate addressing mode16 15 87 oiii i i i isrcISR signifies a standard branch that executes in four cycles, since a pipelineflush also occurs upon execution of the branch; see Section 9.2. An unconditionalbranch is performed. The srcoperand is assumed to be a 24-bit unsignedinteger. Note that bit 24 = 0 for a standard branch.4LUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM bit value.BR 80SChIBefore Instruction:PC = 80hLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:PC = 805ChLUF LV UF N Z V C = 0 0 0 0 0 0 010-57
BRD Branch Unconditionally (Delayed);O;:'~;~;!;:;';!;';';!;!;'::;":"':;:;:;:;:;:;:~;:;:::;:;:::;:~;:;:;:;:;:;:::::::::::::::;:::;:;:;.;.;.;.;.;:;:::;:;:::;';';:::::;:;:;:,';';:;:;';';:.';';:.';';:;:.'.:.:;.;:;:;•••;:;.;••••:;•••••;.;...;••:•••••••:;.:::.;:.:•••:;.;.;.;.;.;:;.;.;::.;.::::::::.,;.;.;.;".;.;.;.;';::'::;';::'::;:;';';';';';-;';';';0;';';';';';';';';';';';';';';';';';';';';';';';';';';';';';';';',.;-;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.;:;:;.;.;.;.;.;.,.;.;".;.;.;.;.,.;.,.;.;.;.;.;.;.;•••;•••••;.;.;.;.;.;.;.;.;.;.;•• :;.::::;.;.;.:::.;.;.;0.;.;.;.;:;:;.::;:;:;:::;::::::~::::;:::;:;:;:;:;:::;:;:;:;::SyntaxOperationOperandsBRD srcsrC--7 PCsrc long-immediate addressing modeEncodingo 1 1 0 0 0 0: 116 15 87iii i i i isrcDescriptionBRD signifies a delayed branch that allows the three instructions after thedelayed branch to be fetched before the PC is modified. The effect is asingle-cycle branch.An unconditional branch is performed. The src operand is assumed to be a24-bit unsigned integer. Note that bit 24 = 1 for a delayed branch.CyclesStatus BitsMode BitExampleLUF Unaffected.LV Unaffected.UF Unaffected.N Unaffected.Z Unaffected.V Unaffected.C Unaffected.OVM Operation is not affected by OVM bit value.BRD 2ChBefore Instruction:PC = 1 BhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:PC = 2ChLUF LV UF N Z V C = 0 0 0 0 0 0 010-58Assembly Language Instructions
Call SubroutineCALLSyntaxOperationOperandsCALL srcNext PC ~ * ++SPsrc~ PCsrc long-immediate addressing modeEncoding011000101615j j j87j j j j.srcDescriptionCyclesStatus BitsMode~itExampleA call is performed. The next PC value is pushed onto the system stack. Thesrc operand is loaded into the PC. The src operand is assumed to be a 24-bitunsigned immediate operand.4LUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM bit value.CALL 123456hBefore Instruction:PC=5hSP = 809801 hLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:PC = 123456hSP = 809802hData at 809802h = 6hLUF LV UF N Z V C = 0 0 0 0 0 0 010-59
Call Subroutine ConditionallyCALLcond;:::;:::::;:::,;:::::;:;:;:;:::;:;:;:::::::::::;:;:::::::::::::::::::::::::::::::;:::;:::::::::.::::::::::::::::::;;%:::::::::::::::::::::::::::::::;:::::::::::::;:;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;;%::::::::::::::::::::::::::::::::::::::::::;;:::::::::::;:::::::::::::.:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;.;:; ••:;••••••:::;.;.;:;••••:•••:::.:::;.;.;y••••;:::.:.:.::'•••••:::::•.;.;:••;••:.::.;:•••:••;••:::.:•.;:.....:;.;:;.;:.:;.;.;:::::;:.:.:;:;:;::•• :.:;:;:::;:::;:~:;:::;:::;:;:;::::::-.:::::::::::::%::;;:;::::::;::::::::::::::.::::::::::::;:;:ExampleCALLNZ R5Before Instruction:PC = 123hSP = 809835hR5 = 789hLUF LV UF N Z V C = 0 0 0 0 0 0 0. After Instruction:PC = 789hSP = 809836hR5 = 789hData at 809836h = 124hLUF LV UF N Z V C = 0 0 0 0 0 0 010-61
SyntaxOperationOperandsCMPF3 sre2, sre1sre1-sre2sre1 three-operand addressing modes (T):o 0 register (Rn1, 0 :::; n1 :::; 7)o 1 indirect (disp = 0, 1, IRO, IR1)1 0 register (Rn1, 0 :::; n1 :::; 7)1 1 indirect (disp = 0, 1, IRO, IR1)sre2three-operand addressing modes (T):o 0 register (Rn2, 0 :::; n2 :::; 7)o 1 register (Rn2, 0:::; n2 :::; 7)1 0 indirect (disp = 0, 1, IRO, IR1)1 1 indirect (disp = 0, 1, IRO, IR1)Encoding31 2423 16 15I I I I 1 1 1 1 1 1 1 T 01 0 1 0 10 10 I I001000110. .1 1 1 1 1 1src1src2DescriptionThe sre20perand is subtracted from the sre1 operand. The result is not loadedinto any register, thus allowing for nondestructive compares. The sre1 and sre2operands are assumed to be floating-point numbers. <strong>Al</strong>though this instructionhas only two operands, it is designated as a three-operand instruction becauseoperands are specified in the three-operand format.CyclesStatus BitsMode BitThese condition flags are modified for all destination registers (R27 -LUF 1 if a floating-point underflow occurs, unchanged otherwise.LV 1 if a floating-point overflow occurs, unchanged otherwise.UF 1 if a floating-point underflow occurs, 0 otherwise.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if a floating-point overflow occurs, 0 otherwise ..C Unaffected.OVM Operation is not affected by OVM bit value.RO).10-63
CMPF3 Compare Floating-Point, 3-0perand;:;:;o;:;:;:;:>:;:;:.:;:~;:;:;:;:;:;:;:;::~:::::?;:;:;:::;.:::::::::::::::::::;:;:::::::;:.:;::::::::::::~:;:;:;:;:;:.:::;:::::::::':;:~;:;:':;'''':;';'::':':'';:~''''::;:'';O':'':'':':;:::;:;·;:;·::.:..;·;:6:::,0:::.·.:.:.:.·::::;0;0.·.·.....•.......·;0;·;.;:;';:::::;';::':';:;0;';';';'::;';';';';';';'.:;';:;-;';:;0;:::::;';::';';';';';0;-:,,:::;';0::::;';';';';0;'::;';':'::;0;';0;';';0;';0;';0;';';';';';0;0;0;';0;';0;';';';';0;0;';';';0;0;-;0;';';';,;,;::,:,,';';';0;:::;';';';';0;0;0;';';';::::::';0::;';0;0;..';':';';';0;';';'::::;';-::;:;:::::::::::::::;0;
SyntaxOperationOperandsCMPI src, dstdst-srcsrc general addressing modes (G):0 register (Rn, 0 ::; n ::; 27)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0 ::; n ::; 27)Encoding, 311 1 , 1 1 1 124 1 23 ,000001001 G871 1 1 1dstsrcDescriptionThe src operand is subtracted from the dst operand. The result is not loadedinto any register, thus allowing for nondestructive compares. The dst and srcoperands are assumed to be signed integers.CyclesStatus BitsMode BitExampleThese condition flags are modified for all destination registers (R27 -LUF Unaffected.LV 1 if an integer overflow occurs, unchanged otherwise.UF o.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if an integer overflow occurs, 0 otherwise.C 1 if a borrow occurs, 0 otherwise.OVM Operation is not affected by OVM bit value.CMPI R3,R7Before Instruction:R3 = 898h = 2200R7 = 3E8h = 1000LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R3 = 898h = 2200R7 = 3E8h = 1000LUF LV UF N Z V C = 0 0 0 1 0 0 0RO).10-65
Compare Integer, 3-0perandCMPI3::;:;:;:;:;:;:::;:::;:::;:;::;::;:::::;:;:::;:;:;:::;.::::::;:::;:;.; :.;.;.;:;.;:::;.::;:::;:;.::.:;:.:••;••:;.,.;.;.,.;.;.;:;:::::;';';';';';';';';';0;';';:;',';'0';';';-;';';';:;:::::::::;:;,;",;:;,;,.:.,;,;.;.;.;.;.,.;.,.;.;.,.;.;.;.;•••••••;.;0;.;.;.;.;.;.;•••••••;.;•••••••;.;.;.;.;.;.;.;.;•••••;.;.;.;.;•••;.;.;.;.;.;.;.;:;.;.;.;.;•••;.;.;.;.;.;.;•••;•••••;•••;.;•••••••••••••••••••••••••••••••••••••••••••••••••••••••••,••••••••••••••••••••••••••••••••••••'•••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••:;:.:;.;:;:::.:::::::;:::::::::.:;';:.:,';:.:.:;:.:.:;:.:;:.:;:::Example CMPI3 R7,R4Before Instruction:R7 = 03E8h = 1000R4 = 0898h = 2200LUF LV UF N Z V C = a a 0 a 0 a aAfter Instruction:R7 = 03E8h = 1000R4 = 0898h = 2200LUF LV UF N Z V C = a a a 0 a a 010-67
Decrement and Branch Conditionally (Standard)DBcond~;~;.::;:;:;~;:;:;:;:::;:;:;:;:;:;:;:;:::;:::;:;:;:;:;:;:;:;:;:;:;:;:::;:;:;:;:;:;:;:;:':;:;:;':::::::';';'~::;';';.;.;.:.,.;:;:;.;:;.;::.;.;.;.;::.;:;.;:;.;:;.;.;.;.;.;';';::';0;:::::::;:::::::::;':';';':':';';';';';'::;';';.;.;:;::.;.; ••• ;::.;.;.;: •• ;.;::: •••• ; ......................................................................................................................................................................................................................................................................; ....... ;:..;.,;.;.;o;.; •• -;:.: •• ; •• :.:::~::::::;: •• ::;:;:;:;:::::.: •• ;:";:::;'::;:0:CyclesStatus BitsMode BitExample4LUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM bit value.CMPI 200,R3DBLT AR3,R2Before Instruction:PC = 5FhAR3 = 12hR2 = 9FhR3 = BOhLUF LV UF N Z V C = 0 0 0 1 0 0 0After Instruction:PC = 9FhAR3 = 11hR2 = 9FhR3 = BOhLUF LV UF N Z V C = 0 0 0 1 0 0 010-69
DBcondD Decrement and Branch Conditionally (Delayed)~~:;:;:;:;:;!;!;!~;!;!~s:;!;-;:;!;%!:!:::::::::::::::::::::.-;:::::::::::::::::;:::::::::::::~:::;:;:.::;::::::.=::::::.:::::::::.:::::::.:.:::.:.:.:.:.:.:.:::::::::.:::.:.:.:.:.:.:::.:::::::.:::::::::.:.:.:;:::::::::::::.:;:::.:::.:.:;:;:;:.:.:::b:.:.:.:.:.~.:.:.:.:.:.:.:.::,:.:.'::.:.:.:.:.:.:::.:.'.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:::.:;';:;'.::::'::::::::::::::::::::::::::::::::::::::::::::':::: •• ;.;:;.:.;:::;::.::::.:.;::::.::.:::::.;.:::::::.:::.;.;.;::.;-;:;.;.;.;:::;... :::.;:;.: •• :~.:: ••• ::;::::.:.;.::: .. "·;·;:::;:::;::::::.:;:::::;..;.::::~:;::%::::::::::::::::::::::::.o;::sx::~%~SyntaxOperationDBcondD ARn, srcARn -1 -7 ARnIf cond is true and ARN ~ 0:If src is in register addressing mode (Rn, 0 ~ n ~ 27)srC-7 PCIf src is in PC-relative mode (label or address)displacement + PC + 3 -7 PC.Else, continue.Operandssrc conditional-branch addressing modes (B):O' register1 PC-relativeARn register (0 ::; n ::; 7)EncodingDescriptionDBcond 0 signifies a delayed branch that allows the three instructions afterthedelayed branch to be fetched before the PC is modified, The effect is a singlecyclebranch. The specified auxiliary register is decremented and a branch ispeiiormed if the condition is true and the specified auxiliary register is greaterthan or equal to zero. The condition flags are those set by the last previous instructionthat affects the status bits. The three instructions following theDBcondD do not affect the condoThe auxiliary register is treated as a 24-bit signed integer. The most significanteight bits are unmodified by the decrement operation. The comparison of theauxiliary register uses only the 24 least significant bits of the auxiliary register.Note that the branch condition does not depend on the auxiliary register decrement.If the src operand is expressed in register addressing mode, the contents ofthe specified register are loaded into the PC. If the src is expressed in PC-relativeaddressing, the assembler generates a displacement: displacement = label-(PC of branch instruction + 3). This displacement is added to the PC ofthe branch instruction plus 3 to generate the new PC. Note that bit 21 = 1 fora delayed branch. .The TMS320C3x provides 20 condition codes that can be used with this instruction(see Section 10.2 for a list of condition mnemonics, encoding, andflags). Condition flags are set on a previous instruction only when the destinationregister is one of the extended-precision registers,(R7-RO) or when one10-70Assembly Language Instructions
FIX Floating-Point to Integer Conversion;:;:~;:;:;:;:.:;:;.:;:::;:::;:;:;:;:;:::;:;:-:;:>:::.:;::~:;:::;:;:;:;.:;:;:.:.:;:;:;:.:;:::::;:;:;:::::::;:;:;:::;:::;:;:;:.:;:;:;:;:;:;:;:-:;:.: ••••••• : ••• :.:.:.:.:;:~;:;:.:.:.:.:.:.:.:;:-:.~:;y ••• :~;:.:;:-:.:::;:>:.=-:;:; •• :.:;:-:;.;. t.;:;:;:;:;:;:;:;.:;::.::;:;~:;:;:;::.;:;:;:;:;:;:;:;:;:;:;:::::::::;:;';:;:::;';';:;0;:;';:;:;::,;::::::,;,;,;,;::.;:::::;:;:;.;.;:;:::;.;:;.;:::;:;.;:;.:.;:::;:;::::::';0;0.::::.;.;.;:;.;.;.;.;:;.;.;.;.;:;.;:;::::.;::::: •• ::;:;0;::.::;:::;.;.;:::::;0;:;:;::0: •••• ;:::;.;.:.;.::::;.;.;:;:;.;:;.;.;::.;.;.;:.:;:;.;:::;.;:;:;:::;:::;:::~;:;:;:;:;:;:;:::;:::::::::;0:;0:;:;:;SyntaxOperationOperandsFIX src, dstfix(src) ~ dstsrc general addressing modes (G):0 register (Rn, 0 ~ n ~ 7)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0 ~ n ~ 27)Encoding3111 1 1 1 1 1241231000001010 G11 1dst871 1srcDescriptionThe floating-point operand src is converted to the nearest integer less than orequal to it in value, and the result is loaded into the dstregister. The srcoperandis assumed to be a floating-point number and the dstoperand a signed integer.The exponent field of the result register (if it has one) is not modified.Integer overflow occurs when the floating-point number is too large to be representedas a 32-bit twos-complement integer. In the case of integer overflow,the result will be saturated in the direction of overflow.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV 1 if an integer overflow occurs, unchanged otherwise.UF O.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if an integer overflow occurs, 0 otherwise.C Unaffected.OVM Operation is not affected by OVM bit value.RO.10-72Assembly Language Instructions
Floating-Point to Integer Conversion::::;:;:;::::':;:::::::;::%:;:::"«;:::::::::::'::~;:::¢:::::::'::::::;:;:::;:::;:::::'::::
ExampleFIXII STI* + + AR 4 (1) , P,lRO,*AR2Before Instruction:AR4 = 8098A2hR1 = OhRO = ODCh = 220AR2 = 80983ChData at 8098A3h = 733COOOh = 1 .7950e + 02Data at 80983Ch = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR4 = 8098A3hR1 =OB3h=179RO = OOCh = 220AR2 = 80983ChData at 8098A3h = 733COOOh = 1.79750e + 02Data at 80983Ch = OOCh = 220LUF LV UF N Z V C = 0 0 0 0 0 0 010-75
SyntaxOperationOperandsFLOAT src, dstfloat (src) --7 dstsrcgeneral addressing modes (G):0 register (Rn, 0 ~ n ~ 27)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0 ~ n ~ 7)Encoding\31 1 24 231 \ 1 1 1 1 1 \000001011 G871 1srcDescriptionThe integer operand src is converted to the floating-point value equal to it, andthe result loaded into the dst register. The src operand is assumed to be asigned integer, and the dst operand a floating-point number.CyclesStatus BitsMode BitExampleThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV Unaffected.UF o.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V o.C Unaffected.OVM Operation is not affected by OVM bit value.FLOAT *++AR2(2),R5Before Instruction:AR2 = 809800hR5 = 034C2000h = 1.27578125e + 01Data at 809802h = OAEh = 174LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR2 = 809802hR5 = 072EOOOOOh = 1.74e + 02Data at 809802h = OAEh = 174LUF LV UF N Z V C = 0 0 0 0 0 0 0RO.10-76Assembly Language Instructions
SyntaxOperationOperandsFLOAT src2, dst1II STF src3, dst2IIfloat(src2 ) ~ dst1src3 ~ dst2src2 indirect (disp = 0, 1, IRO, IR1)dst1 register (Rn1, 0::; n1 ::; 7)src3 register (Rn2, 0 ::; n2 3 7)dst2 register (disp = 0, 1, IRO, IR1)Encoding324\ I • • • • 11 1 0 1 0 1 11dst1. . src3• 23. I o· o· 0 I I I 1611 5.• • • • ••dst2src2DescriptionAn integer to floating-point conversion is performed. <strong>Al</strong>l registers are read atthe beginning and loaded at the end of the execute cycle. This means that ifone of the parallel operations (STF) reads from a register and the operationbeing performed in parallel (FLOAT) writes to the same register, then STF acceptsas input the contents of the register before it is modified by FLOAT.If src2 and dst2 point to the same location, src2is read before the write to dst2.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV Unaffected.UF O.N 1 if a negative result is generated,·O otherwise.Z 1 if a zero result is generated, 0 otherwise.V O.C Unaffected.OVM Operation is affected by OVM bit value.RO.10-77
ExampleFLOAT *+AR2(IRO),R6I I STF R7,*ARlBefore Instruction:AR2 = 8098C5hIRO = 8hR6 = OhR7 = 034C200000h = 1.27578125e + 01AR1 = 809933hData at 8098CDh = OAEh = 174Data at 809933h = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction: .AR2 = 8098C5hIRO = 8hR6 = 072EOOOOOOh = 1 .7 40e + 02R7 = 034C200000h = 1.27578125e + 01AR1 = 809933hData at 8098CDh = OAEh = 174Data at 809933h = 034C2000h = 1.27578125e + 01LUF LV UF N Z V C = 0 0 0 0 0 0 010-78Assembly Language Instructions
Interrupt AcknowledgelACK0:;:::;:;:::;:0:::;:::::-":;:;:;:;:::0:;:;:::;":"':::::::::::::::::::::;:::;:::"o!'::::::::::;:;':::::;:::;:;:::::;:;';';';':::-:::::';':·;·:·::;-::::::;.:o:·:·;·;·;-;:;·;·;:;:;"·;·:~":;:::;:;·;5::.;:::: ...;.;.:.,;.;.,;.:.:.......;.;.::;.:.;.;.;••.,;.;.;.......;.....;....;:;.;.::::;.;.;:;.;.;.;...;...;.;.;0;.;•••;0;.;.;.;«.;-:........ 0;-•• ..;.;.:::..,;.;.;.;.;.;.;•••,.;.:«.....;.;.......;...;.•••.•.;...;...................................................................................... v. .....................:...........:.•••.:.........""'-'=>'.:;:::;:>:;:::::::;:;:;=>:::05:;:0:::::::::;:::;:.:::::·:0:SyntaxOperationOperandslACK srcPerform a dummy read operation with lACK = o.At end of dummy read, set lACK to 1.srcgeneral addressing modes (G):o 1 direct1 0 indirectEncoding87isrciDescriptionA dummy read operation is performed with lACK = O. At the end of the dummyread, lACK is set to 1. This instruction can be used to generate an external interruptacknowledge. If the address specified is off-chip, a read operation fromthat address is performed. The lACK signal and the address can then be usedto signal interrupt acknowledge to external devices. The data read by the processoris unused.CyclesStatus BitsLUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Mode BitExampleOVM Operation is not affected by OVM bit value.lACK *AR5Before Instruction:lACK = 1PC =300hLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:lACK = 1PC = 301hLUF LV UF N Z V C = 0 0 0 0 0 0 010-79
IDLEIdle Until'''''''c.·,.,.",,.,.,.SyntaxOperationOperandsEncodingIDLE1 --7 ST(GIE)Next PC --7 PCIdle until interrupt.None31 24 23 16 15 8 7 0I 0' 0' 0 I 0' 0' l' l' 0 ' 0 I 0' 0' 0' 0 ' 0' 0' 0 " 0' 0' 0' 0' 0' 0' 0' 0' 0' 0' 0' 0' 0' 0' 0 ' 0 IDescriptionCyclesStatus BitsMode BitThe global interrupt enable bit is set, the next PC value is loaded into the PC,and the CPU idles until an interrupt is received. When the interrupt is received,the contents of the PC are pushed onto the active system stack.LUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM bit value.10-80Assembly Language Instructions
SyntaxOperationOperationLDE src, dstsrc{exp) ~ dst(exp)srcgeneral addressing modes (G):o 0 register (Rn, 0 $ n $ 7)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0 $ n $ 7)Encoding31 2423 16 15 87 o1 1 I·srcIIDescriptionCyclesStatus BitsMode BitExampleThe exponent field of the src operand is loaded into the exponent field of thedst register. No modification of the dst register mantissa field is made unlessthe value of the exponent loaded is the reserved value of the exponent for zeroas determined by the precision of the src operand. Then the mantissa field ofthe dstregister is set to zero. The srcand dstoperands are assumed to be floating-pointnumbers. Immediate values are evaluated in the short floating pointformat.LUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM bit value.LDE RO,R5Before Instruction:RO = 0200056F30h = 4.00066337e + 00R5 = OA056FE332h = 1 .06749648e + 03LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:RO = 0200056F30h = 4.00066337e + 00R5 = 02056FE332h = 4.16990814e + 00LUF LV UF N Z V C = 0 0 0 0 0 0 010-81
LDF Load Floating-Point "~;!~;.;. .. ;:~;:~;::: .. ;:;:;./.:o:::::;~:::;';-;:::::;';O>,::;:O-;:;:O~;:::::::;';~~«;';:~t:::::;:~">'t:::~"";:;:;:;,;:::o!,:,,;~,:,:,,,:,,::::;:;';Y;:;:;'/.;';:;:~;:;:;'''';'»';'~;:;y';:;O>';'/.;';';:::;:;:::;:;:;:;:~::;:;:;~t:;::.::;:;.>.;:;:;.>.::;:;:~»;.;:::;.>.;:;./'::~:;';:;y'"«'-;.;:;./.;:::;:;:;:;..::;:;Y/.XY;.».:o»/.::;';O/.::;''';O;'/.;:;:;::y';';';:::;:;:;y';')';:;'::;:;''»;';'~;'/'::;Y::~;'::::;'::::::iS">::;';'':-»::;:::::~~::~;';:;::Y.~;'».'6'';';:;:i'»'::~».;.... » ... ~SyntaxOperationOperandsLDF src, dstsrc~ dstsrc general addressing modes (G):o 0 register (Rn, 0 ~ n ~ 7)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0 ~ n ~ 7)Encoding131, , 1 ' , , , 24,231 1 116115, I "r 87 1 1000001110 G dst . src1DescriptionThe src operand is loaded into the dst register. The dst and src operands areassumed to be floating-point numbers.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV Unaffected.UF o.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V O.C Unaffected.OVM Operation is not affected by OVM bit value.RO.ExampleLDF@9800h,R2Before Instruction:DP = 80hR2 = OhData at 809800h = 1 OC52AOOh = 2.19254303e + 00LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:DP = 80hR2 = 01 OC52AOOOh = 2.19254303e + 00Data at 809800h = 1 OC52AOOh = 2.19254303e + 00LUF LV UF N Z V C = 0 0 0 0 0 0 010-82Assembly Language Instructions
SyntaxOperationLDFcond sre, dstIf eond is true:sre -7 dst.Else:dst is unchanged.Operandssre general addressing modes (G):0 register (Rn, 0 ~ n ::; 7)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0 ~ n ::; 7)Encoding31I I I I I. 0 1 0 o.2423 16 15I I II I I IIcond G dstI87 0I I IsrcIDescriptionIf the condition is true, the sre operand is loaded into the dst register. Otherwise,the dst register is unchanged. The dst and sre operands are assumedto be floating-point numbers.The TMS320C3x provides 20 condition codes that can be used with this instruction(see Section 10.2 for a list of condition mnemonics, encoding, andflags). Note that an LDFU (load floating-point unconditionally) instruction isuseful for loading R7 - RO without affecting condition flags. Condition flagsare set on a previous instruction only when the destination register is one ofthe extended-precision registers (R7-RO) or when one of the compare instructions(CMPF, CMPF3, CMPI, CMPI3, TSTB, or TSTB3) is executed.CyclesStatus BitsMode BitLUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM bit value.10-83
LDFcond;..................·.·.·;·;o.·.·.·...........·;·;·;.. ~·;~~;:;~:.~s:;:;:;sss:;s:;:;:~;·;:;·;·.· ...·..;.,;~·;·;:.·.·;·.·;..•...·Load Floating-Point Conditionally...••·••................................................................................;.......................................................;...;...... ~.;.; ...;o..;oo.;.....;o;...;.........;·;·;....·;·;·;.............;·;·;y.·;............·;......«Y;·;.....;·;.. v;o; .....;y.;·..;%....·;..·;....·:·;~..·;.... y;, .....;..;........·.·;.;·;·;~.. v: ..•.......·;·..... ~·; ..·;.."'·.,... s ...;Y.>...... s~ .. ~;:;·;sssss:;s:;ssss:~:,.~ExampleLDFZR3,R5Before Instruction:R3 = 2CFF2CD500h = 1.77055560e + 13R5 = 5F0000003Eh = 3.96140824e + 28LUF LV UF N Z V C = 0 0 0 0 1 0 0After Instruction:R3 = 2CFF2CD500h = 1.77055560e + 13R5 = 2CFF2CD500h = 1.77055560e + 13LUF LV UF N Z V C = 0 0 0 0 1 0 010-84Assembly Language Instructions
Load Interlocked LDFISyntaxOperationOperandsLDFI src, dstSignal interlocked operation.src~ dstsrc general addressing modes (G):o 1 direct1 0 indirectdst register (Rn, 0 ::;; n ::;; 7)EncodingDescriptionCyclesI I II' ,000,00 , I" 1111, " , I I31 2423 1615 87 aI I I I I IG dst srcThe srcoperand is loaded into the dstregister. An interlocked operation is signaledover XFO and XF1. The src and dstoperands are assumed to be floatingpointnumbers. Note that only direct and indirect modes are allowed. Refer toSection 6.4 for detailed description.1 if XF1 = 0 (see Section 6.4)Status BitsMode BitExampleThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV Unaffected.UF O.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V O.C Unaffected.OVM Operation is not affected by OVM bit value.LDFI *+AR2,R7Before Instruction:AR2 = 8098F1 hR7 = OhData at 8098F2h = 584COOOh = - 6.28125e + 01LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR2 = 8098F1 hR7 = 0584COOOOOh = - 6.28125e + 01Data at 8098F2h = 584COOOh = - 6.28125e + 01LUF LV UF N Z V C = 0 0 0 0 0 0 1RO.10-85
SyntaxIILDF sre2, dst2LDF sret, dst1OperationOperandsIIsre2~ dst2sre1 ~ dst1sre1 indirect (disp = 0, 1, IRO, IR1)dst1 register (Rn1, ° :::; n1 :::; 7)sre2 indirect (disp = 0,1, IRO, IR1)dst2 register (Rn2, 0:::; n2 :::; 7)Encoding1 1 0 0 0 1 0 dst2 dst1ii16 15iiisrc1, I87 oI' iiisrc2DescriptionTwo floating-point loads are performed in parallel. If the LDFs load the sameregister, the assembler issues a warning. The result is that of LDF sre2, dst2.CyclesStatus BitsMode BitLUFLVUFNZVCUnaffected.UnaffeCted.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM bit value.10-86Assembly Language Instructions
Example LDF *--, AR1 (IRO) ,R7I I LDF *AR7++ (1), R3Before Instruction:AR 1 = 80985FhIRO = 8hR7 = OhAR7 = 80988AhR3 = OhData at 809857h = 70C8000h = 1.4050e + 02Data at 80988Ah = 57B4000h = 6.281250e + 01LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR 1 = 809857hRO =8hR7 = 070C800000h = 1.4050e + 02AR7 = 80988BhR3 = 057B400000h = 6.281250e + 01Data at 809857h = 70C8000h = 1.4050e + 02Data at 80988Ah = 57B4000h = 6.281250e + 01LUF LV UF N Z V C = 0 0 0 0 0 0 010-87
LDFIISTFParallel LDF and STF....;.;.;•••••;•••;.......;•••••••••••••••:-:.;.;•••;,;.;,;';';:;:::;:::::::::;0::::::::::::';:::::.'::.:::.'.::••:::;.;.;.;.;.;•••••••;.;.;.;0;•••;•••;•••••••••••;•••;.;.....................;.......................;.;:::::;::.;:::;:;-::;::':':::';':';O;';o;o;.;.;.;o;.;.;o;•••;.:.;.,,:.;:;:;~..;O;".;.:.;.;.;.;.;.;.;.;.;~;o;.;o;.:.:.;.:.;........;o;.;•••,,;o;•........ n ......;·;·;·.....;o;o..;q.·.......;o-..;....;~...·;o;·.·......·;·;.o;·;~.~•• ;•••;
Example LDF *AR2--(1) ,RlI I STF R3, *AR4++ (IR1)Before Instruction:AR2 = 8098E7hR1 = OhR3 = 0578400000h = 6.28125e + 01AR4 = 809900hIR1 = 10hData at 8098E7h = 70C8000h = 1 .4050e + 02Data at 809900h = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR2 = 8098E6hR1 = 070C800000h = 1.4050e + 02R3 = 057B400000h = 6.28125e + 01AR4 = 80991 OhIR1 = 10hData at 8098E7h = 70C8000h = 1.4050e + 02Data at 809900h = 57B4000h = 6.28125e + 01LUF LV UF N Z V C = 0 0 0 0 0 0 010-89
LOILoadSyntaxOperationOperandslOt src, dstsrC-7 dstsrc general addressing modes (G):0 register (Rn, 0 ~ n ~ 27)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0 ~ n ~ 27)Encoding31 2423 87IsrcIDescriptionThe src operand is loaded into the dst register. The dst and src operands areassumed to be signed integers. An alternate form of LOI, LOP, is used to loadthe data page pointer register (OP), or any other register with the eight MSBsof a relocatable address. See the LOP instruction and subsection 10.3.2.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected.lV Unaffected.UF O.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V O.C Unaffected.OVM Operation is not affected by OVM bit value.RO.10-90Assembly Language Instructions
Load Integer;:;'''%:;!;:::::;:::;:::::::::;:::;~o:;:::;:;:".:::::::;';:;:::::~:;:;:::;:;:::::;:::;:;:::;:::::::::;:;:;:::::;:::;:"':;::';';:;o;~.::::::.;:::~::;:;:;:;:;::.;:;~:::::.;::.:-;.::~::o;:;:;:;:;:;';-;::::';«';"::N::::::::v.;'::::;:::.::'::::;';';';';-;';';';';::';';';';';0;';';',';';0;';';';';''';';';-;';';';::';'.:.';';';';';';':';';';-;'»;-;';0;';0;9;0;';';';';';0;';';":0;',';o;o;o;·;..:·;·;y;·;·;v;·;·;·;.,.;·;-;o;,»;,;,;,:·;,,:::·;·:v.;·;·;·;..:o;·;Y.;~:'''·'''''·'·'''''''·'' ......... !o"N.;·''''''''''·M .. ''·'·':'!>·;'':;:':;(.:O:;::%:;::::::Y';:;';::::::'::::Y;:;:::o:LOIExampleLDI *-AR1(IRO),R5Before Instruction:AR1 = 2ChIRQ = 5hR5 = 3C5h = 965Data at 27h = 26h = 38LUF LV UF N Z V C = 0 0 0 0 0 0 QAfter Instruction:AR1 = 2ChIRQ = 5hR5 = 26h = 38Data at 27h = 26h = 38LUF LV UF N Z V C = Q 0 0 0 0 Q 010-91
LDlcondLoad Integer Conditionally;:.:.:.:;:M.:...•...·.:.·.:.:.·.!O·.·.:.:.:;:;:.:.:.:.·;:;~:;:;:;:'::;:::::;:;:;:;:;:;:;:;:::;:':'~:':':""::;:.:;:.:.:.:.:; ·.:.:::&.·.·.·.·.:.·.·.:.:.v...·.:.·.:.:.:.u.....·.·.·.·.:.·.:.·.·.·...·.:.:o':.:.:.!o:...•••••.....·.:.·6~:;..·.:;:;·;·:·;.;.;.;.;.;••• ~;.; ••:::;.;:;:;:;:;•••;:.:;:;.;:;.;••••••:;::.;:;.;::...;.;.;::::::.;.;••:;.;.;.;.;:;.;.,.;.;.;.;.,:;:;.;.;:;•••;:......;.;••••••:;.•••..::;....:.•••;.;.;:;•••)!;.;.;O;.;.;O;::.;.;.;•••••;•••••;.••;..!.•••;••::::y::;:;.;:::;•••;:.:......;.....:;.;••..:.;::.;::::::.;.;.;.;.;.;.;.:::.;.;.;:;:::;:;~;..::;:;O:~;::!::::::::;:;:::;Y.::;::::SyntaxOperationLDlcond src, dstIf cond is true:srC-7 dst,Else:dst is unchanged.Operandssrc general addressing modes (G):o 0 register (Rn, 0 ::;; n ::;; 27)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0 ~ n ::;; 27)Encoding31I' . 0 1 " 0 1. I2423 1615I I II i i IIcond G dstI87 0i i IsrcIDescriptionIf the condition is true, the src operand is loaded into the dst register. Otherwise,the dst register is unchanged. The dst and src operands are assumedto be signed integers.The TMS320C3x provides 20 condition codes that can be used with this instruction(see Section 10.2 for a list of condition mnemonics, encoding, ~ndflags). Note that an LDIU (load integer unconditionally) instruction is useful forloading R7 - RO without affecting the condition flags. Condition flags are seton a previous instruction only when the destination register is one of the extended-precisionregisters (R7-RO) or when one of the compare instructions(CMPF, CMPF3, CMPI, CMPI3, TSTB, or TSTB3) is executed.CyclesStatus BitsMode BitLUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM bit value.10-92Assembly Language Instructions
Load Integer ConditionallyL[)I~()nd::::::-:::::;:::::::::::::::::.:::::."':::::::;:::::::::::::::;.:::::::::::::::::::::::::::::::::::.:::::;::;:;.;:;';:;:;';:::::::::;0:::::::::':::::'::::::;';';:;';';';':.;.;.;:;.;::,;.:::::::::.;:::::;.;:;.:::.;,;,;.;:;.::;.;.;.;.;:.::.;:;.,.;.;.;.;.;.;.;.::;.;.;.;.;.;:;.;.;.;:.:••;:•• ~; ••:;:;::::••:;.;.;:;.;:.:;:••:.:•••;.;::.:.;.;.;:;.;.::::::::::::;.;.;.;.;.;.;.;::.;.,.;.;.,.;.;." ••••••••,•••;:.......:.................... 10'.:.: .............:••........................,.:..............,:.:•••:.:•••.•:•••:.':.:......;.;:;.;:::.:;:;:;:::::::;:;:;:;:::;:;:::.:.~:::.:.y..:.:.::~:.:.:.:::.:::.:;:::.:::::::ExampleLDIZ R4,R6Before Instruction:R4 = 027Ch = 636R6 = OFE2h = 4,066LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R4 = 027Ch = 636R6 = OFE2h = 4,066LUF LV UF N Z V C = 0 0 0 0 0 0 010-93
LOllLoad Integer, Interlocked~7.=:=;:~:;:;~:;:O-:~;:::;:::;:;~
SyntaxLDI src2, dst2\I LDI src1, dst1Operationsrc2 --7 dst2\I src1 --7 dst1Operandssrc1 indirect (disp = 0, 1, IRa, IR1)dst1 register (Rn1, a :5 n1 :5 7)src2 indirect (disp = 0, 1, IRa, IR1)dst2 register (Rn2, a :5 n2 :5 7)EncodingIIdst1I I Isrc187I'I I Isrc2DescriptionTwo integer loads are performed in parallel. A warning is issued by the assemblerif the LDls load the same register. The result is that of LDI src2, dst2.CyclesStatus BitsMode BitLUFLVUFNZVCUnaffected.Unaffected.·Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM bit value.10-95
ExampleLDI *-ARl(1),R7I I LDI *AR7++ (IRO) ,RlBefore Instruction:AR 1 = 809826hR7 = OhAR7 = 8098C8hIRO = 10hR1 = OhData at 809825h = OFAh = 250Data at 8098C8h = 2EEh = 750LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR1 = 809826hR7 = OFAh = 250AR7 = 8098D8hIRO = 10hR1 = 02EEh = 750Data at 809825h = OFAh = 250Data at 8098C8h = 2EEh = 750LUF LV UF N Z V C = 0 0 0 0 0 0 01 0-96 Assembly Language Instructions
SyntaxIILOI src2, dst1STI src3, dst2OperationOperandsEncodingIIsrc2-t dst1src3 -t dst2src2 indirect (disp = A, 1, IRa, IR1)dst1 register (Rn1, a :;; n1 :;; 7)src3 register (Rn2, a :;; n2 :;; 7)dst2 indirect (disp = a, 1, IRa, IR1)iiidst2iii87 oiiiI i src2DescriptionCyclesStatus BitsMode BitAn integer load and an integer store are performed in parallel. If src2 and dst2point to the same location, src2 is read before the write to dst2.LUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM bit value.10-97
LDIIISTIParallel LOI and sri;:;:;:o:;:;:::;o:.~:O~~;:.:.:;:.:;:':;Y;:::;:.~::::::::::::::::".::-.::::::;:;:::;,,::;:.:::':::::::~;:;:;:::;:;:;:;:::;!o!O·;:.:::':O:h~::":;:.:;:,, ... :.:.: ....... ,. .... y, ... ·;:;·::::::;:::;::s::::::::::::::.::::::.::::::;:::::;::s:::::::;:::::;r.:::::;:::;:;:;::::::::::::::::y.;:::::;:::;~.::::;y.::,;:;:;::::::y.::;::::::::::::::::::::s::·::: ....:::::::::::::::::·:·;·::::::::: ... :.~:.;:;.;:;-;.;.:O;.:O; .. ::::.:::::::.:.; .... :: ... ;O;.:~Y.:.; ..... ;:;.:.::::::::.~::::;:::::::;:~~:::::~;r.:;::.::::;:;:;:::::::::::::::::;::r.~;:;::-:;::r.::::=,*;::s.":::::;:::::.~:;:':::ExampleLDI *-ARl(1),R2II STI R7,*AR5++(IRO)Before Instruction:AR 1 = 8098E7hR2 = OhR7 = 35h = 53AR5 = 80982ChIRO = 8hData at 8098E6h = ODCh = 220Data at 80982Ch = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR1 = 8098E7hR2 = ODCh = 220R7 = 35h = 53AR5 = 809834hIRO = 8hData at 8098E6h = ODCh = 220Data at 80982Ch = 35h = 53LUF LV UF N Z V C = 0 0 0 0 0 0 01 0-98 Assembly Language Instructions
LOPLoad Data Page Pointer~»~.x~~~~;:;:;:::::;::~:~~»"!o"!:9.:-:~~~~~;:>::::-:::~:;:~~~~::;:>:;:::;:::::::.:::oY.;:bX .... oY.;: ... se.!>:.:~'tI!Mt~*~~.:;.:~~~'!~'!~~~::~~:::::::;:;:;s:;:::::::::::;:::;::::::~:::~.,;:::;.~:.;:;.;*;::.::;.;.::;:>.:. ::;.;.;.:.:::-;.;::y:::: .. ::;:;.;.;.:.::::::::.,;.:::.;.;o;::::·;'::~;·:·:·;:;';:;·:~9;o.;:>:X~:;Y:·X'~;"·;·";·::N;:::~:;·::::;:;·;.;.x.;:;s·:!>·.:;::::..:~!o~;.;·x~:;:::;s*:*;:;»~::."!~::~~;»"!::~~).,:::::i?'SyntaxOperationOperandsLOP sre,DPsre ~ Data page pointersre is the 8 MSBs of the absolute 24-bit source address (sre).The ",DP" in the operand is optional.dst register (Rn, 0 ::; n ::; 7)Encoding1 I,srcDescriptionThis pseudo-op is an alternate form of the LDI instruction, except that LOP isalways in the immediate addressing mode. The sreoperand field contains theeight MSBs of the absolute 24-bit sreaddress (essentially, only bits 23 -16 ofsreare used). These eight bits are loaded into the eight LSBs of the data pagepointer.The eight LSBs of the pointer are used in direct addressing as a pointer to thepage of data being addressed. There is a total of 256 pages, each page 6.4Kwords long. Bits 31 - 8 of the pointer are reserved and should be kept to zero.CyclesStatus BitsMode BitExampleThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV Unaffected.UF Unaffected.N Unaffected.Z Unaffected.V Unaffected.C Unaffected.OVM Operation is not affected by OVM bit value.LDP @809900h, DPorLDP @809900hBefore Instruction:DP = 65hLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:DP = 80hLUF LV UF N Z V C = 0 0 0 0 0 0 0RO.1 0-1 00 Assembly Language Instructions
SyntaxOperationLSH count, dstIf count~ 0:dst« count -7 dstElse:dst» I count I -7 dstOperands. count general addressing modes (G):o 0 register (Rn, 0 :::; n :::; 27)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0 :::; n :::; 27)Encoding31. • 1 • • • • 24.23000010011G1187icountiDescriptionThe seven least significant bits of the countoperand are used to generate thetwos-complement shift count. If the countoperand is greater than zero, the dstoperand is left-shifted by the value of the countoperand. Low-order bits shiftedin are zero-filled, and high-order bits are shifted out through the C (carry) bit.Logical left-shift:C ~ dst~ 0If the count operand is less than zero, the dst is right-shifted by the absolutevalue of the count operand. The high-order bits of the dst operand are zerofilledas shifted to the right. Low-order bits are shifted out through the C (carry)bit.Logical right-shift:0-7 dst-7 CIf the count operand is 0, no shift is performed and the C (carry) bit is set to O.The count operand is assumed to be a signed integer and the dst operand isassumed to be an unsigned integer.10-101
SyntaxOperationLSH3 count, src, dstIf count ~ 0:src « count ~ dstElse:src» /count / ~ dstOperandsEncodingDescriptionregister (Rn1, 0::::;; n ::::;; 27)° 1 indirect (disp = 0, 1, IRO, IR1)1 ° register (Rn1, 0::::;; n1 ::::;; 27)1 1 indirect (disp = 0, 1, IRO, IR1)srcthree-operand addressing modes (T):count three-operand addressing modes (T):° register (Rn2, ::::;; n2 ::::;; 27)° 1 register (Rn2, ° ::::;; n2 ::::;; 27)1 ° indirect (disp 0, 1, IRO, IR1)1 1 indirect (disp = 0, 1, IRO, IR1)dst register (Rn, ° ::::;; n ::::;; 27)312423 16 15 87 0I I I I I II I I II 1 ' I " " 1 I,001,001000, T dst src countIThe seven least significant bits of the countoperand are used to generate thetwos-complement shift count.IIIf the count operand is greater than zero, the dst operand is left-shifted bythe value of the count operand. Low-order bits shifted in are zero-filled, andhigh-order bits are shifted out through the C (carry) bit.Logical left-shift:C f-- src f--°If the count operand is less than zero, the src operand is right-shifted by theabsolute value of the countoperand. The high-order bits of the dstoperand arezero-filled as shifted to the right. Low-order bits are shifted out through the C(carry) bit.Logical right-shift:° ~ src~ CIf the countoperand is 0, no shift is performed and the C (carry) bit is set to 0.The count operand is assumed to be a signed integer. The src and dst operandsare assumed to be unsigned integers.10-103
LSH3Logical Shift, 3-0perand~~y.~~.~,,-~~;o~~;:,"';~;:;:~«;:;:;:;:;:;:o:~;:.:.:.:;:::~:;:;:;:;:;:~.:.:;:;:.:.:~:.:.::y.::::;:;:;:;:.:.:;:.';:;'~v..:.'«-»:~:~.:':N..: ... :.:.~~;SO:~.:;~;:::;:;:;:;~~~:~~:::;:;:;:::;O:y';o;:;::::.~::;:;:::~~:;%:::~:;:;:;:"':;"~'~S"';·;O*~~~;';S%~;:>y'~~·::~~:~~.;~:·:::~;:;o: .... ~;:.::·:·;·:~':::~~:;:;:::;~~:;';:;:~~~:;::Y,::;~.~~::::~~y.:Y,:::Y,:Y,;S:OS:;S:~S:"~:~::;::Y,::::::::::;::~CyclesStatus BitsMode BitExample 1These condition flags are modified only if the destination register is R7 -LUF Unaffected.LV Unaffected.UF O.N MSB of the output.Z 1 if a zero output is generated, 0 otherwise.V O.C Set to the value of the last bit shifted out. 0 for a shift count of O.Unaffected if dst is not R7 - RO.OVM Operation is not affected by OVM bit value.LSH3 R4,R7,R2RO.Before Instruction:R4 = 018h = 24R7 = 02AChR2 = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R4 = 018h = 24R7 = 02AChR2 = OACOOOOOOhLUF LV UF N Z V C = 0 0 0 1 0 l' 0Example 2LSH3 *-AR4(IR1),R5,R3Before Instruction:AR4 = 809908hIR1 = 4hR5 = 012COOOOOhR3 = OhData at 809904h = OFFFFFFF4h = -12LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR4 = 809908hIR1 = 4hR5 = 012COOOOOhR3 = 0000012COOhData at 809904h = OFFFFFFF4h = -12LUF LV UF N Z V C = 0 0 0 0 0 0 01 0-1 04 Assembly Language Instructions
SyntaxOperationOperandsLSH3 count, src2, dst1II STI src3, dst2If count~ 0:src2« count,-7 dst1Else:src2» I count I -7 dst1II src3 -7 dst2count register (Rn1, ° ~ n1 ~ 7)src1 indirect (disp = 0, 1, IRO, IR1)dst1 register (Rn3, ~ n3 ~ 7)src2 register (Rn4, ° ~ n4 ~ 7)dst2 indirect (disp = 0, 1, IRO, IR1)EncodingIIcountI I I I I Idst2src2DescriptionThe seven least significant bits of the count operand are used to generate thetwos-complement shift count.If the count operand is greater than zero, the dst operand is left-shifted bythe value of the count operand. Low-order bits shifted in are zero-filled andhigh-order bits are shifted out through the C (carry) bit.Logical left-shift:C ~ dst2~ °If the count operand is less than zero, the dst operand is right-shifted by theabsolute value of the count operand. The high-order bits of the dst operandare zero-filled as shifted to the right. Low-order bits are shifted out through theC (carry bit).Logical right-shift:0-7 dst2-7 CIf the count operand is 0, no shift is performed and the carry bit is set to 0.The count operand is assumed to be a 7 -bit signed integer, and the src2 anddst1 operands are assumed to be unsigned integers. <strong>Al</strong>l registers are read atthe beginning and loaded at the end of the execute cycle. This means thatif one of the parallel operations (STI) reads from a register and the operationbeing performed in parallel (LSH3) writes to the same register, then STI acceptsas input the contents of the register before it is modified by the LSH3.If src2 and dst2 point to the same location, src2 is read before the write to dst2.10-105
CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV Unaffected.UF . O.N MSB of the output.Z 1 if a zero output is generated, 0 otherwise.V O.C Set to the value of the last bit shifted out. 0 for a shift count of O.OVM Operation is affected by OVM bit value.RO.ExampleLSH3I I STIR2,*++AR3(1),ROR4, *-AR5Before Instruction:R2 = 18h = 24AR3 = 8098C2hRO = OhR4 = ODCh = 220AR5 = 8098A3hData at 8098C3h = OAChData at 8098A2h = OhLU F LV UF N Z V C = '0 0 0 0 0 0 0After Instruction:R2 = 18h = 24AR3 = 8098C3hRO = OACOOOOOOhR4 = ODCh = 220AR5 = 8098A3hData at 8098C3h = OAChData at 8098A2h = OOCh = 220LUF LV UF N Z V C = 0 0 0 1 0 010-106Assembly Language Instructions
MPYFMultiply Floating-Point;:;~:;:::;:;:;:::;:;:;:;:;:;:;:;~:;:::;:;:::;:::;:::;:;~:;:::;:;:;:;~:;:::;:;:::::;~:;:::;:;:':;:;:;"":::;~:::;: •• ;:;~ •••• :::.::.;:.: •• ~~::.:.:.: ••• :; ••• ; •• ::~.; •• :.'o' ........ ;.;.;:::;:::;:::::;.;::~~:"~::;:::;:;~:;:;::::::::::::::::::::::.::::::::::::::::::::::::::;.::::::::::::::::;:::::;.;:::::;:::::::;:::::;::-;:::;~.:.-:.:~:;::.;:::::;.;::::::::.;:;.;:::;.;::::::.;-;:;-:.;.;.;::::.:::: •• ;.;:::; ••• ;:::;.;.:.;.;.;.; ••• ;.;:: ••••••• ; ..... ;:::;::.::;::.;.;.;.:.:::.:.:.:::.::;:;:;:;~;:;:: .. ::::.:::.::;:;:;:::;:;.;:::;:;:;~:;:;:;:::::::::;:.::.:~::::~:::;:::;:;:::;~:;~::~~:::;:;:;:;SyntaxOperationOperandsMPYF src, dstdst x src -7 dstsrc general addressing modes (G):0 register (Rn, 0 S; n s; 7)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0 s; n s; 7)Encoding311 I' 1 1 1 1 124 1 23000010100 G1116 15871 1srcDescriptionThe product of the dst and src operands is loaded into the dst register. The srcoperand is assumed to be a single-precision floating-point number, and the dstoperand is an extended-precision floating-point number.CyclesStatus BitsMode BitExampleThese condition flags are modified only if the destination register is R7 -LUF 1 if a floating-point underflow occurs, unchanged otherwise.LV 1 if a floating-point overflow occurs, unchanged otherwise.UF 1 if a floating-point underflow occurs, 0 otherwise.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if a floating-point is overflow occurs, 0 otherwise.C Unaffected.OVM Operation is not affected by OVM bit value.MPYF RO,R2Before Instruction:RO = 070C800000h = 1 .4050e + 02R2 = 034C200000h = 1.27578125e + 01LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:RO = 070C800000h = 1 .4050e + 02R2 = OA600F2000h = 1.79247266e + 03LUF LV UF N Z V C = 0 0 0 0 0 0 0RO.10-108Assembly Language Instructions
SyntaxOperationOperandsEncodingM PYF3 src2, src 1, dstsrc1 x src2 ~ dst° register (Rn1, ° :s; n1 :s; 7)1 ° register (Rn1, ° :s; n1 :s; 7)src1 three-operand addressing modes (T):° 1 indirect (disp = 0, 1, IRO, IR1)1 1 indirect (disp = 0, 1, IRO, IR1)register (Rn2,° 1 register (Rn2, °1 ° indirect (disp = 0, 1, IRO, IR1)1 1 indirect (disp =- 0, 1, IRO, IR1)dst register (Rn, ° :s; n :s; 7)src2 three-operand addressing modes (T)::s; n2 :s; 7):s; n2 :s; 7)31 2423 16 15iiisrc187 oI I I, II'src2DescriptionThe product of the dst1 and src2 operands is loaded into the dst register. Thesrc1 and src20perands are assumed to be single-precision floating-point numbers,and the dst operand is an extended-precision floating-point number.Cycles -Status BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF 1 if a floating-point underflow occurs, unchanged otherwise.LV 1 if a floating-point overflow occurs, unchanged otherwise.UF 1 if a floating-point underflow occurs, ° otherwise.N 1 if a negative result is generated, ° otherwise.Z 1 if a zero result is generated, ° otherwise.V 1 if a floating-point is overflow occurs, ° otherwise.C Unaffected.OVM Operation is not affected by OVM qit value.RO.10-109
Example 1MPYF3 RO,R7;RlBefore Instruction:RO = 0578400000h = 6.281250e + 01R7 = 0733COOOOOh = 1.79750e + 02R1 = Oh ,LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:RO = 0578400000h = 6.281250e + 01R7 = 0733COOOOOh = 1 .79750e + 02R1 = OD306A3000h = 1.1290546ge + 04LUF LV UF N Z V C = 0 0 0 0 0 0 0'Example 2MPYF3 *+AR2(IRO),R7,R2orMPYF3 R7,*+AR2(IRO),R2Before Instruction:AR2 = 809800hIRO=12AhR7 = 0578400000h = 6.281250e + 01R2 =OhData at 80992Ah = 70C8000h = 1 .4050e + 02LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR2 = 809800hIRO = 12AhR7 = 0578400000h = 6.281250e + 01R2 = OD09E4AOOOh = 8.82515625e + 03Data at 80992Ah = 70C8000h = 1.4050e + 02LUF LV UF N Z V C = 0 0 0 0 0 0 010-110Assembly Language Instructions
SyntaxIIMPYF3 srcA, srcB, dst1ADDF3 srcC, srcD, dst2OperationsrcA x srcB ~ dst1II srcC + srcD ~ dst2OperandssrcAsrcB Any two indirect (disp = O,1,IRO,IR1)srcCUAny two register (0 ~ Rn ~ 7)srcDdst1dst2register (d1):0= RO1 = R1register (d2):0= R21 = R3src1src2src3src4registerregisterindirectindirect(Rn, 0 ~ n ~ 7)(Rn, 0 ~ n ~ 7)(disp = 0, 1, IRO, IR1)(disp = 0, 1, IRO, IR1)P parallel addressing modes (0 ~ P ~ 3)Operation (P Field)00 src3 x src4, src 1 + src201 src3 x src1, src4 + src210 src 1 x src2, src3 + src411 src3 x src 1, src2 + src4Encoding31 2423iiisrc3iiisrc4DescriptionA floating-point multiplication and a floating-point addition are performed inparallel. <strong>Al</strong>l registers are read at the beginning and loaded at the end of the executecycle. This means that if one of the parallel operations (MPYF3) readsfrom a register and the operation being performed in parallel (ADDF3) writesto the same register, then MPYF3 accepts as input the contents of the registerbefore it is modified by the ADDF3.10-111
Any combination of addressing modes may be coded for the four possiblesource operands as long as two are coded as indirect and two are register. Theassignment of the source operands srcA - srcDto the src1 - src4fields varies,depending on the combination of addressing modes used, and the P field isencoded accordingly. The assembler may, when not significant, change the orderof operands in commutative operations in order to simplify processing.If src2 and dst2 point to the same location, src2 is read before the write to dst2.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF 1 if a floating-point underflow occurs, unchanged otherwise.LV 1 if a floating-point overflow occurs, unchanged otherwise.UF 1 if a floating-point underflow occurs. 0 otherwise.N O.Z O.V1 if a floating-point overflow occurs, 0 otherwise.C Unaffected. \OVM Operation is not affected by OVM bit value.RO.ExampleMPYF3II ADDF3*AR5++(1),*--ARl(IRO),ROR5,R7,R3Before Instruction:AR5 = 8098C5hAR 1 = 8098A8hIRO = 4hRO = OhR5 = 0733COOOOOh = 1 .79750e + 02R7 = 070C800000h = 1 .4050e + 02R3 = OhData at 8098C5h = 34COOOOh = 1.2750e + 01Data at 8098A4h = 111 OOOOh = 2.2500e + 00LUF LV UF N Z V C = 0 0 0 0 0 0 010-112Assembly Language Instructions
After Instruction:AR5 = 8098C6hAR1 = 8098A4h .IRO = 4hRO = 0467180000h = 2.88867188e + 01R5 = 0733COOOOOh = 1.79750e + 02R7 = 070C800000h = 1.4050e + 02R3 = 0820200000h = 3.20250e + 02Data at 8098C5h = 34COOOOh = 1.2750e + 01Data at 8098A4h = 111 OOOOh = 2.2500e + 00LUF LV UF N Z V C = 0 0 0 0 0 0 010-113
SyntaxMPYF3 src2, src1, dstII STF src3, dst2OperationIIsrc1 x src2 --+ dst1src3 --+ dst2Operandssrc1 register (Rn1, 0 ::; n1 ::; 7)src2 indirect (disp = 0, 1, IRO, IR1)dst1 register (Rn3, 0 ::; n3 ::; 7)src3 register (Rn4, 0 ::; n4 ::; 7)dst2 indirect (disp = 0, 1, IRO, IR1)Encodingi isrc1I 11rSIsrc3Iiidst2II87iiisrc2DescriptionA floating-point multiplication and a floating-point store are performed in parallel.<strong>Al</strong>l registers are read at the beginning and loaded at the end of the executecycle. This means that if one of the parallel operations (MPVF3) writes to a registerand the operation being performed in parallel (STF) reads from the sameregister, then the STF accepts as input the contents of the register before it ismodified by the MPVF3.If src2 and dst2 point to the same location, then src2 is read before the writeto dst2.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF 1 if a floating-point underflow occurs, 0 unchanged otherwise.LV 1 if a floating-point overflow occurs, unchanged otherwise.UF 1 if a floating-point underflow occurs, 0 otherwise.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if a floating-point overflow occurs, 0 otherwise.C Unaffected.OVM Operation is not affected by OVM bit value.RO.10-114Assembly Language Instructions
Example MPYF3 *-AR2(1),R7,ROI I STF R3, *ARO--(IRO)Before Instruction:AR2 = 809828hR7 = 0578400000h = 6.281250e + 01RO = OhR3 = 0868280000h = 4.7031250e + 02ARO = 809860hIRO = 8hData at 80982Ah = 70C8000h = 1 .4050e + 02Data at 809860h = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR2 = 809828hR7 = 0578400000h = 6.281250e + 01RO = OD09E4AOOOh = 8.82515625e + 03R3 = 0868280000h = 4.7031250e + 02 .ARO = 809858hIRO = 8hData at 80982Ah = 70C8000h = 1.4050e + 02Data at 809860h = 868280000h = 4.7031250e + 02LUF LV UF N Z V C = 0 0 0 0 0 0 010-115
SyntaxOperationOperandsIIIIMPYF3 sreA, sreB, dst1SUBF3 sreC, sreD, dst2. sreA x sreB -7 dst1sreD - sreC -7 dst2sreAsreB Any two indirect (disp = 0,1 ,IRO,IR1)sreCUAny two register (0 ~ Rn ~ 7)sreDdst1dst2register (dl):0= RO1 = R1register (d2):0= R21 = R3sre1sre2sre3sre4registerregisterindirectindirect(Rn, ° ~ n ~ 7)(Rn, ° ~ n ~ 7)(disp= 0, 1, IRO, IR1)(disp = 0, 1, IRO, IR1)P parallel addressing modes (0 ~ P ~ 3)Operation (P Field)00 sre3 x sre4, sre 1 - sre201 sre3 x sre 1, sre4 - sre21 ° sre 1 x sre2, sre3 - sre411 sre3 x sre1, sre2 - sre4Encoding31 2423i isrc116 15iii isrc2iiisrc387iiisrc4I'DescriptionA floating-point multiplication and a floating-point subtraction are performed inparallel. <strong>Al</strong>l registers are read at the beginning and loaded at the end of the executecycle. This means that if one of the parallel operations (MPYF3) readsfrom a register, and the operation being performed in parallel (SUBF3) writesto the same rregister, then MPYF3 accepts as input the contents of the registerbefore it is modified by the SUBF3.10-116Assembly Language Instructions
After Instruction:R5 = 034COOOOOOh = 1.2750e +01AR7 = 80990Ch .IR1 = 8hRO = 0467180000h = 2.88867188e + 01R7 = 0733COOOOOh = 1 .79750e + 02AR3 = 809881 hR2 = 05E3000000h = - 3.9250e + 01Data at 80990Ch = 111 OOOOh = 2.250e + 00Data at 8098B2h = 70C8000h = 1.4050e + 02LUF LV UF N Z V C = 0 0 0 0 0 0 010-118Assembly Language Instructions
SyntaxOperationOperandsEncodingDescriptionMPYI sre, dstdst x sre -7 dstsre general addressing modes (G):0 register (Rn, 0 ~ n ~ 27)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0 ~ n ~ 27)87o,3\ , , ' , , ,24,23, I I, I000010101 G srcThe product of the dst and sre operands is loaded into the dst register. The sreand dst operands, when read, are assumed to be 24-bit signed integers. Theresult is assumed to be a 48-bit signed integer. The output to the dst registeris the 32 least significant bits of the result.Integer overflow occurs when any of the most significant 16 bits of the 48-bitresult differs from the most significant bit of the 32-bit output value.CyclesStatus BitsMode BitExampleThese condition flags are modified only if the destination register is R7 -LUF Unchanged.LV 1 if an integer overflow occurs, unchanged otherwise.UF O.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if an integer overflow occurs, 0 otherwise.C Unaffected.OVM Operation is affected by OVM bit value.MPYI Rl,R5Before Instruction:R1 = 000033C251 h = 3,392,081R5 = 0000788600h = 7,910,912LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R1 = 000033C251 h = 3,392,081R5 = 00E21 D9600h =- 501 ,377,536LUF LV UF N Z V C = 0 1 0 1 0 1 0RO.10-119
SyntaxOperationOperandsMPYI3 src2, src1, dstsrc 1 x src2 ~ dstsrc1 three-operand addressing modes (T):o 0 register (Rn1, n1 ~ 27)o 1 indirect (disp = 0, 1, IRO, IR1)1 0 register (Rn1, $ n1 ~ 27)1 1 indirect (disp = 0,1, IRO, IR1)src2 three-operand addressing modes (T):o 0 register (Rn2, ~ n2 ~ 27)o 1 register (Rn2, ~ n2 ~ 27)1 0 indirect (disp = 0, 1, IRO, IR1)1 1 indirect (disp = 0, 1, IRO, IR1)dst register (Rn, 0 ~ n ~ 27)EncodingDescription312423 16 15 87 0I I I1"1""'1.001.001010.I I I I I I I I IT dst src1 src2IThe product of the src1 and src2 operands is loaded into the dst register. Thesrc1 and src2 operands are assumed to be 24-bit signed integers. The resultis assumed to be a signed 48-bit integer. The output to the dst register is the32 least significant bits of the result.Integer overflow occurs when any of the most significant 16 bits of the 48-bitresult differs from the most significant bit of the 32-bit output value.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unchanged.LV 1 if an integer overflow occurs, unchanged otherwise.UF O.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if an integer overflow occurs, 0 otherwise.C Unaffected.OVM Operation is affected by OVM bit value.RO.10-120Assembly Language Instructions
Example 1MPYI3 *AR4,*-AR1(1),R2Before Instruction:AR4 = 809850hAR1 = 8098F3hR2= OhData at 809850h = OADh = 173Data at 8098F2h = ODCh = 220LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR4 = 809850hAR1 = 8098F3hR2 = 094ACh = 38,060 'Data at 809850h = OADh = 173Data at 8098F2h = ODCh = 220LUF LV UF N Z V C = 0 0 0 0 0 0 0Example 2MPYI3*--AR4(IRO),R2,R7Before Instruction:AR4 = 8099F8hIRO = 8hR2 = OC8h = 200R7 = OhData at 8099FOh = 32h = 50LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR4 = 8099FOhIRO = 8h'R2 = OC8h = 200R7 = 0271 Oh = 10,000Data at 8099FOh = 32h = 50LUF LV UF N Z V C = 0 0 0 0 0 0 010-121
Syntax MPYI3 sreA, sreB, dsttII ADDI3 sreC, sreD, dst2OperationOperandsIIsreA x sreB -7 dsttsreD + sreC -7 dst2sreAU sreBsreCsreDdsttdst2sretsre2sre3sre4Any two indirect (disp = 0,1 ,IRO,IR1)Any two register (0 :s; Rn :s; 7)register (dt):0= RO1 = R1register (d2):0= R21 = R3registerregisterindirectindirect(Rn, o:s; n:s; 7)(Rn, ° :s; n :s; 7)(disp = 0, 1, IRO, IR1)(disp = 0, 1, IRO, IR1)P parallel addressing modes (0 :s; P :s; 3) .Operation (P Field)00 sre3 x sre4, sre t + sre201 src3 x sret, src4 + sre210 sret x sre2, sre3 + sre411 sre3 x sret, sre2 + sre4Encoding31 2423i isrc1i isrc3iiisrc4IoIDescriptionAn integer multiplication and an integer addition are performed in parallel. <strong>Al</strong>lregisters are read at the beginning and loaded at the end of the execute cycle.This means that if one of the parallel operations (MPVI3) reads from a registerand the operation being performed in parallel (ADDI3) writes to the same register,then MPVI3 accepts as input the contents of the register before it is modifiedby the ADDI3.10-122Assembly Language Instructions
Any combination of addressing modes may be coded for the four possiblesource operands as long as two are coded as indirect and two are register. Theassignment of the source operands srcA - srcDto the src1 - src4fields varies,depending on the combination of addressing modes used, and the P field isencoded accordingly. The assembler may, when not significant, change the orderof operands in commutative operations in order to simplify processing.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unchanged.LV 1 if an integer overflow occurs, unchanged otherwise.UF O.N O.Z O.VC1 if an integer overflow occurs, 0 otherwise.Unaffected.OVM Operation is affected. by OVM bit value.RO.ExampleMPYI3I I ADDI3R7,R4,RO*-AR3, *ARS--(l), R3Before Instruction:R7 = 14h = 20R4 = 64h = 100RO = OhAR3 = 80981 FhAR5 = 80996EhR3 = Oh, Data at 80981 Eh = OFFFFFFCBh = - 53Data at 80996Eh = 35h = 53LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R7 = 14h = 20R4 = 64h = 100RO = 07DOh = 2000AR3 = 80981 FhAR5 = 80996DhR3 = OhData at 80981 Eh = OFFFFFFCBh = - 53Data at ,80996Eh = 35h = 53LUF LV UF N Z V C = 0 0 0 0 0 0 010-123
Example MPYI3 *++ARO(l) ,R5,R7I I STI R2, *-AR3 (1)Before Instruction:ARO = 80995AhR5 = 32h = 50R7 = OhR2 = ODCh = 220AR3 = 80982FhData at 80995Bh = OC8h = 200Data at 80982Eh = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:ARO = 80995BhR5 = 32h = 50R7 = 2710h = 10000R2 = OOCh = 220AR3 = 80982FhData at 80995Bh = OC8h = 200Data at 80982Eh = OOCh = 220LUF LV UF N Z V C = 0 0 0 0 0 0 0.10-125
SyntaxOperationOperandsIIIIMPYI3 sreA, sreB, dst1SUBI3 sreG, sreD, dst2sreA x sreB ~ dst1sreD - sreG ~ dst2sreAU sreBsreGsreDAny two indirect (disp = 0,1 ,IRO,IR1)Any two register (0 ~ Rn ~ 7)dst1dst2register (d1):0= RO1 = R1register (d2):0= R21 = R3sre1sre2sre3sre4registerregisterindirectindirect(Rn, 0 ~ n ~ 7)(Rn, 0 ~ n ~ 7)(disp = 0, 1, IRO, IR1)(disp = 0, 1, IRO, IR1)EncodingP parallel addressing modes (0 ~ P ~ 3)Operation (P Field)31 2423I I I I I I1 I 0 0 I 0 I 1 I 1 I P d1 d~00 sre3 x sre4, src 1 - sre201 sre3 x sre1, sre4 - sre21 ° sre 1 x sre2, src3 - src411 sre3 x sre 1, sre2 - sre4I I I Isrc1src3I I Isrc4DescriptionAn integer multiplication and an integer subtraction are performed in parallel.<strong>Al</strong>l registers are read at the beginning and loaded at the end of the executecycle. This means that if one of the parallel operations (MPVI3) reads from aregister and the operation being performed in parallel (SUBI3) writes to thesame register, then MPVI3 accepts as input the contents of the register beforeit is modified by the SUBJ3.10-126Assembly Language Instructions
Any combination of addressing modes may be coded for the four possiblesource operands as long as two are coded as indirect and two are register. Theassignment ofthe source operands srcA - srcDto the src1 - src4fields varies,depending on the combination of addressing modes used, and the P field isencoded accordingly. The assembler may, when not significant, change the orderof operands in commutative operations in order to simplify processing.Integer overflow occurs when any of the most significant 16 bits of the 48-bitresult differs from the most significant bit of the 32-bit,output value.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unchanged.LV 1 if an integer overflow occurs, unchanged otherwise.UF 1 if an integer underflow occurs, 0 otherwise.N o.Z O.V 1 if an integer overflow occurs, 0 otherwise.C Unaffected.OVM Operation is affected by OVM bit value.RO.ExampleMPYI3I I SUBI3orMPYI3I I SUBI3R2,*++ARO(1),RO*ARS--(IR1), R4, R2*++ARO(1),R2,RO*ARS--( IR1) , R~, R2Before Instruction:R2 = 32h = 50ARO = 8098E3hRO = OhAR5 = 8099FChIR1 = OChR4 = 07DOh = 2000Data at 8098E4h = 62h = 98Data at 8099FCh = 4BOh = 1200LUF LV UF N Z V C = 0 0 0 0 0 0 010-127
After Instruction:R2 = 320h = 800ARO = 8098E4hRO = 0 1324h = 4900AR5 = 8099FOhIR1 = OChR4 = 07DOh = 2000Data at 8098E4h = 62h = 98Data at 8099FCh = 4BOh = 1200LUF LV UF N Z V C = 0 0 0 0 0 0 01 0-128 'Assembly Language Instructions
With BorrowNEGBSyntaxOperationOperandsNEGB src, dsta - src - C ~ dstsrc general addressing modes (G):00 register (Rn, a :::;; n :::;; 27)a 1 direct1 0 indirect1 1 immediatedst register (Rn, a :::;; n :::;; 27)EncodingDescriptionI I I I I I I I I II I I°I I I I I I31 2423 16 15 87,000,010110,G dst srcThe difference of the 0, src, and C operands is loaded into the dstregister. Thedst and src are assumed to be signed integers.CyclesStatus BitsMode BitExampleThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV 1 if an integer overflow occurs, unchanged otherwise.UF o.N 1 if a negative result is generated, a otherwise.Z 1 if a zero result is generated, a otherwise.V 1 if an integer overflow occurs, a otherwise.C 1 if a borrow occurs, a otherwise.OVM Operation is affected by OVM bit value.NEGB RS,R7Before Instruction:R5 = OFFFFFFCBh = - 53R7 = OhLU F LV U F N Z V C = a a a a a 0' 1After Instruction:R5 = OFFFFFFCBh = - 53R7 = 34h = 52LUF LV UF N Z V C = a a a a a a 1RO.10-129
SyntaxOperationOperandsNEGF src, dsto - src --7 dstsrc general addressing modes (G):0 register (Rn, 0 ~ n ~ 7)o 1 direct1 0 indirect1. 1 immediatedst register (Rn, 0 :::; n :::; 7)Encoding87\ • 1 • i • • 24. 23 I •000010111 G src131DescriptionThe difference of the 0 and src operands is loaded into the dst register. Thedst and src operands are assumed to be floating-point numbers.CyclesStatus BitsThese condition flags are modified only if the destination register is R7 -LUF 1 if a floating-point underflow occurs, unchanged otherwise.LV 1 if a floating-point overflow occurs, unchanged otherwise.UF 1 if a floating-point underflow occurs, 0 otherwise.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if a floating-point overflow occurs, 0 otherwise.C Unaffected.RO.Mode BitExampleOVM Operation is not affected by OVM bit value.NEGF *++AR3(2),RlBefore Instruction:AR3 = B09BOOhR1 = 0578400025h = 6.2B125006e + 01Data at B09B02h = 70CBOOOh = 1.4050e + 02LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR3 = B09B02hR 1 = 07F3BOOOOOh = -1.4050e + 02Data at B09B02h = 70CBOOOh = 1 .4050e + 02LUF LV UF N Z V C = 0 0 0 0 0 0 010-130Assembly Language Instructions
SyntaxOperationOperandsNEGF src2, dst1II STF src3, dst2II0 - src2 ~ dst1src3 ~ dst2src2 indirect (disp = 0, 1, IRO, IR1)dst1 register (Rn1, 0 ~ n1 ~ 7)src3 register (Rn2, ° ~ n2 ~ 7)dst2 indirect (disp = 0, 1, IRO, IR1)Encoding31 2423 16 15I I Idst287src2I' I I IDescriptionA floating-point negation and a floating-point store are performed in parallel.<strong>Al</strong>l registers are read at the beginning and loaded at the end of the executecycle. This means that if one of the parallel operations (STF) reads from a registerand the operation being performed in parallel (NEGF) writes to the sameregister, then STF accepts as input the contents of the register before it is modifiedby the NEGF.If src2 and dst2 point to the same location, src2 is read before the write to dst2.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF 1 if a floating-point underflow occurs, ° unchanged otherwise.LV 1 if a floating-point overflow occurs, unchanged otherwise.UF 1 if a floating-point underflow occurs, 0 otherwise.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if a floating-point overflow occurs, 0 otherwise.C Unaffected.OVM Operation is not affected by OVM bit value.RO.10-131
ExampleNEGF *AR4--(1),R7I I STF R2, *++AR5 (1)Before Instruction:AR4 = 8098E 1 hR7 = OhR2 = 0733COOOOOh = 1.797S0e + 02ARS = 809803hData at 8098E1 h = S78400000h = 6.281250e + 01Data at 809804h = OhLUF LV UF N Z V C = 0 0 0' 0 0 0 0A fter Instruction:AR4 = 8098EOhR7 = 0584COOOOOh = - 6.2812S0e + 01R2 = 0733COOOOOh = 1.797S0e + 02ARS = 809804hData at 8098E1 h = 5784000h = 6.281250e + 01Data at 809804h = 733COOOh = 1.797S0e + 02LUF LV UF N Z V C = 0 0 0 0 0 0 010-132Assembly Language Instructions
SyntaxOperationOperandsNEGI sre, dsto - sre --j dstsre general addressing modes (G):o 0 register (Rn, 0 ::; n ::; 27)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0::; n ::; 27)EncodingDescription31 2423 16 15 87 oI III I I I I I I I I I000011000 G srcThe difference of the 0 and sreoperands is loaded into the dstregister. The dstand sre operands are assumed to be signed integers.ICyclesStatus BitsMode BitExampleThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV 1 if an integer overflow occurs, unchanged otherwise.UF o.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if an integer overflow occurs, 0 otherwise.C 1 if a borrow occurs, 0 otherwise.OVM Operation is affected by OVM bit value.NEGI 174,RS (174 = OAEh)Before Instruction:R5 = OOCh = 220LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R5 = OFFFFFF52 = -174LU~ LV UF N Z V C = 0 0 0 1 0 0 1RO.10-133
SyntaxNEGISTIsrc2, dst1src3, dst2OperationOperandsEncodingDescriptionIIo - src2 -7 dst1src3 -7 dst2src2 indirect (disp = 0, 1, IRO, IR1)dst1 register (Rn1, 0 ::;; n1 ::;; 7)src3 register (Rn2, 0 ::;; n2 ::;; 7)dst2 indirect (disp = 0, 1, IRO, IR1)I I Idst2I'87 oI I I, Isrc2An integer negation and an integer store are performed in parallel. <strong>Al</strong>l registersare read at the beginning and loaded at the end of the execute cycle. Thismeans that if one of the parallel operations (STI) reads from a register and theoperation, being performed in parallel (NEGI) writes to the same register, thenSTI accepts as input the contents of the register before it is modified by theNEG!.If src2 and dst2 point to the same location, src2 is read before the write to dst2.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected:LV· 1 if an integer overflow occurs, unchanged otherwise.UF O.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if an integer overflow occurs, 0 otherwise.C 1 if a borrow occurs, ° otherwise.OVM Operation is affected by OVM bit value.RO.10-134Assembly Language Instructions
Example NEGI *-AR3,R2'II STI R2,*AR1++Before Instruction:AR3 = 80982FhR2 = 19h = 25AR 1 = 8098A5hData at 80982Eh = ODCh = 220Data at 8098A5h = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR3 = 80982FhR2 = OFFFFFF24h = - 220AR 1 = 8098A6hData at 80982Eh = ODCh = 220Data at 8098A5h = 19h = 25LUF LV UF N Z V C = 0 0 0 1 0 0 1/10-135
NOP NoSyntaxOperationOp~randsEncodingNOP srcNo ALU or multiplier operations.ARn is modified if src is specified in indirect mode .. src general addressing modes (G):o 0 registe~ (no operation)1 0 indirect (modify ARn, 0 ::; n ::; 7)31 2423 16 15 87 oi isrcIIDescriptionCyclesStatus BitsMode BitExample 1If the src operand is specified in the indirect mode, the specified addressingoperation is performed and a dummy memory read occurs. If the src operandis omitted, no operation is performed.LUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM·bit value.NOPBefore Instruction:PC = 3AhAfter Instruction:PC = 3BhExample 2NOP*AR3--(1)Before Instruction:PC = 5hAR3 = 809900hAfter Instruction:PC = 6hAR3 = 8098FFh10-136Assembly Language Instructions
NormalizeNORMSyntaxOperationOperandsNORM sre, dstnorm (sre) -7 dstsrc general addressing modes (G):o 0 register (Rn, 0 ~ n ~ 7)o 1 direct1 0 indirect1 1 immediateEncoding13\ , 1 ' , , ,24,231000011010Gj 16,15,87j j j jdst _srcDescriptionThe srcoperand is assumed to be an unnormalized floating-point number; i.e.,the implied bit is set equal to the sign bit. The dst is set equal to the normalizedsrc operand with the implied bit removed. The dst operand exponent is set tothe srcoperand exponent minus the size of the left-shift necessary to normalizethe src. The dstoperand is assumed to be a normalized floating-point number.If src (exp) =-128 and sre (man) = 0, then dst=O, Z= 1, and UF = O.lf sre (exp)= -128 and src (man):;t: 0, then dst= 0, Z = 0, and UF = 1. Foral! other casesof the src, if a floating-point underflow occurs, then dst (man) is forced to 0 anddst (exp) =-128. If src (man) = 0, then dst (man) = 0 and dst (exp) =-128. Referto Section 4.6.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF 1 if a floating-point underflow occurs, unchanged otherwise.LV Unaffected.UF 1 if a floating-point underflow occurs, 0 otherwise.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V o.C Unaffected ..OVM Operation is not affected by OVM bit value.RO.10-137
NORM Normalize••••••••••••• :. •••••••••••••••• : ••••• : ..... : ••••••••••••• !.!.:::.:.:;:;:.:.:.!.:.!.:.:.:.'.:,'.:;:.:.'.:.:.:.: ••••• :;: ••• :.:.:.: •• ;:;.;:; ••• ;.;:; ••• ;:; •• : •••••• ;: •••••• ; ••• ;.;-;.; ••• ; ••• ;.;.;:;.; ...... .; ••• ;.; ••••• ; ......... ;.; ••••••• ; ... ; ••• ;.;.;.;.; ••••••••••••••••• ; ............... ; ••••••••••••••••••••••••••.•••••••• ; ................. ;.; ••••••••••••••••••••••••••••••••• ; ..................... ; ••••••• ; ••• ; ................................................................................... ; ••.•••••••••••••• ;.; .............................. ;.; ......... ; •••••••••.• ; ••••• ; •• :.;:;:;:.:.~;:.~.~.~.~;:~.~::;:::;::ExampleNORM Rl,R2Before Instruction:R 1 = 0400003AF5hR2 = 070C800000hLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R 1 = 0400003AF5hR2 = F26BD40000h = 1.12451613e - 04LUF LV UF N Z V C = 0 0 0 0 0 0 010-138Assembly Language Instructions
SyntaxOperationOperandsNOT sre, dst-sre --7 dstsre general addressing modes (G):0 register (Rn, 0 ~ n ~ 27)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0 ~ n ~ 27)Encoding31\ \ , ' \ \ \ 24\23,,o 0 0 0,1 1 0 1 1 GI I \ 16,15,dst .87, IsrcDescriptionThe bitwise logical-complement of the sreoperand is loaded into the dstregister.The complement is formed by a logical-NOT of each bit of the sre operand.The dst and sre operands are assumed to be unsigned integers.CyclesStatus BitsMode BitExampleThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV Unaffected.UF O.N MSB of the output.Z 1 if a zero result is generated, 0 otherwise.V O.C Unaffected.OVM Operation is affected by OVM bit value.NOT @982Ch,R4Before Instruction:DP = BOhR4= OhData at 80982Ch = 5E2FhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:DP = 80hR4 = OFFFFA 1 DOhData at 80982Ch = 5E2FhLUF LV UF N Z V C = 0 0 0 1 0 0 0RO.10-139
NOTIISTI Parallel NOT and STI........... ~.: •••••••••••••••••••••••.••.•••.•.••:•••:.'.:.'.!.!.:::::::::::::;:;:::::::::.:::.:::::::.!.:::.:.:o!o'.:.:.:•••••••:.:.......:.:.:.:•••••••••••••••••• ~ .••:••••••••••• ~.:.: •••••••:••••••••••••:•.::••••:;.••• ~ ••:........................., ............ ~ ...........:.:••••• ~;. ••;.;......!:.;.;•••••.•••;•••;•••••;•••••••••••••;.,.............................................................,;•••••.•••••;.....;.........................;.............;............................... ~.: .....;.:.....,.;..!>...:.;.;..;.:••••.;.......;•••:.....:~••:~••.:o!;~::~:;.. ~:::.:.::;:.~:;o;:;:;:>:;:;:;:;:;SyntaxIINOTSTIsrc2, dst1src3, dst2OperationII-src2 -7 dst1src3 -7 dst2Operandssrc2 indirect (disp = 0, 1, IRO, IR1)dst1 register (Rn1, 0 ~ n1 ~ 7)src3 register (Rn2, 0 ~ n2 ~ 7)dst2 indirect (disp = 0, 1, IRO. IR1)Encoding31 2423 1615i I Idst287 oI I II I src2 IIDescriptionA bitwise logical-NOT and an integer store are performed in parallel. <strong>Al</strong>l registersare read at the beginning and loaded at the end of the execute cycle. Thismeans that if one of the parallel operations (STI) reads from a register and theoperation being performed in parallel (NOT) writes to the same register, thenSTI accepts as input the contents of the register before it is modified by theNOT.If src2 and dst2 point to the same location, src2 is read before the write to dst2.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV Unaffected.UF o.N MSB of the output.Z 1 if a zero result is generated, 0 otherwise.V O.C Unaffected.OVM Operation is not affected by OVM bit value.RO.10-140Assembly Language Instructions
Example NOT *+AR2,R3I 1ST I R 7 , * - - AR 4 (I R 1 )Before Instruction:AR2 = 8099CBhR3 =OhR7 = ODCh = 220AR4 = 809850hIR1 = 10hData at 8099CCh = OC2FhData at 809840h = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR2 = 8099CBhR3 = OFFFFF3DOhR7 = ODCh = 220AR4 = 809840hIR1 = 10hData at 8099CCh = OC2FhData at 809840h = ODCh = 220LUF LV UF N Z V C = 0 0 0 1 0 0 010-141
ORBitwise LULllua'-LJ'SyntaxOperationOperandsEncodingDescriptionOR src, dstdst OR src -7 dstsrc general addressing modes (G):0 register (Rn, 0, ~ n ~ 27)o 1 direct1 0 indirect1 1 immediate (not sign-extended)dst register (Rn, 0 ~ n ~ 27)31 2423 87 oI IsrcII I I I I I I I I I00010 0000 GThe bitwise logical OR between the src and dst operands is loaded into the dstregister. The dst and src operands are assumed to be unsigned integers.ICyclesStatus BitsMode BitExampleThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV Unaffected.UF O.N MSB of the output.Z ,1 if a zero result is generated, 0 otherwise.V O.C Unaffected.OVM Operation is not affected by OVM bit value.OR *++AR1(IR1) ,R2Before Instruction:AR1 = 809800hIR1 = 4hR2 = 012560000hData at 809804h = 2BCDhLUF LV UF N Z V C = 0 0 O' 0 0 0 0After Instruction:AR1 = 809804hIR1 = 4hR2 = 012562BCDhData at 809804h = 2BCDhLUF LV UF N Z V C = 0 0 0 0 0 0 0RO.1 0-142 . Assembly Language Instructions
SyntaxOperationOperandsOR3 sre2, sret, dstsret OR sre2 --7 dstsret three-operand addressing modes (T):0 register (Rn1, 0 n1 ~ 27)o 1 indirect (disp = 0, 1, IRO, IR1)1 0 register (Rn1, 0 ~ n1 ~ 27)1 1 indirect (disp = 0, 1, IRO, IR1)sre2 three-operand addressing modes (T):o 0 register (Rn2, 0 ~ n2 ~ 27)o 1 register (Rn2, 0 ~ n2 ~ 27)1 0 indirect (disp = 0, 1, IRO, IR1)1 1 indirect (disp = 0, 1, IRO, IR 1)dst register (Rn, 0 ~ n ~ 27)Encoding1615(\ , 1 ' , , ,24,23I I I001001011 T src11I I Isrc2DescriptionThe bitwise logical-OR between the sret and sre20perands is loaded into thedstregister. The sret, sre2, and dstoperands are assumed to be unsigned integers.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV Unaffected.UF o.N MSB of the output.Z 1 if a zero result is generated, 0 otherwise.V O.C Unaffected.OVM Operation is not affected by OVM bit value.RO.10-143
OR3 ........;;;.;..?J!.1I::J~~;.;~Pf!!9.c;!.:g.'2'...... ~ ..:,.r;?P.~r~D.q.... ...' .... ........ ..... ..... ....... ...................;.;...;.;...;.;.........;.;.;.......;.;.;...;...;.;...;.;.;.....;.;.;.;..... ... ...;..............;;.............;.;.;.;...;.;ExampleOR3 *++AR1(IR1),R2,R7Before Instruction:AR1 = 809800hIR1 = 4hR2 = 012560000hR7 = OhData at 809804h = 2BCDhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR1 = 809804hIR1 = 4hR2 = 012560000hR7 = 012562BCDhData at 809804h = 2BCDhLUF LV UF N Z V C = 0 0 0 0 0 0 01 0-144 Assembly Language Instructions
SyntaxOperationOperandsOR3 src2, src1, dst1II STI src3, dst2src1 OR src2 ---:; dst1src3 ---:; dst2src1 register (Rn1, a ~ n1 ~ 7)src2 indirect (disp = 0, 1, IRa, IR1)dst1 register (Rn2, a ~ n2 ~ 7)src3 register (Rn3, a ~ n3 ~ 7)dst2 indirect (disp = 0, 1, IRa, IR1)Encoding1 1 1 0 1 0 0 dst1 src1II16 15I I I Isrc3I I I I I Idst2src2A bitwise logical-OR and an integer store are performed in parallel. <strong>Al</strong>l registersare read at the beginning and loaded at the end of the execute cycle. Thismeans that if one of the parallel operations (STI) reads from a register and theoperation being performed in parallel (OR3) writes to the same register, thenSTI accepts as input the contents of the register before it is modified by theOR3.If src2and dst2pointto the same location, src2is read before the write to dst2.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV Unaffected.UF o.N MSB of the output.Z 1 if a zero result is generated, a otherwise.V o.C Unaffected.OVM Operation is not affected by OVM bit value.RO.10-145
OR311STIParallel OR3 and STI.~.·.· ••• ~".y.:.:.·.·.·.·.:.·.·.:.'.:.·.:.:.:.:.:::.:;:;:::::;';:::::::::::::::::::::::::::::::::::::::::::.:.:.:.:.: ••••. : .••.••••••• : ••• : ............. :.: ••••••• :.:.0 ••• :.: ••• : ••••••• :.y.:.:.: ••••• :.:.:.:.:.:.:.:.: ••• ~ •• : •••••• ;:;.;:.:.:;: •• ;:.:.: •••••• ;.;.;.;.;:;.~;.;:.: •• ;:; ••• ; ......... ;.; ••• ; ••• ; ••••••• ;.;.; •• : •••• ;:.:; ... ;::.; ••• ; ••••••• ;.; ••••••••••••• ;.;. .... ;.;.;.;.; ••••• ; ••• ; ••••••••••••••••••• ;.;.;.; ••• ; ........................................................... ; ....................... ; ••• ;.;. •••••••• ;:.: ••• : •••• ;:; •• :: •• :.: •. ::;:;:;:::;~:.:.:::;!;:;:;:;:;:;:;:;.;:;::::::-:;:;::::::::~~Example OR3 *++AR2,R5,R2I I STI R6, *AR1--Before Instruction:AR2 = 809830hR5 = 800000hR2 = OhR6 = ODCh = 220AR1 = 809883hData at 809831 h = 9800hData at 809883h = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR2 = 809831 hR5 = 800000hR2 = 809800hR6 = ODCh = 220AR1 = 809882hData at 809831 h = 9800hData at 809883h = ODCh = 220LUF LV UF N Z V C = 0 0 0 0 0 0 01 0-146 Assembly Language Instructions
SyntaxOperationOperandsPOP dst*SP- - --7 dstdst register (Rn, 0::; n ::; 27)Encoding1615 87 0DescriptionCyclesThe top of the current system stack is popped and loaded into the dst register(32 LSBs). The top of the stack is assumed to be a signed integer. The POPis performed with a postdecrement of the stack pointer. The exponent bits ofan extended precision register (R7-RO) are left unmodified.1Status BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV Unaffected.UF O.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V O. .C Unaffected.OVM Operation is not affected by OVM bit value.RO.ExamplePOPR3Before Instruction:SP = 809856hR3 = 0 12DAh = 4,826Data at 809856h = OFFFFODA4h = - 62,044LUF LV UF N Z V C = 0 0 0 0 0 a 0After Instruction:SP = 809855hR3 = OFFFFODA4h = -62,044Data at 809856h = OFFFFODA4h = - 62,044LUF LV UF N Z V C = 0 0 0 1 0 0 010-147
Syntax, OperationOperands'POPF dst*SP- --7 dst1dst register (Rn, 0 ~ n ~ 7)Encoding1615 87 000001110101DescriptionThe top of the current system stack is popped and loaded into the dst register(32 MSBs). The top of the stack is assumed to be a floating-point number. ThePOP is performed with a postdecrement of the stack pointer. The 8 LSBs ofan extended precision register (R7-RO) are zero filled:CyclesStatus BitsMode BitExampleThese condition flags are modified only if the destination register is R7 -LUF Unaffected.UF O.LV Unaffected.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V O.C Unaffected.OVM Operation is not affected by OVM bit value.POPF R4Before Instruction:SP = 80984AhR4 = 025D2E0123h = 6.91186578e + 00Data at 80984Ah = 5F2C1302h = 5.32544007e + 28LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:SP = 809849hR4 = 5F2C130200h = 5.32544007e + 28Data at 80984Ah = 5F2C1302h == 5.32544007e + 28LUF LV UF N Z V C = 0 0 0 0 0 0 0RO.10-148Assembly Language Instructions
SyntaxOperationOperandsPUSH srcsrc --7 *++SPsrc register (Rn, 0 :::; n :::; 27)Encoding1615 87 000001111001DescriptionCyclesStatus BitsMode BitExampleThe contents of the src register (32 LSBs) arepushed on the current systemstack. The src is assumed to be a signed integer. The PUSH is performed witha preincrement of the stack pointer. The integer or mantissa portion of an extendedprecision register (R7-RO) is saved with this instruction.LUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected;OVM Operation is not a,ffected by OVM bit value.PUSH R6Before Instruction:SP = 8098AEhR6 = 815Bh = 33,115Data at 8098AFh = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:SP = 8098AFhR6 = 815Bh = 33,115Data at 8098AFh = 815Bh = 33,115LUF LV UF N Z V C = 0 0 0 0 0 0 010-149
PUSHF PUSH Floating-Point.: ... ~ .. ~.~~ ..... ~~ .............. :.:.:.: ... :.:;:;:.:;:;:~.::::;:.;:::;:::::.:.;; .:.:;:;:;:.:;.'.:;:;:::,:;:::;:.:: .•..•. :~ .; ....... : .•...•.•........ .: ... ; ... .' ....... : ..... ; ....... : ... :.:;:;.';:;.'.; .' .';.;:;.;.'~ ... ,.~.;.:.: ............ : .... ;: •......• ; ..... ;:;::.;.;.; ..• :: .•.•...•. ::.;.; ... ::;.;.;.::;.;.;.;.;.; .. : ...... ;.; •.... ;.;:; ... ;.;.;:; ... ; .... .'.: .. ; •............ ;.; .... : .. ; .... ::.;.; ..... ; .....•.... :;' .... ;.; •.. ; ... ;.;.;.; ..... ;.; ....... ; ..... :: .. :: ... .'.: ... :; ..... ;: .•.............•..... :;.; ... ; ... ; ...... .' ... :; .. ::: .... ;: .......... ;.;.;.;:; .. :;.;: .. ;.;:::::::::::::::::::::;.::::.:::::::::::::::;:.::.;:;SyntaxOperationOperandsPUSHF srcsrc~ *++SPsrc register (Rn, 0 ::; n ::; 7)Encoding·1615 87 000001111101DescriptionThe contents of the src register (32 MSBs) are pushed on the current systemstack. The src is assumed to be a floating-point number. The PUSH is performedwith a preincrement of the stack pointer. The 8 LSBs of the mantissaare not saved. (Note the difference in R2 and the value on the stack in the examplebelow.)CyclesStatus BitsMode BitLUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM bit value.ExamplePUSHFR2Before Instruction:SP = 809801 hR2 = 025C128081 h = 6.87725854e + 00Data at 809802h = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:SP = 809802hR2 = 025C128081 h = 6.87725854e + 00Data at 809802h = 025C1280h = 6.87725830e + 00LUF LV UF N Z V C = 0 0 0 0 0 0 010-150Assembly Language Instructions
RETlcond',';',';',';',' "SyntaxOperationRETlcondIf cond is true:*SP --~ PC1 --7 ST (GIE).Else, continue.OperandsNoneEncoding31 2423I I I I I I I I I I I I011110000 00IIcond1615 87 aDescriptionA conditional return is performed. If the condition is true, the top of the stackis popped to the PC, and 1 is written to the global interrupt enable (GIE) bit ofthe status register. This has the effect of enabling all interrupts for which thecorresponding interrupt enable bit is a 1.The TMS320C3x provides 20 condition codes that can be used with this' instruction(see Section 10.2 for a list of condition mnemonics, encoding, andflags). Condition flags are set on a previous instruction only when the destinationregister is one of the extended-precision registers (R7-RO) or when oneof the compare instructions (CMPF, CMPF3, CMPI, CMPI3, TSTB, or TSTB3)is executed.CyclesStatus BitsMode Bit4LUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM bit value.10-151
ExampleRETINZBefore Instruction:PC = 456hSP = 809830hST= OhData at 809830h = 123hLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:PC = 123hSP = 80982FhST = 2000hData at 809830h = 123hLUF LV UF N Z V C = 0 0 0 0 0 0 010-152 Assembly Language Instructions
Return From SubroutineRETScondSyntaxOperationOperandsRETScondIf cond is true:*SP---7 PC.Else, continue.NoneEncoding31 2423 16 15 87 0j jcondDescriptionA conditional return is performed. If the condition is true, the top of the stackis popped to the PC.The TMS320C3x provides 20 condition codes that can be used with this instruction(see Section 10.2 for a list of condition mnemonics, encoding, andflags). Condition flags are set on a previous instruction only when the destinationregister is one of the extended-precision registers (R7-RO) or when oneof the compare instructions (CMPF, CMPF3, CMPI, CMPI3, TSTB, orTSTB3)is executed.CyclesStatus BitsMode BitExample4LUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM bit value.RETSGEBefore Instruction:PC = 123hSP = 80983ChData at 80983Ch = 456hLUF LV UF N Z V C = 0 0 0 0 0 0 '0After Instruction:PC = 456hSP = 80983BhData at 80983Ch = 456hLUF LV UF N Z V C = 0 0 0 0 0 0 010-153
RNDRound F/n,r=1tinn-P'nintSyntaxRND sre t dstOperationOperandsrnd (sre) -7 dstsre general addressing modes (G):o 0 register (Rn, 0 ~ n ~ 7)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0 ~ n ~ 7)Encoding87IsrcIDescriptionThe result of rounding the sre operand is loaded into the dst register.The sreoperand is rounded to the nearest single-precision floating-point value. If thesre operand is exactly half-way bet'ween two single-precision values, it isrounded to the most positive of those values.Cycles.Status BitsMode BitExampleThese condition flags are modified only if the destination register is R7 -LUF 1 if a floating-point underflow occurs, unchanged otherwise.LV 1 if a floating-point overflow occurs, unchanged otherwise.UF 1 if a floating-point underflow occurs, 0 otherwise.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if a floating-point overflow occurs, 0 otherwise.C Unaffected.OVM Operation is affected by OVM bit value.RND R5,R2Before Instruction:R5 = 0733C16EEFh = 1.7975559ge + 02R2 = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R5 = 0733C16EEFh = 1.7975559ge + 02R2 = 0733C16FOOh = 1.79755600e + 02LUF LV UF N Z V C = 0 0 0 0 0 0 0RO.10-154Assembly Language Instructions
ROLeSyntaxOperationOperandsROLC dstdst left-rotated 1 bit through carry bit --7 dstdst register (Rn, 0 ~ n ~ 27)Encoding31 2423 1615 87 0DescriptionThe contents of the dst operand are left-rotated one bit through the carry bitand loaded into the dstregister. The MSB is rotated to the carry bit, at the sametime the carry bit is transferred to the LSB.Rotate left through carry bit: .
Exampie2ROLe R3Before Instruction:R3 = 80004281 hLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R3 = 00008502hLUF LV UF N Z V C = 0 0 0 0 0 0 110-157
RORRotateSyntaxOperationOperandsROR dstdst right-rotated 1 bit through carry bit ~ dstdst register (Rn, 0:::; n :::; 27)Encoding1615 87 0DescriptionThe contents of the dst operand are right-rotated one bit and loaded into thedst register. The LSB is rotated into the carry bit and also transferred into theMSB.Rotate right:CyclesStatus BitsMode BitExampleThese condition flags are modified only if the destination register is R7 - RO.LUF Unaffected.LV Unaffected.UF o.N MSB of the output.Z 1 if a zero output is generated, 0 otherwise.V O.C Set to the value of the bit rotated out of the high-order bit. Unaffectedif dst is not R7 - RO.OVM Operation is not affected by OVM bit value.ROR R7Before Instruction:R7 = 00000421 hLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R7 = 8000021 OhLUF LV UF N Z V C = 0 0 0 1 0 0 110-158Assembly Language Instructions
SyntaxOperationOperandsRORC dstdst right-rotated 1 bit through carry bit ~ dstdst register (Rn, 0 ::; n ::; 27)Encoding1615 87 0DescriptionThe contents of the dstoperand are right-rotated one bit through the status register'scarry bit. This could be viewed as a 33-bit shift. The carry bit value is rotatedinto the MSB of the dst, while at the same time, the dst LSB is rotated intothe carry bit.Rotate right through carry bit:r=:----c () dstjCyclesStatus BitsMode BitExampleThese condition flags are modified only if the destination register is R7 - RO.LUF Unaffected.LV Unaffected.UF O.N MSB of the output.Z 1 if a zero output is generated, 0 otherwise.V O.C Set to the value of the bit rotated out of the high-order bit. If dst is notR7 - RO, then C is shifted in but not changed.OVM Operation is not affected by OVM bit value.RORe R4Before Instruction:R4 = 80000081 hLUF LV UF N Z V C = 0 0 0 1 0 0 0After Instruction:R4 = 40000040hLUF LV UF N Z V C = 0 0 0 0 0 0 110-159
RPTBSyntaxOperationOperandsEncodingRPTB srcsrc~ RE1 ~ ST (RM)Next PC ~ R8src long-immediate addressing mode31 2423 16 15I I I87I I I IsrcDescriptionCyclesStatus BitsMode BitRPTB allows a block of instructions to be repeated a number of times withoutany penalty for looping. This instruction activates the block repeat mode of updating-thePC. The src operand is a 24-bit unsigned immediate value that isloaded into the repeat end address (RE) register. A 1 is written into the repeatmode bit of status register 8t (RM) to indicate that the PC is being updated inthe repeat mode. The address of the next instruction is loaded into the repeatstart address (RS) register.4LUFLVUFNZVCUnaffected.Unaff€cted.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM bit value.ExampleRPTB127hBefore Instruction:PC = 123hST= OhRE = OhR8 = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:PC = 124h8T = 100hRE = 127hRS = 124hLUF LV UF N Z V C = 0 0 0 0 0 0 01 0-160 Assembly Language Instructions
SyntaxOperationOperandsEncodingRPTS srcsrc~ RC1 ~ ST (RM)1~SNext PC ~ RSNext PC ~ REsrc general addressing modes (G):0 registero 1 direct1 0 indirect1 1 immediate3111 1 1 1 1 124 1 23 111 1 10 11 1116115,000100111 G. .1187 o1 1, IsrcDescriptionThe RPTS instruction allows a single instruction to be repeated a number oftimes without any penalty for looping. Fetches can ,also be made from the instructionregister (IR), thus avoiding repeated memory access.The src operand is loaded into the repeat counter (RC). A 1 is written into therepeat mode bit of the status register 8T (RM). A 1 is also written into the repeatsingle bit (8). This indicates that the program fetches are to be performed onlyfrom the instruction register. The next PC is loaded into the repeat end address(RE) register and the repeat start address (RS) register.Forthe immediate mode, the srcoperand is assumed to be an u'nsigned integerand is not sign-extended.CyclesStatus BitsMode Bit4LUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM bit value.10-161
RPTSRepeat Single;:;:~~:;:;::::!;:::;=;!
Signal, Interlocked~;~.=;:;:::;:;::':::::::;:;:~:;:;:;:;:::::;:;:::::::;:;:;:;:~::;:::::::;:::::;:::;:~:;:::;:::::::::;:;::::.::;:;:;:;.;:;:;:::::::::::::::::::::;'::::::::;:::::::;';:::;0;:::::::::::::::::::;:::::.::::::::::.::;.::::: .;.;::.::;.::::::::;:::::::;.;::::::::.:::::::::.::: .;.:.;.:.;.:.;.;::::::::::::-.::.;:::;.;:::::;0.:::::;.;.;::::::::::::.::.:;.;.:::.;:.:::;.;.:::.;: •••. ;: •• ;:::::;·.:.:.·;:;· ... :;·.:.:.·.·.:::::::.:;·.w::.·.:.:.:: •••• : ••••• :.: ••• ' ••• :.: ................. :.:.: ........... : ... : ••••••• !O:.: ••• :;:::::.: ••••• :.:.::: ••••• :.:.:.:.:;.;:.:.:::::::::::::::::::::;:::::::::::::::::::::::::SIGISyntaxOperationOperandsEncodingSIGISignal interlocked operation.Wait for interlock acknowledge.Clear interlock.None31 24 23 16 15 8 7 010' 0 ' 01 ' 0' l' l' 0' 01 0' 0 I 0' 0' 0' 0 ' 0' 0' 0 ' 0 ' 0' 0' 0' 0' 0' 0' 0' 0' 0' 0' 0' 0' 0 IDescriptionAn interlocked operation is signaled over XFO and XF1 . After the interlockedoperation is acknowledged, the interlocked operation ends. SIGI ignores theexternal ready signals. Refer to Section 6.4 on page 6-10 for detailed information.CyclesStatus BitsMode BitLUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM bit value.10-163
STF Store Floating-Point;o.:-:.;.»;S";.;.;o;.... ~;:;:;o: ......:;.;:;~;:.:;::.;:;:;:;:;:;:~~;:::::;:;:::;::y.;:;:~;:;:;~:.:;:;.;:;:;:.:;.;.;•••;:;.;o••"•....·;·;:::=:;:;:-~:s:;:;:;:;:;:;:::;-;:;:~o;"..·~;·;·;:~v;v:-:~:;-:-:;·;y:-;o~..:.:-:»:-::.;.;..;o;o;o;.:.;.;.:.;.::;::.;.;:;.:.;.;.;:;•••;.;.;.;.;.;o;...;.;.;.;o;.. o;o;.;.;o ••;.;.;•• ~; ...;.;.;..;.;.;.;o.... ~;.;o;o;.; •• ~;.; •• ~;.;.;.;.;.;.;.;.;o;.;.:.;.;.;.; •• ~ ••;.;•• ~;.; ...;..';.:...;.;•••;.;...;.;0;.. 0;0;'1' .............;.........:...;0;.............: .......; ...;.;..,;.;...; .....; ..;:...;0;,;,::::::::;.;:;;:.. :=:;.;:;.;:;.;.;:~O;:O;:;::.,..:;:;:::::::::;SyntaxOperationOperands.STF src, dstsrc~ dstsrc register (Rn, 0 ~ n ~ 7)dstgeneral addressing modes (G):o 1 direct1 0 indirectEncoding(\ 1 1 1 1 1 /4123000101000G11615i iiIisrc .87 oi idst1 IDescriptionThe src register is loaded into the dst memory location. The src and dst operandsare assumed to be floating-point numbers.CyclesStatus BitsMode BitExampleLUF Unaffected.LV Unaffected.UF Unaffected.N Unaffected.Z Unaffected.V Unaffected.C Unaffected.OVM Operation is not affected by OVM bit value.STF R2,@98<strong>Al</strong>hBefore Instruction:DP = 80hR2 = 052C501900h = 4.30782204e + 01Data at 8098A 1 h = OhLUF LV UF N Z V C=;O 0 0 0 0 0 0After Instruction:DP = 80hR2 = 052C501900h = 4.30782204e + 01Data at 8098A 1 h = 52C5019h = 4.30782204e + 01LUF LV UF N Z V C = 0 0 0 0 0 0 010-164Assembly Language Instructions
SyntaxOperationOperandsSTFI src, dstsrc --7 dstSignal end of interlocked operation.src register (Rn, 0 ~ n ~ 7)Encodingdstgeneral addressing modes (G):o 1 direct1 0 indirectr ', I ' , , , 24,23000101001 G187IdstIDescriptionCyclesStatus BitsMode BitThe src register is loaded into the dst memory location. An interlocked operationis signaled over pins XFO and XF1. The srcand dstoperands are assumedto be floating-point numbers. Refer to Section 6.4 on page 6-10 for detailed information.LUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.DVM Operation is not affected by OVM bit value.ExampleSTFIR3,*-AR4Before Instruction:R3 = 0733COOOOOh = 1.79750e + 02AR4 = 80993ChData at 80993Bh = Oh'LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R3 = 0733COOOOOh = 1.79750e + 02AR4 = 80993ChData at 80993Bh = 733COOOh = 1.79750e + 02LUF LV UF N Z V C = 0 0 0 0 0 0 010-165
SyntaxSTF sre2, dst2II STF sre1, dst1OperationIIsre2~ dst2sre1 ~ dst1Operandssre1 register (Rn1, 0 :::; n1 :::; 7)dst1 indirect (disp = 0, 1, IRO, IR1)sre2 register (Rn2, 0 :::; n2 :::; 7)dst2 indirect (disp = 0,1, IRO, IR1)Encoding31 2423 1615I I Idst187 oI I II', Idst2DescriptionCyclesStatus BitsMode BitExampleTwo STF instructions are executed in parallel. Both sre1 and sre2are assumedto be floating-point numbers.LUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected·.OVM Operation is not affected by OVM bit value.STFI I STFR4, *AR3-R3, *++ARSBefore Instruction:R4 = 070C800000h = '1.4050e + 02AR3 = 809835hR3 = 0733COOOOOh = 1.79750e + 02AR5 = 8099D2hData at 809835h = OhData at 8099D3h = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R4 = 070C800000h = 1.4050e + 02AR3 = 809834hR3 = 0733COOOOOh = 1.79750e + 02AR5 = 8099D3hData at 809835h = 070C8000h = 1.4050e + 02Data at 8099D3h = 0733COOOh = 1.79750e + 02LUF LV UF N Z V C = 0 0 0 0 0 0 010-166Assembly Language Instructions
SyntaxOperationOperandsSTI src, dstsrc --7 dstsrc register (Rn, 0 :::; n :::; 27)Encodingdstgeneral addressing modes (G):o 1 direct1 0 indirect(\ , 1 ' , , ,24,23000101010 G187 oI I, IdstDescriptionCyclesStatus BitsMode BitExampleThe src register is loaded into the dst memory location. The src and dst operandsare assumed to be signed integers.LUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation· is not affected by OVM bit value.STI R4,@982BhBefore Instruction:DP = 80hR4 = 42BD7h = 273.367Data at 80982Bh = OE5FCh = 58,876LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:DP = 80hR4 = 42BD7h = 273,367Data at 80982Bh = 428D7h = 273,367LUF LV UF N Z V C = 0 0 0 0 0 0010-167
STIIStore Integer, Interlocked;~".~.~.: ••• ' ••••• '.:.~.~.:.:.~;:::.:;:::::;:;:;:;:;:.:;:;:.:;';:;~.:::::::;::=-:::::::.:::::::;:::.'::;:::;:':':.:.:.:.:.:.!.:..;:::.: ••• :.:.:.: ••••••••••••• : ••• : ••••••••••••• =-...... : .....•........ ;:.:;.;:::::;.;.;.;::::::::.:~ •.. ;~.:.::: •• ~.;:. ... ;:;.:.;.;.; .. :;:;:;.;:::;.:.~::;·;·::;:::::b:.·::.:.·::;·::::;·.·;·.:.:.·;·.·.·;·.·.: ............ ;.;.; ••• :: •• ; ••• ; ••• ;.;:..; ••••• ; ••••••••••••••••••••••• ; ••••••••••• ; ••••••••••••••••••••••••••••••••• ; ......... ; ....................... ; ••• ;:;.; ....... ; ••• ;.; ..... : ...... : •• ;: •••••••• ;.;.: •• :::;.;:::::;.;::.;.;.;::y •• ;.;:::::::;.;.;:::::::;::::::::::::::::SyntaxOperationOperandsSTII src, dstsrc~ dstSignal end of interlocked operation.src register (Rn, 0 :::;; n :::;; 27)dstgeneral addressing modes (G):o 1 direct1 0 indirectEncodingDescriptionCyclesStatus BitsMode Bit87 oI IdstIThe src register is loaded into the dst memory location. An interlocked operationis signaled over pins XFO and XF1. The srcand dstoperands are assumedto be signed integers. Refer to Section 6.4 for detailed information.LUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM bit value.IExampleSTIIRl,@98AEhBefore Instruction:DP = 80hR1 = 78DhData at 8098AEh = 25ChAfter Instruction:DP = 80hR1 = 78DhData at 8098AEh = 78Dh10-168Assembly Language Instructions
SyntaxSTI src2, dst2II STI src1, dst1OperationIIsrc2-7 dst2src1 -7 dst1Operandssrc1 register (Rn1, a ~ n1 ~ 7)dst1 indirect (disp = 0,1, IRa, IR1)src2 register (Rn2, 0 ~ n2 ~ 7)dst2 indirect (disp = 0, 1, IRa, IR1)EncodingI I Idst1r'I I Idst2DescriptionCyclesStatus BitsMode BitExampleTwo integer stores are performed in parallel. If both stores are executed to thesame address, the value written is that of STI src2, dst2.LUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM bit value.STI RO,*++AR2(IRO)I I STI R5, *AROBefore Instruction:RO = ODCh = 220AR2 = 809830hIRa = 8hR5 = 35h = 53ARO = 8098D3hData at 809838h = OhData at 8098D3h = OhLUF LV UF N Z V C = 0 0 0 0 0 0 010-169
STIIISTIParallel STI and STI.......:.:.........:;•••••.:.................:.:;•• :;~•••;:«;:::::::;:;:;:::::::::::::::.:::::::::::::::::::.:-:::;0.0...:.-.:••.:.:0".............. O,: ... y.o. ...................................""........ Y. ....;.N.;:~;...................:...;.;.....;O".......•.....·.y.·.·.·....;·.·;·.....·........;y:·;·,.,;.....:....·.w.·.......·......... y ••••;.....;.. ~ .......;•••;.;.;•••:•••;.........;.;.............;.............;•••••••,v•.;.••;.o.;.........;.......;.;.;...... ~ .............;.;.....;...;.;.;.;..:.;.,;.;.........;...;.;...:.:.....;-;~:;.,;.~.;!>:;:;:;:;~:;.:;:~~::;:;:;:~:;~After Instruction:RO= ODCh = 220AR2 == 809838hIRO = 8hR5 = 35h = 53ARO = 8098D3hData at 809838h = ODCh = 220Data at 8098D3h = 35h = 53LUF LV UF N Z V C = 0 0 0 0 0 0 01 0-170 Assembly Language Instructions
SyntaxOperationOperandsEncodingSUBB src, dstdst- src- C ~ dstsrc general addressing modes (G):o 0 register (Rn, 0 ~ n ~ 27)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0 ~ n ~ 27)r' , I ' , , ,24,23000101101 G187i isrcDescriptionThe difference of the dst, src, and C operands is loaded into the dst register.The dst and src operands are assumed to be signed integers.CyclesStatus BitsMode BitExampleThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV 1 if an integer overflow occurs, unchanged otherwise.UF O.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if an integer overflow occurs, 0 otherwise.C 1 if a borrow occurs, 0 otherwise.OVM Operation is affected by OVM bit value.SUBB *ARS++(4),RSBefore Instruction:AR5 = 809800hR5 = OFAh = 250Data at 809800h = OC7h = 199LUF LV UF N Z V C = 0 0 0 0 0 0 1After Instruction:AR5 = 809804hR5 = 032h = 50Data at 809800h = OC7h = 199LUF LV UF N Z V C = 0 0 0 0 0 0 0RO.10-171
SyntaxOperationOperandsSUBB3 sre2, sret, dstsre1 - sre2- C ~ dst 'sre1 three-operand addressing modes (T):0 register (Rn1, 0 ~ n1 ~ 27)o 1 indirect (disp = 0, 1, IRO, IR1)1 0 register (Rn1, 0 ~ n1 ~ 27)1 1 indirect (disp'= 0,1, IRO, IR1)sre2three-operand addressing modes (T):00 register(Rn2, 0 ~ n2 ~ 27)o 1 register (Rn2, 0 ~ n2 ~ 27)1 0 indirect (disp = 0, 1, IRO, IR1)1 1 indirect (disp = 0, 1, IRO, IR1)dst register (Rn, 0 ~ n ~ 27)EncodingDescriptionCyclesl"IIiIl"I31 2423 1615 87 0I I,001,001100,I I I I I I I I I IT dst src1 src2The difference of the sret and sre2 operands and the C (carry) flag is loadedinto the dst register. The sre1, sre2, and dst operands are assumed to besigned integers.1Status BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV 1 if an integer overflow occurs, unchanged otherwise.UF O.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if an integer overflow occurs, 0 otherwise.C 1 if a borrow occurs, 0 otherwise.OVM Operation is affected by OVM bit value.RO.10-172Assembly Language Instructions
Subtract Integer With Borrow, 3-0perand SUBB3;:.:::::::;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;:;:;::!;:::::::;:;:::;:;:::;:;:;:::::;:::;O):;O):~;:::;~;:;:;:;~;.;:;...;,.. ~;~.o!::;:::.:.:: •.•.y""~";:::;:;:::::;:;:':'":....;•••••;:;.;:;~••:::::::::;.....;........:;.. ~.~ .........................:.~......................................................... ~ ••...•.......•••••.....·N.·.·.............·...·.....•...·...........·.·••...·.y... ~·6 ....•..... ~ ..·.·.:.:.:.·.:.:.:.:;:.:.:.:.:.:.:.:::::.:::::.:;:;::::::::::::::::::::::::::::::::::::::::::,;:ExampleSUBB3 RS,*ARS++(IRO),ROBefore Instruction:AR5 = 809800hIRO = 4hR5 = OC7h = 199RO = OhData at 809800h = OFAh = 250LUF LV UF N Z V C = 0 0 0 0 0 0 1After Instruction:AR5 = 809804hIRO = 4hR5 = OC7h = 199RO = 32h = 50Data at 809800h = OFAh = 250LUF LV UF N Z V C = 0 0 0 0 0 0 010-173
SyntaxOperationOperandsSUBC src, dstIf (dst- src;;::'O):(dst- src« 1) OR 1 -? dstElse:dst« 1 -? dstsrc general addressing modes (G):0 register (Rn, 0 ~ n ~ 27)o 1 direct1 0 indirect1 1 immediateEncodingdst register (Rn, a ~ n ~ 27)31 2423Iii Iii iii I000101110G16 15 87isrciDescriptionThe srcoperand is subtracted from the dstoperand. The dstoperand is loadedwith a value dependent upon the resultofthe subtraction. If (dst-src) is greaterthan or equal to zero, then (dst- src) is left-shifted one bit, the least significantbit is set to 1 , and the result is loaded into the dst register. If (dst - src) is lessthan zero, dstis left-shifte-d one bit and loaded into the dstregister. The dstandsrc operands are assumed to be unsigned integers.SUBC may be used to perform a single step of a multibit integer division. Seesubsection 11.3.4 for a detailed description.CyclesStatus BitsMode BitLUFLVUFNZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM bit value.I10-174Assembly Language Instructions
Subtract Integer Conditionally SUBC::;:;:::::;:::::::;:;:::::;:::;:::::;:::::::::::::::::::::::::::::::::::::.:::::::::::::;:::::::;:::::;:::::::::.:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;:::;:;:::::::;::.;:.:;:::::::::::::.:::::;.;:::::.:::::::::::::::::::::::::::;.;:::::;.;.;:.:::::::::::::;.;',:;';:::::.:.:::.'.:: ;.;.;.;:::;.;:::;..:....;:;.;:...:;.;:;..:....::;.;:.:.....:.....:...................................................................................................................................................:.:.:.•..•:.:.............:.:.:.:.:...:.:.:;..:...:::.:;:::::;:.:;:::::::::::::;:::;:Example 1SUBC@98C5h,RlBefore Instruction:DP = BOhR1 = 04F6h = 1270Data at B098C5h = 492h = 1170LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:DP = BOhR1 = OC9h = 201Data at B09BC5h = 492h = 1170LUF LV UF N Z V C = 0 0 0 0 0 0 0Example 2SUBC 3000,RO(3000 = OBB8h)Before Instruction:RO = 07DOh = 2000LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:RO = OFAOh = 4000LUF LV UF N Z V C = 0 0 0 0 0 0 010-175
SUBF3Subtract Floating-Point, 3-0perand~; ...;.:.:.:-:~.;~~~y,;.;".",:.::;~.:..~~::-.:::::;:-.. /.-:::::-.:;:,=::::::: :::;:::::::::::;:;::::y.;:::;:;:~;:;:::::~::;.::;o••••;••:;o...:;:;.;.;.;v;:............;o..;o;.;~••••;.;.;•••••;o;o;o;o;.;.;o;o.::•••;.............;o;o::-:;.....;.;o••••;.............;.....;.:.;::~...-:;0;.:.....;.;.;.;0••;.;0;0;.;.:.:.:.;.;0;0;.;.;.;.;.;.;.;.;0;.;0;0;.;......»:-;0;0;.;0;.;.;.;.;0;.:0;.:.;.;.;0;.;0;.;.;0;.;.;.;.;.;•••;•• 0;.;.;0;.;.; ...;.;0;.';•••;0;.:...;-;..-.;000:-;.;...;0;.....:0;.;:;:;0;.:...:.;.;.::;.;o;...;o;.:.;:;o;.:.:.:o;.;.;:~~o;:::;::::or.:~O;':... ;:::;y.:;y.;:,,:::::;:~/,.(o:>Example 1SUBF3*ARO--(IRO),*AR1,R4Before Instruction:ARO = 809888hIRO = 80hAR1 = 809851 hR4 = OhData at 809888h = 70C8000h = 1.4050e + 02Data at 809851 h = 733COOOh = 1.79750e + 02LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:ARO = 809808hIRO = 80hAR1 = 809851 hR4 = 51 DOOOOOOh = 3.9250e + 01Data at 809888h = 70C8000h = 1.4050e + 02Data at 809851 h = 733COOOh = 1.79750e + 02LUF LV UF N Z V C = 0 0 0 0 0 0 0Example 2SUBF3R7,RO,R6Before Instruction:R7 = 57B400000h = 6.281250e + 01RO = 34C200000h = 1.27578125e + 01R6 = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R7 = 57B400000h = 6.281250e + 01RO = 34C200000h = 1.27578125e + 01R6=587C80000h= - 5.00546875e + 01LUF LV UF N Z V C = 0 0 0 0 1 0 010-178Assembly Language Instructions
SyntaxSUBF3 src1, src2, dst1II STF src3, dst2OperationIIsrc2- src1 -4 dst1src3 -4 dst2Operandssrc1 register (Rn1, 0 ::; n1 ::; 7)src2 indirect (disp = 0,1, IRO, IR1)dst1 register (Rn2, 0 ::; n2 ::; 7)src3 register (Rn3, 0 ::; n3 ::; 7)dst2 indirect (disp = 0, 1, IRO, IR1)Encoding31I i I Iii i,11,1,01012423 1615 87 0I i i I i i i i I i i i I i i i idst1 src1 src3 dst2 src2IDescriptionA floating-point subtraction and a floating-point store are performed in parallel.<strong>Al</strong>l registers are read at the beginning and loaded at the end of the executecycle. This means that if one of the parallel operations (STF) reads from a registerand the operation being performed in parallel (SUBF3) writes to the sameregister, then STF accepts as input the contents of the register before it is modifiedby the SUBF3.If src3 and dst1 point to the same location, src3 is read before the write to dst1.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF 1 if a floating-point underflow occurs, unchanged otherwise.LV 1 if an floating-point overflow occurs, unchanged otherwise.UF 1 if a floating-point underflow occurs, 0 otherwise,N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if an floating-point overflow occurs, 0 otherwise.C Unaffected.OVM Operation is not affected by OVM bit value.RO,10-179
ExampleSUBF3II STFRl,*-AR4(IR1),ROR7,*+AR5(IRO)Before Instruction:R1 = 057B400000h = 6.28125e + 01AR4 = 8098B8hIR1 = 8hRO = OhR7 = 0733COOOOOh = 1.79750e + 02AR5 = 809850hIRO = 10hData at 8098BOh = 70C8000h = 1.4050e + 02Data at 809860h = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R1 = 057B400000h = 6.28125e + 01AR4 = 8098B8hIR1 = 8hRO = 061 B600000h = 7.768750e + 01R7 = 0733COOOOOh = 1.79750e + 02AR5 = 809850hIRO = 10hData at 8098BOh = 70C8000h = 1.4050e + 02Data at 809860h = 733COOOh = 1.79750e + 02LUF LV UF N Z V C = 0 0 0 0 0 0 010-180Assembly Language Instructions
SyntaxOperationOperandsSUBI3 src2, src1, dstsrc 1 - src2 ~ dstsrc1 three-operand addressing modes (T):o 0 register (Rn1, O·~ n1 ~ 27)o 1 indirect (disp = 0,1, IRO, IR1)1 0 register (Rn1, 0 :::;; n1 ~ 27)1 1 indirect (disp = 0, 1, IRO, IR1)src2 three-operand addressing modes (T):o 0 register (Rn2, 0 ~ n2 ~ 27)° 1 register (Rn2, 0 ~ n2 ~ 27)1 ° indirect (disp = 0, 1, IRO, IR1)1 1 indirect (disp = 0, 1, IRO, IR1)dst register (Rn, 0 ~ n ~ 27)EncodingI " I II I I I II I I31 2423 16 15 87 0.001,001110,I I I I I I I I I IT dst src1 src2DescriptionThe difference of the src1 operand minus the src2 operand is loaded into thedstregister. The src1, src2, and dstoperands are assumed to be signed integers.CyclesStatus BftsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV 1 if an integer overflow occurs, unchanged otherwise.UF O.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if an integer overflow occurs, ° otherwise.C 1 if a borrow occurs, 0 otherwise.OVM Operation is affected by OVM bit value.RO.10-182Assembly Language Instructions
Example 1SUBI3R7,R2,ROBefore Instruction:R2 = 0866h = 2150R7 = 0834h = 2100RO = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R2 = 0866h = 2150R7 = 0834h = 2100RO = 032h = 50LUF LV UF N Z V C = 0 0 0 1 0 0 0Example 2SUBI3 *-AR2(1),R4,R3Before Instruction:AR2 = 80985EhR4 = 0226h = 550R3 = OhData at 80985Dh = ODCh = 220LUF LV UF N Z V C = 0 0 0 0 0 0 0'After Instruction:AR2 = 80985EhR4 = 0226h = 550R3 = 014Ah = 330Data at 80985Dh = ODCh = 220LUF LV UF N Z V C = 0 0 0 0 0 0 010-183
SyntaxSUBI3 src1, src2, dst1II STI src3, dst2OperationIIsrc2 - src1 ~ dst1src3 ~ dst2Operandssrc1 register (Rn1, ° ~ n1 ~ 7)src2 indirect (disp = 0, 1, IRO, IR1)dst1 register (Rn2, ~ n2 ~ 7)src3 register (Rn3, ° ~ n3 ~ 7)dst2 indirect (disp = 0, 1, IRO, IR1)Encodingiisrc116 15iii isrc3idst2iisrc2iIoIDescriptionAn integer subtraction and an integer store are performed in parallel. <strong>Al</strong>l registersare read at the beginning and loaded at the end of the execute cycle. Thismeans that if one of the parallel operations (STI) reads from a register and theoperation being performed in parallel (SUBI3) writes to the same register, thenSTI accepts as input the contents of the register before it is modified by theSUBI3.If src3 and dst1 point to the same location, src3 is read before the write to dst1.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV 1 if an integer overflow occurs, unchanged otherwise.UF 0.N 1 if a negative result is generated, ° otherwise.Z 1 if a zero result is generated, ° otherwise.V 1 if an integer overflow occurs, ° otherwise ..C 1 if a borrow occurs, ° otherwise.OVM Operation is affected by OVM bit value.RO.10-184Assembly Language Instructions
Example SUBI3 R7,*+AR2(IRO),RlI I STI R3,*++AR7Before Instruction:R7 = 14h = 20AR2 = 80982FhIRO = 10hR1 = OhR3 = 35h = 53AR7 = 80983BhData at 80983Fh = ODCh = 220Data at 80983Ch = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R7 = 14h = 20AR2 = 80982FhIRO = 10hR1 = OC8h = 200R3 = 35h = 53AR7 = 80983ChData at 80983Fh = ODCh = 220Data at 80983Ch = 35h = 53LUF LV UF N Z V C = 0 0 0 0 0 0 010-185
Subtract Reverse Floating-Point SUBRF~;:'::;:::;:;:;:;:;:;:;:;:::;:;:;:;:;:::;:;:;:;:::::;:;:;:;:;:;:::::::::::::;:::;:::;:::;:::;:;:::::::::::::.:;:.:.:.:;.;:;:;.;:;:;:::;:::::::::;:;:;:::;.::;:;:: ..:::::;••:::::;.;:::::::::::::::::::;:::::::.:;:;.::::.:;.;:::::.::;:;.;:;•••::::.:;:~;.;.;.::;:;.;.;::.;•••••;:;:;.;•••••••;.;.;.;••:;•••••;.;...;.;::.;.....;:;.;•••; •••;•••• 0;0; •••;...;:;.;.........;.;...............................••...·.·.·.·.·.·.·.·.:.·.·.·.·........ N.·.·.·.·.· .....·.....·.·.........·.............................................................:..... !>.;: ..... : ••• :;:.:.:.:;:;:;~::.::::;:;:;:;:;:;:.:::;:;:::;:::;:;:;:;:;:::SyntaxOperationOperandsSUBRF sre, dstsre - dst ~ dstsregeneral addressing modes (G):o 0 register (Rn, 0 ~ n ~ 7)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0 ~ n ~ 7)Encoding3 \ 1 1 1 1 1 1 24123000110010 G src11871 1DescriptionThe difference of the sreoperand minus the dstoperand is loaded into the dstregister.The dstand sreoperands are assumed to be floating-point numbers.CyclesStatus BitsMode BitExampleThese condition flags are modified only if the destination register is R7 -LUF 1 if a floating-point underflow occurs, unchanged otherwise.LV 1 if a floating-point overflow occurs, unchanged otherwise.UF 1 if a floating-point underflow occurs, 0 otherwise.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if a floating-point overflow occurs, 0 otherwise.C Unaffected.OVM Operation is not affected by OVM bit value.SUBRF @9905h,R5Before Instruction:DP = 80hRS = OS7B400000h = 6.2812S0e + 01Data at 80990Sh = 733COOOh = 1 .797S0e + 02LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:DP = 80hRS = 0669EOOOOOh = 1.16937S00e + 02Data at 80990Sh = 733COOOh = 1.797S0e + 02LUF LV UF N Z V C = 0 0 0 0 0 0 0RO.10-187
SyntaxOperationOperandsSUBRI src, dstsrc - dst ~ dstsrcgeneral addressing modes (G):0 register (Rn, 0 =s; n =s; 27)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0 =s; n =s; 27)Encoding(1, , 1 ' , I ,24,23000110011G116 1587I IsrcDescriptionThe difference of the src operand minus the dst operand is loaded into the dstregister. The dst and src operands are assumed to be signed integers.CyclesStatus BitsMode BitExampleThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV 1 if an integer overflow occurs, unchanged otherwise.UF o.N 1 if a negative result is generated, 0 otherwise.Z 1 if a zero result is generated, 0 otherwise.V 1 if an integer overflow occurs, 0 otherwise.C 1 if a borrow occurs, 0 otherwise.OVM Operation is affected by OVM bit value.SUBRI *AR5++(IRO),R3Before Instruction:AR5 = 809900hIRO = 8hR3 = ODCh = 220Data at 809900h = 226h = 550LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR5 = 809908hIRO = 8hR3= 014Ah = 330Data at 809900h = 226h = 550LUF LV UF N Z V C = 0 0 0 0 0 0 0RO.1 0-188 Assembly Language Instructions.
SyntaxOperationOperandsEncodingDescriptionCyclesStatus BitsMode BitSWIPerforms an emulation interruptNone31 24 23 16 15 8 7 0I 0' 1 ' l' 0 ' 0' 1 '11 0' 0' 0' 0 I 0' 0' 0' 0 ' 0' 0' 0' 0' 0' 0' 0' ri' 0' 0' 0' 0' 0' 0' 0' 0 ' 01The SWI instruction performs an emulator interrupt. This is a reseNed instructionand should not be used in normal programming.4LUFLVUFN.ZVCUnaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.Unaffected.OVM Operation is not affected by OVM bit value.10-189
Example TRAPZ 16Before Instruction:PC = 123hSP = 809870hST=OhTrap Vector 16 = 1 OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:PC = 10hSP = 809871 hData at 809871 h = 124hST= OhLUF LV UF N Z V C = 0 0 0 0 0 0 010-191
TSTBTest Bit FieldsSyntaxOperationOperandsTSTB src, dstdst AN D srcsrc general addressing modes (G):o 0 register (Rn, 0 ~ n ~ 27)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0 ~ n ~ 27)EncodingDescription31 2423 1615 87 oi isrcIThe bitwise logical-AND of the dst and src operands is formed, but the resultis not loaded in any register. This allows for nondestructive compares. The dstand src operands are assumed to be unsigned integers.ICyclesStatus BitsMode BitExampleThese condition flags are modified for all destination registers (R27 -LUF Unaffected.LV Unaffected.UF o.N MSB of the output.Z 1 if a zero output is generated, 0 otherwise.V O.C Unaffected.OVM Operation is not affected by OVM bit value.TSTB *-AR4(1),R5Before Instruction:AR4 = 8099C5hR5 = 898h = 2200Data at 8099C4h = 767h = 1895LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR4 = 8099C5hR5 = 898h = 2200Data at 8099C4h = 767h = 1895LUF LV UF N Z V C = 0 0 0 0 1 0 0RO).10-192Assembly Language Instructions
SyntaxTSTB3 src2, src 1Operationsrc1 AND src2Operation° ° register (Rn1, 0::; n1 ::; 27)1 ° register (Rn1, ° ::; n1 ::; 27)src1 three-operand addressing modes (T):° 1 indirect (disp = 0, 1, IRO, IR1)1 1 indirect (disp = 0,1, IRO, IR1)src2 three-operand addressing modes (T):° register (Rn2, ::; n2 ::; 27)o 1 register (Rn2, ° ::; n2 ::; 127)1 ° indirect (disp = 0, 1, IRO, IR1)1 1 indirect (disp = 0, 1, IRO, IR1)Encodingi isrc187I'i isrc2a, IDescriptionThe bitwise logical-AND between the src1 and src2 operands is formed, butis not loaded into any register. This allows for nondestructive compares. Thesrc1 and src2 operands are assumed to be unsigned integers. <strong>Al</strong>though thisinstruction has only two operands, it is designated as a three operand instructionbecause operands are specified in the three-operand format.CyclesStatus BitsMode BitThese condition flags are modified for all destination registers (R27 -LUF Unaffected.LV Unaffected.UF 0.N MSB of the output.Z 1 if a zero output is generated, ° otherwise.V 0.C Unaffected.OVM Operation is not affected by OVM bit value.RO).10-193
TSTB3Test Bit Fields, 3-0perands;::~;=;:;::=;:.:;~:~;:;:::;\:;:.:;.~::;:;:::;:;:;:::::::::::::::::;:::::::::::;:::::::~::::::::::::::::::::::::;:::::;:::::;:::::::::.:.:.:.:.:;:.:.:::~.:~.:.:.:.:.:.:.' ••• :.:.:.~~.:.:.: •••• ~.:::;:::::;:;:::;:::;:::;:::::~::~::::::::::::':::'.:;'.::::::::::::'::::::::::.:::;';';0;::::,,:;\.;:::;.;:;.::;.;:::::::::::.,;.;:.::::.;: •• ;.;:;';~'::::::::::::;~%':';';';';';':::::':'::;O;';';';O;':':';'.';.'O';.;O •••• ; ••• ; ••• ; •••• \.;.:::::.;.»:.: ... ;.;.;:;. .• ;O;.;.;.;.;.;.;.,:.o!::;.;·;·;·:::~:·:~::·:·;·;~·;y;·;:.·:·::;::::::~;:::;9;:::;~:~:::;:;:;:;9::~::::"~"!;:::::;:;Example 1TSTB3*AR5--(IRO),*+ARO(1)Before Instruction:AR5 = 809885hIRO = 80hARO = 80992ChData at 809885h = 898h = 2200Data at 80992Dh = 767h = 1895LUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR5 = 809805hIRO = 80hARO = 80992ChData at 809885h = 898h = 2200Data at 80992Dh = 767h = 1895LUF LV UF N Z V C = 0 0 0 0 1 0 0Example 2TSTB3R4, *AR6--(IRO)Before Instruction:R4 = OFBC4hAR6 = 8099F8hIRO = 8hData at 8099F8h = 1568hLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R4 = OFBC4hAR6 = 8099FOhIRO = 8hData at 8099F8h = 1568hLUF . LV UF N Z V C = 0 0 0 0 0 0 01 0-194 Assembly Language Instructions
Bitwise Exclusive-OR XORSyntaxOperationOperandsXOR src, dstdst XOR src -7 dstsrc general addressing modes (G):0 register (Rn, 0 $ n $ 27)o 1 direct1 0 indirect1 1 immediatedst register (Rn, 0 $ n $ 27)Encoding8731 • • , • • • • 24.23,,000110101 G src••DescriptionThe bitwise exclusive-OR of the srcand dstoperands is loaded into the dstregister.The dst and src operands are assumed to be unsigned integers.CyclesStatus BitsMode BitExampleThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV Unaffected.UF o.N MSB of the output.Z 1 if a zero output is generated, 0 otherwise.V O.C Unaffected.OVM Operation is not affected by OVM bit value.XOR Rl,R2Before Instruction:R1 = OFFA32hR2 = OFF5C1hLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R1 = OFF412hR2 = OOOFF3hLUF LV UF N Z V C = 0 0 0 0 0 0 0RO.10-195
XOR3Bitwise Exclusive-OR. 3-0perand;:·;-;:;:,;~~Y,.:v.;:.;:;!.:;=~~Q.;:::t~;::~~::::r.::~:~::-:;:~~:~::~:;m:;:::.Y~~06~M~""~:M:>·;·;::Y>%~":.·;:;:::»';y;"""~""'N............................;-;«:"o:;:::;..::~o::.. v.:X«""l:;·;"::O~:;::?:o:;O:::::X"-,:·;::·;~~x·:""":;,;"",,o; ........-:-;.. o:; ..·;«-:::*>..·.·;«
· . Bitwise Exclusive-OR, 3-0perand XOR3::;::::y.".:;:;:;:;:~y.;:;:;:%;:;:;:;:::;:;:;::::,:;:::;:;:::".:;:~.;:;:::".:;:;~; :;~.$:;:;::f.~.:;.~.:;$:;:;:;:;':;:;f.%:;:;:;'~l.~.:;:;:;~:;:;':; :;.~:::;:;:;:::;.:;:::::::;:::::::::;:;:;:::;:;:::::::::::;:::::::;~;.;:::;:;::~::::;:;:;:::::::~:~:::::::;.::::;:::;:;::~.::::::::;.:::::::9';:::;:::::::;:;:::;:;:::;:;:::::::;:::::;:::;::::::.::::::%:;:::::::;.;.:..:.................................:••• ~~· ...-:.:~o!... »!ow.!o·.·.·.!'o~.:...·6..!>'.:~·;:.-...:~...:;:.. ~::~ .. ~:~:;~:;,.;::>:::::;:O::.:;:::::::;:;:;z:;:::;:;:;:i::.:;:;:::::;,.;:;:Example 1XOR3 *AR3++(IRO),R7,R4Before Instruction:AR3 = 809800hIRO = 10hR7 = OFFFFhR4 =OhData at 809800h = 5AC3hLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR3 = 809810hIRO = 10hR7 = OFFFFhR4 = OA53ChData at 809800h = 5AC3hLUF LV UF N Z V C = 0 0 0 0 0 0 0Example 2XOR3R5,*-AR1(1),RlBefore Instruction:R5 = OFFA32hAR1 = 809826hR1 = OhData at 809825h = OFF5C1 hLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:R5 = OFFA32hAR1 = 809826hR1 = OOOF33hData at 809825h = OFF5C1 hLUF LV UF N Z V C = 0 0 0 0 0 0 010-197
XOR311STIParallel XOR3 and STI; ••• ; •• ~.: •• ", •••••••• : •• " •••••• " •• -: ••••• :.' ••• "' ••• ":::::;::::0;::::::::::::::::::::::::::::;';:::::.:::.:.: •• ;:.:.: .......... :.-; ......................................................................... : •••• ~ ...... o! ........ : ... ;.; ••• ;.:.;.;.;.;.;.;.;.; ••• ;.;.;.;.;.; ••• ; ••••• ; ... ; ••• ;.;.; ••• ; ••• ; ••••• ;.;.;.;.;.;.; •• ~.;.;.;-; ••• ;.;.; ....... ;.;.;\~.;-;.;.;.;.;.; ••• ,.;.; •• ..;.;.; ••• ;.;.;.; •••••• .; ••• ; ••••• ;.;.; ••••• ;.; ••••••••••••••• ;.; ••••• ;.; ••••••••• ;.;.;.; ... ; ••• ;.; ••••• ;.;.; ••••• ; ••••• ; ••• ;.; ••• ;.;.;.;.;.; ••• ;.;:;.;",;,;,;,;,;,;,;,;,;,;,;,;,;:::;,;,;:;",;:::;,;".;.;.;.;:;::.::;:::;:::::;~:;:oSyntaxIIXOR3STIsrc2, src1, dst1src3, dst2OperationIIsrc1 XOR src2 --7 dst1src3 --7 dst2Operandssrc1 register (Rn1, 0 ~ n1 ~ 7)src2 indirect (disp = 0, 1, IRO, IR1)dst1 register (Rn2, ~ n2 ~ 7)src3 register (Rn3, ~ n3 ~ 7)dst2 indirect (disp = 0, 1, IRO, IR1)Encoding31 2423I I I I I I I I I I1 1 1 0 1 1 1 dstIIsrc116 15I I I Isrc3I I Idst287I' I I Isrc2DescriptionA bitwise exclusive-XOR and an integer store are performed in parallel. <strong>Al</strong>l registersare read atthe beginning and loaded atthe end of the execute cycle. Thismeans that if one of the parallel operations (STI) reads from a register and theoperation being performed in parallel (XOR3) writes to the same register, thenSTI accepts as input the contents of the register before it is modified by theXOR3.If src2 and dst2 point to the same location, src2 is read before the write to dst2.CyclesStatus BitsMode BitThese condition flags are modified only if the destination register is R7 -LUF Unaffected.LV Unaffected.UF o.N MSB of the output.Z 1 if a zero output is generated, 0 otherwise.V O.C Unaffected.OVM Operation is not affected by OVM bit value.RO.10-198Assembly Language Instructions
Example XOR3 *AR1++,R3,R3II STI R6,*-AR2(IRO)Before Instruction:AR1'= 80987EhR3 = 8ShR6 = ODCh = 220AR2 = 809884hIRO = 8hData at 80987Eh = 8ShData at 8098ACh = OhLUF LV UF N Z V C = 0 0 0 0 0 0 0After Instruction:AR 1 = 80987FhR3 = Oh .R6 = ODCh = 220AR2 = 8098B4hIRO = 8hData at 80987Eh = 8ShData at 8098ACh = ODCh = 220LUF LV UF N Z V C = 0 0 0 0 0 0 010-199
10-200 Assembly Language Instructions
Software Applications
1IIIIII~ ____________________________ S_o_ft_w_a_re_A_p_p_l_iC_a_ti_on_s ______ ~
Software Applications .• Extended-precision arithmetic• IEEE C3x floating-point conversionsQ Application-Oriented Operations (Section 11.4 on page 11-48)• Companding (A-law, Il-Iaw)• FIRIIIR filters (fixed and adaptive)• Matrix math• FFT• Lattice filtersQ Programming Tips (Section 11.5 on page 11-88)• C-callable routines• Code optimization check listFor convenience, the code in this section is located on the TI DSP BulletinBoard System (BBS) at 713-274-2323.11-2Software Applications
Processor Initialization11.1 Processor InitializationBefore you execute a digital signal processing algorithm, it is necessary to initializethe processor. Generally, initialization takes place any time the processoris reset.When reset is activated by applying a low level to the RESET input for severalcycles, the TMS320C3x terminates execution and puts the reset vector (Le.,the contents of memory location 0) in the program counter. The reset vectornormally contains the address of the system initialization routine. The hardwarereset also initializes various registers and status bits.After reset, initialize the processor further by executing instructions that setup operational modes, memory pointers, interrupts, and the remaining functionsneeded to meet system requirements.To configure the processor at reset, the following internal functions should beinitialized:QQMemory-mapped registersInterrupt structureExample 11-1 shows coding for initializing the TMS320C3x to the followingmachine state, in addition to the initialization performed during the hardwarereset (for conditions after hardware reset, see Chapter 12):Q <strong>Al</strong>l interrupts are enabled.Q The overflow mode is disabled.Q The data memory page pointer is set to zero.Q The internal memory is filled with zeros.Note that all constants larger than 16 bits should be placed in memory and accessedthrough direct or indirect addressing.11-3
Processor InitializationExample 1 '1-1. . TMS320C3x Processor Initialization** TITL 'PROCESSOR INITIALIZATION EXAMPLE'*.global.global.global.global.global.global.globalRESET,INIT,BEGININTO,INT1,INT2,INT3ISRO,ISR1,ISR2,ISR3DINT,DMATINTO,TINT1,XINTO,RINTO,XINT1,RINTlTIMEO,TIME1,XMTO,RCVO,XMT1,RCVlTRAPO,TRAP1,TRAP2,TRPO,TRP1,TRP2* PROCESSOR INITIALIZATION FOR THE TMS320C3x.* RESET AND INTERRUPT VECTOR SPECIFICATION. THIS* ARRANGEMENT ASSUMES THAT DURING LINKING, THE FOLLOWING* TEXT SEGMENT WILL BE PLACED TO START AT MEMORY* LOCATION O.*RESET*INTOINTlINT2INT3*XINTORINTOXINTlRINTlTINTOTINTlDINTTRAP 0TRAP 1TRAP2.sect "init".word INIT.word ISRO.word ISRl.word ISR2.word ISR3.word XMTO.word RCVO.word XMTl.word RCVl· word TIMEO.word TIMEl.word DMA· space 20.word TRPO.word TRPl.word TRP2· space 29Named sectionRS- load address INIT to PCINTOINT1-INT2-INT3-loads address ISRO to PCloads address ISRl to PCloads address ISR2 to PCloads address ISR3 to PCSerial port 0 transmit interrupt processingSerial port 0 receive interrupt processingSerial port 1 transmit interrupt processingSerial port 1 receive interrupt processingTimer 0 interrupt processingTimer 1 interrupt processingDMA interrupt processingReserved spaceTrap 0 vector processing beginsTrap 1 vector processing beginsTrap 2 vector processing beginsLeave space for the other 29 traps**IN THIS SECTION, CONSTANTS THAT CANNOT BE REPRESENTED*IN THE SHORT FORMAT ARE INITIALIZED. THE NUMBERS IN PARENTHESIS*AT THE END OF THE COMMENTS REPRESENT THE OFFSET OF A*PARTICULAR CONTROL REGISTER FROM*CTRL (808000H).dataMASK .wordBLKO .wordBLKl .wordSTCK .wordCTRL .wordDMACTL .wordTIMOCTL .wordTIM1CTL .wordSERGLOBO .wordSERPRTXO .wordSERPRTRO .wordOFFFFFFFFH0809800H0809COOH0809FOOH0808000HOOOOOOOHOOOOOOOHOOOOOOOHOOOOOOOHOOOOOOOHOOOOOOOHBeginning address of RAM block 0Beginning address of RAM block 1Beginning of stackPointer for peripheral-bus memory mapInitialization for DMA control (0)Initialization of timer 0 control (32)Initialization of timer 1 control (48)Init of serial 0 glbl control (64)Init of serial 0 :·:mt port control (66)Init of serial 0 rcv port control (67)11-4Software Applications
Processor InitializationSERTIMOSERGLOB1SERPRTX1SERPRTR1SERTIM1PARINTIOINT*.word.word.word.word.word.word.wordOOOOOOOHOOOOOOOHOOOOOOOHOOOOOOOHOOOOOOOHOOOOOOOHOOOOOOOHInit of serial 0 timer control (68)Init of serial 1 glbl control (80)Init of serial 1 xmt port control (82)Init of serial 1 rcv port control (83)Init of serial 1 timer contro~ (84)Init parallel interface control (100)Init I/O interface control (96).text** THE ADDRESS AT MEMORY LOCATION 0 DIRECTS EXECUTION TO BEGIN HERE* FOR RESET PROCESSING THAT INITIALIZES THE PROCESSOR. WHEN RESET* IS APPLIED, THE FOLLOWING REGISTERS ARE INITIALIZED TO ZERO:* ST CPU STATUS REGISTER* IE CPU/DMA INTERRUPT ENABLE FLAGS* IF CPU INTERRUPT FLAGS* IOF-- I/O FLAGS* THE STATUS REGISTER HAS THE FOLLOWING ARRANGEMENT:* BITS: 31-14 13 12 11 10 9 8 7 6 5 4 3 2 1 0* FUNCTION: RESRV GIE CC CE CF RESRV RM OVM LUF LV UF N Z V C*INIT LDP O,DPPoint the DP register to page 0LDI 1800H,ST Clear and enable cache, and disable OVMLDI @MASK,IE Unmask all interrupts* INTERNAL DATA MEMORY INITIALIZATION TO FLOATING POINT ZERO*LDI @BLKO,ARO ARO points to block 0LDI @BLK1,AR1 AR1 points to block 1LDF O.O,RO Zero register RORPTS 1023 Repeat 1024 timesSTF RO, *ARO++ (1) Zero out location in RAM blockII STF RO,*AR1++(1) zero out location in RAM block** THE PROCESSOR IS INITIALIZED. THE REMAINING APPLICATION-* DEPENDENT PART OF THE SYSTEM (BOTH ON- AND OFF-CHIP SHOULD* NOW BE INITIALIZED.* FIRST, INITIALIZE THE CONTROL REGISTERS. IN THIS EXAMPLE,o and1.* EVERYTHING IS INITIALIZED TO ZERO SINCE THE ACTUAL INITIALIZATION IS* APPLICATION DEPENDENT."**LDILDISTI@CTRL,ARO@DMACTL,RORO, *+ARO (0)LOAD in ARO the pointer to controlregistersInit DMA control11-5
Processor Initialization**LDI @TIMOCTL,ROSTI RO,*+ARO(32) Init timer° controlLDI @TIMlCTL,ROSTI RO, *+ARO (48) Init timer 1 controlLDI @SERGLOBO,ROSTI RO, *+ARO (64) Init serial global controlLDI @SERPRTXO,RO °STI RO, *+ARO (66) Init serial :·:mt controlLDI @SERPRTRO,RO °STI RO,*+ARO(67) Init serial rcv controlLDI @SERTIMO,RO °STI RO, *+ARO (68) Init serial 0 timer controlLDI @SERGLOBl,ROSTI RO,*+ARO(80) Init serial 1 global controlLDI @SERPRTXl,ROSTI RO, *+ARO (82) Init serial 1 :·:mt controlLDI @SERPRTRl,ROSTI RO,*+ARO(83) Init serial 1 rcv controlLDI @SERTIM1,ROSTI RO,*+ARO(84) Init serial 1 timer controlLDI @PARINT,ROSTI RO, *+ARO (100) Init parallel interface control (C30 only)LDI @IOINT,ROSTI RO,*+ARO(96) Init I/O interface controlLDI @STCK,SP Initialize the stacy. pointerOR 2000H,ST Global interrupt enableBR BEGIN Branch to the beginning of application..end11-6 Software Applications
Program Control:-;:::;:::;:::::;:;::::::::::::::-;::-;o;:;:'t.::;:::".(,%:::::::::::::o::==:;:::;...:=;::~:::~::!:-.;:::;:::::::::::::::::::::::::::::::::::::::::::;:;:;:::::::;::::::::%'::'':::::::::::(::;*::::~:'::(::(:::-'::::::"'':::::::y.(::::;:(;::::::::::::~.::::.::;:::::::;:;:;:(::::;:::::::~:::;::.;.:::.. ::.:.:.:.:.:.:::::.;.;.(::;.:.:.;:;.;::::y/.:.;:;.;.;.::;~...::;,~:::-:::;::·::::::::;.(;:;.;o:;o:;:;.;:::x:.~::;:::;o:;:....:;·::;:::;.:::·::;';:::::"t.;.~.:::;:;.:.:.;.. ~:;.-.. ;.~;:::;... ~>.,;:::~;::::::::,::::::;:;: ;:::::::;:::::&;:;:>.;~:::-.. ~:==-//... ;~;*)!;:~~:;-;Example 11-2. Subroutine Call (Dot Product)* TITLE SUBROUTINE CALL (DOT PRODUCT)** MAIN ROUTINE THAT CALLS THE SUBROUTINE 'DOT'TO'COMPUTE THE* DOT PRODUCT OF TWO VECTORS.**** LDI @blkO,ARO AROpoints to vector a* LDI @blkl,ARl ARl points to vector b* LDI N,RCRC contains the number of elements* CALL DOT**** SUBROUTINE DOT* EQUATION: d = a(O) * b(O) + a(l) * b(l) + ... + a(N-l) * b(N-l)* THE DOT PRODUCT OF a AND b IS PLACED IN REGISTER RO. N MUST* BE GREATER THAN OR EQUAL TO 2.* ARGUMENT ASSIGNMENTS:* ARGUMENT I FUNCTION* --------+-------------------------------------* ARO I ADDRESS OF a (0)* ARl I ADDRESS OF b (0), * RC I LENGTH OF VECTORS (N)******DOTREGISTERS USED AS INPUT: ARO, AR1, RCREGISTER MODIFIED: ROREGISTER CONTAINING RESULT: RO.global DOTPUSHPUSHPUSHFPUSHPUSHPUSHSTR2R2AROARlRCSave status registerUse the stack to save R2'slower 32 and upper 32 bitsSave AROSave ARlSave RC11-8Software Applications
Prl"lt'1rt:J.rTI Control*MPYF3LDFSUBI*ARO,*AR1,ROO.O,R22, RC* DOT PRODUCT (1 ROInitialize R2.Set RC = N-2RPTS RC ; Setup the repeat single.MPYF3 *++ARO(1),*++AR1(1),RO; a(i) * b(i) -> ROI I ADDF3 RO, R2, R2 a (i-l) *b (i-l) + R2 -> R2*ADDF3 RO, R2, RO a(N-l)*b(N-l) + R2 -> RO** RETURN SEQUENCE*** end*.endPOPPOPPOPPOPFPOPPOPRETSRCAR1AROR2R2STRestore RCRestore AR1Restore ARORestore top 32 bits of R2Restore bottom 32 bits of R2Restore STReturn11.2.2Software StackThe TMS320C3x has a software stack whose location is determined by thecontents of the stack pointer register SP. The stack pointer increments fromlow to high values, and provisions should be made to accommodate the anticipatedstorage requirements. The stack can be used not only during the subroutineCALL and RETS, but also inside the subroutine as a place of temporarystorage of the registers as shown in Example 11-2. SP always points to thelast value pushed on the stack.The CALL and CALLcond instructions push the value of the program counteronto the stack, as do the interrupt routines. Then, RETScond and RETlcondpop the stack and place the value in the program counter. The integer valueof any register can also be pushed onto and popped off the stack using thePUSH and POP instructions. There are two additional instructions, PUSHFand POPF, for floating point numbers. These instructions can be used to popand push floating point numbers to registers R7 - RO. This feature is veryuseful for saving all 40 bits of the extended precision registers (seeExample 11-2). Using PUSH and PUSHF onthe same register saves the lower32 and upper 32 bits. PUSH saves the lower 32; PUSHF, the upper 32. Torecover this extended precision number, a POPF can be done, followed byPOP. It is important to do the integer and floating-point PUSH and POP in theabove order. POPF forces the least significant eight bits of the extended-precisionregisters to zero, and therefore must be performed first.11-9
Program ControlThe stack pointer (SP) can be read as well as written to. Multiple stacks fordifferent program segments may be easily created. SP is not initialized by thehardware during reset. It is therefore important to remember to initialize its valueso that SP points to a predetermined memory location. This avoids the problemof SP attempting to write into ROM or over other useful data.11.2.3 Interrupt Service RoutinesInterrupts on the TMS320C3x are prioritized and vectored. When an interruptoccurs, the corresponding flag is set in the Interrupt Flag Register IF. If the correspondingbit in the Interrupt Enable Register IE is set, and interrupts are enabledby having the GIE bit in the status register set to 1, interrupt processingbegins. You can also write to the Interrupt flag register, allowing you to forcean interrupt by software, or to clear interrupts without processing them.The Interrupt Flag Register IF can be read, and action can be taken, dependingon whether the interrupt has occurred. This is true even when the interrupt isdisabled. This can be useful when an interrupt-driven interface is not implemented.Example 11-3 shows the case where a subroutine is called when interrupt1 has not occurred.Example 11-3. Use of Interrupts for Software Polling* TITLE INTERRUPT POLLINGTSTB 2,IFCALLZ SUBROUTINETest if interrupt 1 has occurredIf not, call subroutineWhen interrupt processing begins, the program counter is pushed on the stack,and the interrupt vector is loaded in the program counter. Interrupts are thendisabled by setting the GIE=O, and the program continues.from the addressloaded in the program counter. Since all interrupts are disabled, interrupt processingmay proceed without further interruption, unless the interrupt seNiceroutine re-enables interrupts.Except for very simple interrupt seNice routines, it is important to assure thatthe processor context is saved during execution of this routine. The contextmust be saved before you execute the routine itself, and restored after the routineis finished. The procedure is called context switching. Context switchingis also useful for subroutine calls, especially when extensive use is made ofthe auxiliary and the extended precision registers. Code examples of contextswitching and an interrupt seNice routine are provided in this section.11-10Software Applications
p,.,..,...,.
IJrrll"lr.~rn ControlExample 11-4.Context-Save for the TMS320C3x* TITLE CONTEXT-SAVE FOR THE TMS320C3:-:*.globalSAVE* CONTEXT SAVE ON SUBROUTINE CALL OR INTERRUPT.*SAVE:PUSH ST ; Save status register* SAVE THE EXTENDED PRECISION REGISTERS**PUSHPUSHFPUSHPUSHFPUSHPUSHFPUSHPUSHFPUSHPUSHFPUSHPUSHFPUSHPUSHFPUSHPUSHFRORORlRlR2R2R3R3R4R4R5R5R6R6R7R7* SAVE THE AUXILIARY REGISTERS***PUSHPUSHPUSHPUSHPUSHPUSHPUSHPUSHAROARlAR2AR3AR4AR5AR6AR7Save the lower 32 bits of ROand the upper 32 bitsSave the lower 32 bits of Rland the upper 32 bitsSave the lower 32 bits of R2and the upper 32 bitsSave the lower 32 bits of R3and the upper 32 bitsSave the lower 32 bits of R4and the upper 32 bitsSave the lower 32 bits of R5and the upper 32 bitsSave the lower 32 bits of R6and the upper 32 bitsSave the lower 32 bits of R7and the upper 32 bitsSave AROSave ARlSave AR2Save AR3Save AR4Save AR5Save AR6Save AR7* SAVE THE REST REGISTERS FROM THE REGISTER FILEPUSHPUSHPUSHPUSHPUSHPUSHPUSHPUSHPUSHPUSHDPIROIRlBKIEIFIOFRSRERC* SAVE IS COMPLETE*Save data page pointerSave index reqister IROSave index re~ister IRlSave block-size registerSave interrupt enable registerSave interrupt flag registerSave I/O flag registerSave repeat start addressSave repeat end addressSave repeat counter11-12Software Applications
Example 11-5.Context-Restore for the TMS320C3x* TITLE CONTEXT-RESTORE FOR THE TMS320C3x*.global RESTR* CONTEXT RESTORE AT THE END OF A SUBROUTINE CALL OR INTERRUPT.*RESTR:* RESTORE THE REST REGISTERS FROM THE REGISTER FILE*POP RC Restore repeat counterPOP RE Restore repeat end addressPOP RS Restore repeat start addressPOP IOF Restore I/O flag registerPOP IF Restore interrupt flag registerPOP IE Restore interrupt enable registerPOP BK Restore block-size registerPOP IRl Restore index register IRlPOP IRO Restore index register IROPOP DP Restore data page pointer** RESTORE THE AUXILIARY REGISTERS*POP AR7 Restore AR7POP AR6 Restore AR6POP AR5 Restore AR5POP AR4 Restore AR4POP AR3 Restore AR3POP AR2 Restore AR2POP ARl Restore ARlPOP ARO Restore ARO** RESTORE THE·EXTENDED PRECISION REGISTERS*POPF R7 Restore the upper 32 bits andPOP R7 the lower 32 bits of R7POPF R6 Restore the upper 32 bits andPOP R6 the lower 32 bits of R6POPF R5 Restore the upper 32 bits andPOP R5 the lower 32 bits of R5POPF R4 Restore the upper 32 bits andPOP R4 the lower 32 bits of R4POPF R3 Restore the upper 32 bits andPOP R3 the lower 32 bits ofR3POPF R2 Restore the upper 32 bits andPOP R2 the lower 32 bits of R2POPF Rl Restore the upper 32 bits andPOP Rl the lower 32 bits of RlPOPF RO Restore the upper 32 bits andPOP RO the lower 32 bits of ROPOP ST Restore status register**RESTORE IS COMPLETE11-13
D,.",.,,.,,,,,.,., Control11.2.3.2 Interrupt PriorityInterrupts on the TMS320C3x are automatically prioritized. This allows interruptsthat occur simultaneously to be serviced in a predefined order. Infrequent,but lengthy, interrupt service routines may need to be interrupted bymore frequently occurring interrupts. In Example 11-6, the interrupt serviceroutine for INT2 temporarily modifies the interrupt enable register (IE) to permitinterrupt processing when an interrupt to INTO (but no other interrupt) occurs.When the routine has finished processing, the IE register is restored to its originalstate. Notice that the RETlcond instruction not only pops the next programcounter address from the stack, but also sets the GIE bit of the status register.This enables all interrupts that have their interrupt-enable bit set.Example 11-6.Interrupt Service Routine* TITLE INTERRUPT SERVICE ROUTINE* .global ISR2ENABLE .set 2000hMASK . set '1** INTERRUPT PROCESSING FOR EXTERNAL INTERRUPT INT2-*ISR2:PUSHPUSHPUSHPUSHPUSHFPUSHPUSHFLDIORSTDPIERORORlRlMASK,IEENABLE,STSave status reqisterSave data page-pointerSave interrupt enable registerSave lower 32 bits andupper 32 bits of ROSave lower 32 bits andupper 32 bits of RlUnmask only INTOEnable all-interrupts* MAIN PROCESSING SECTION FOR ISR2*XORPOPFPOPPOPFPOPPOPPOPPOPRETIENABLE,STRlRlROROIEDPSTDisable all interruptsRestore upper 32 bits andlower 32 bits of RlRestore upper 32 bits andlower 32 bits of RORestore interrupt enable registerRestore data page registerRestore status registerReturn and enable interrupts11-14Software Applications
Prnrrr!:Jrn Control11.2.5 Repeat Modes11.2.5. 1 Block RepeatThe TMS320C3x supports looping without any overhead. For that purpose,there are two instructions: RPTB repeats a block of code, and RPTS repeatsa single instruction. There are three control registers: RS (repeat start address),RE (repeat end address), and RC (repeat counter). These contain theparameters that specify loop execution (refer to Section 7.1 for a complete descriptionof RPTB and RPTS). RS and RE are automatically set from the code,while RC must be set by the user, as shown in the examples below.Example 11-8 shows an application ofthe block repeat construct. In this example,an array of 64 elements is flipped over by exchanging the elements thatare equidistant from the end of the array. In other words, if the original arrayisa(1), a(2), ... , a(31), a(32), ... , a(64);the final array after the rearrangement will bea(64), a(63), ... , a(32), a(31 ), ... , a(1).Because the exchange operation is done on two elements at the same time,it requires 32 operations. The repeat counter RC is initialized to 31. In general,if RC contains the number N, the loop will be executed N + 1 times. The loopis defined by the RPTB instruction and the EXCH label.11-16Software Applications
Program ControlExample 11-10; Loop Using Single Repeat* TITL LOOP USING SINGLE REPEAT** THIS CODE SEGMENT COMPUTES***SUM[a(i)b(i)] FOR i 1 to N**LDILDILDFMPYF3@ADDR1,ARO@ADDR2,AR1O.O,RO*ARO++(1),*AR1++(1),R1ARO points to array a (i)AR1 points to ar.ray b (i)Initialize RO* ; Compute first productRPTS 511 ; Repeat 512 times*MPYF3 *ARO++(1),*AR1++(1),R1,RO I Compute next product.II ADDF3 R1,RO,RO and accumulate the previous one*ADDF R1,RO ; One final addition11-19
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Logical and Arithmetic Operations11.3 Logical and Arithmetic OperationsThe TMS320C3x instruction set supports both integer and floating-point arithmeticand logical operations. The basic functions of such instructions can becombined to form more complex operations. This section examines examplesof these operations:QQQQQQQBit manipulationBlock movesBit-reversed addressingInteger and floating-point divisionSquare rootExtended-precision arithmeticFloating-point format conversion between IEEE and TMS320C3x formats11.3.1 Bit ManipulationInstructions for logical operations, such as AND, OR, NOT, ANDN, and XOR,can be used together with the shift instructions for bit manipulation. A specialinstruction, TSTB, tests bits. TSTB does the same operation as AND, but theresult of the logical AN D is used only to set the condition flags and is not writtenanywhere. Example 11-12 and 11-13 demonstrate the use of the several instructionsfor bit manipulation and testing.Example 11-12. Use of TSTB for Software-Controlled Interrupt* TITLE USE OF TSTB FOR SOFTWARE-CONTROLLED INTERRUPT* IN THIS EXAMPLE, ALL INTERRUPTS HAVE BEEN DISABLED BY* RESETTING THE GIE BIT OF THE STATUS REGISTER. WHEN AN* INTERRUPT ARRIVES, IT IS STORED IN THE IF REGISTER. THE* PRESENT EXAMPLE ACTIVATES THE INTERRUPT SERVICE ROUTINE INTR* WHEN IT DETECTS THAT INT2- HAS OCCURRED.TSTB OlOOb,IFCALLNZ INTRCheck if bit 2 of IF is set,and, if so, call subroutine INTR11-21
Logical and Arithmetic Operationsil:w.~-::x:>!;(~:::-~.::::-.:::::::::"-:,«::::;x:".(.::!:r.:::::;:::::::::::;:::::" . .:::::::-.::".:"~~;:::Y./'.::w.'::::(.:;:::::::::;:;::-;::::~:::::-:::;:::::::~~~::;:"::*::::::::::::::"«::;:;::::::-;:::::::::;:::::::~:::::::::::::;:::;X:::::-o!::::::::::~:;';:::i:;:~«::;~::;:::::"~:::::::~~:::.::::::::::;o;::-;:::;:::"~;.;:::;.;:..;.;.::;.::;.;:;.:.,;..::.;........................ ~.~ ......;...;o,.~.... ~;-.-;.:: ........:... ~; ... ::;:::::::::;:::;:::::::::::::::::;:::::::::::::::::::::::::;::e:::~:~:;:".(.:::"-:::;:::::;:;::.:,11.3.2 Block MovesExample 11-14. Block Move Under Program ControlSince the TMS320C3x directly addresses a large amount of memory, blocksof data or program code can be stored off-chip in slow memories and thenloaded on-chip for faster execution. Data can also be moved from on-chip tooff-chip for storage or for multiprocessor data transfers.Such data transfers can be accomplished efficiently in parallel with CPU operations,using the DMA. The DMA operation is explained in detail in subsection8.3 on page 8-38. An alternative to DMA is to perform data transfers under programcontrol using load and store instructions in a repeat mode.Example 11-14 shows the transfer of a block of 512 floating-point numbersfrom external memory to block 1 of the on-chip RAM.* TITLE BLOCK MOVE UNDER PROGRAM CONTROL*extern .wordblock1 .wordOlOOOH0809COOHIILDILDILDFRPTSLDFSTFSTF@extern,ARO@block1,AR1*ARO++,RO510*ARO++,RORO,*AR1++RO,*ARlSource addressDestination addressLoad the first numberRepeat following instruction 511 timesLoad the next number, and ...store the previous· oneStore the last number11.3.3 Bit-Reversed AddressingThe TMS320C3x can implement Fast Fourier Transforms (FFT) with bit-reversedaddressing. If the data to be transformed is in the correct order, the finalresult of the FFT is scrambled in bit-reversed order. To recover the frequencydomaindata in the correct order, certain memory locations must be swapped.Tt"le bit-reversed addressing mode makes swapping unnecessary. The nexttime data needs to be accessed, the access is done in a bit-reversed mannerrather than sequentially. The base address of bit-reversed addressing must belocated on a boundary of the size of the table. For example, if IRO = 2n- 1, then LSBs of the base address must be zero (0).·In bit-reversed addressing, IRO holds a value equal to one-half the size of theFFT, if real and imaginary data are stored in separate arrays. During accessing,the auxiliary register is indexed by IRO, but with reverse carry propagation.Example 11-15 illustrates a 512-point complex FFT being moved from theplace of computation (pointed at by ARO) to a location pointed at by AR1. In11-23
Logical and Arithmetic Operations·:-::::-:o::x~,*;::~~~..::~:::-..xx--":::Y'««"Q,$';o-...... e::Y":::::::::::::::;:::::;:::::;:::;:::;&;:OX:::;':;'::::--';:O:::::::::($;~,!".::::~~::::~~~:::-a;:;~,::,~:::-o:"Q»'"«~Y.«;?;';::-':-";::::::X*-;:;'':X';o;o,:!~::(,:~:-»'::::::~:S!,.!'~«.:'«~::~;?'09.:-':-.::'Q.:::(.::::m?:(.( ..)!..»:::::e;..:::~:::x-~w...s:~~..>'::~:::."Se:::::..--.. "!:l::::-;:::::;-;so~~:~:::e;:;:::x.::::::x:w.~~Example 11-15. Bit-Reversed Addressingthis example, real and imaginary parts XR(i) and XI (i) of the data are not storedin separate arrays, but they are interleaved XR(O), XI(O), XR(1), XI(1), ... ,XR(N-1), XI(N-1). Because of this arrangement, the length of the array is 2Ninstead of N, and IRO is set to 512 instead of 256.** TITLE BIT-REVERSED ADDRESSING** THIS EXAMPLE MOVES THE RESULT OF THE 5l2-POINT FFT* COMPUTATION, POINTED AT BY ARO, TO A LOCATION POINTED AT* BY AR1. REAL AND IMAGINARY POINTS ARE ALTERNATING.LDI 5l2,IROLDI 2,J;RlLDI 5ll,RC Repeat 511+1 timesLDF *+ARO(l),Rl Load first imaginary pointRPTB LOOP*LDF *ARO++(IRO)B,RO Load real value (and pointII STF Rl,*+AR1(1) to next location) and store* the imaginary valueLOOP LDF *+ARO(l),Rl Load next imaginary point andII STF RO, *AR1++ (IR1) previous real valuestore11.3.4 Integer and Floating-Point Division11.3.4.1 Integer Division<strong>Al</strong>though division is not implemented as a single instruction in the TMS320C3x,the instruction set has the capacity to perform an efficient division routine.lntegerand floating-point division are examined separately because different algorithmsare used.Division is implemented on the TMS320C3x by repeated subtractions usingSUBC, a special conditional subtract instruction. Consider the case of a 32-bitpositive dividend with i significant bits (and 32 - i sign bits), and a 32-bit positivedivisor with j significant bits (and 32 - j sign bits). The repetition of theSUBC command i - j + 1 times produces a 32-bit result where the lower i - j + 1bits are the quotient, and the upper 31 - i + j bits are the remainder of the division.SUBC implements binary division in the same manner as long division. The divisor(assumed to be smaller than the dividend) is shifted left i - j times to bealigned with the dividend. Then, using SUBC, the shifted divisor is subtractedfrom the dividend. For each subtract that does not produce a negative answer,11-24Software Applications
Logical and Arithmetic Uperatlof7SLONG DIVISION:the dividend is replaced by the difference. It is then shifted to the left, and a oneis put in the LSB. If the difference is negative, the dividend is simply shifted leftby one. This operation is repeated i - j + 1 times.As an example, consider the division of 33 by 5 using both long division andthe SUBC method. In this case, i = 6, j = 3, and the SUBC operation is repeated6 - 3 + 1 = 4 times.0000000000000000000000000000010100000000000000000000000000000110Quotient00000000000000000000000000100001-1011101-10111 RemainderSUBC METHOD:0000000000000000000000000010000100000000000000000000000000101000Negative differenceJ.000000000000000000000000001000100000000000000000000000000010100000000000000000000000000000011010J.000000000000000000000000001101010000000000000000000000000010100000000000000000000000000000001101. J.0000000000000000000000000001101100000000000000000000000000101000Negative differenceJ.00000000000000000000000000110110DividendDivisor (aligned)(1 st SUBC command)New Dividend + QuotientDivisorDifference (>0) (2nd SUBC command)New Dividend + QuotientDivisorDifference (>0) (3rd SUBC command)New Dividend + QuotientDivisor(4th SUBC command)Final ResultRemainderQuot.When the SUBC command is used, both the dividend and the divisor must bepositive. Example 11-16shows a realization of the integer division in which thesign of the quotient is properly handled. The last instruction before returningmodifies the condition flag in case subsequent operations depend on the signof the result.11-25
Logical and Arithmetic Operations::~:;:::;:~"!:::::~:~'('::S::!;::S::--A1::!~:::::::::*,Q.::::-,(.:;::::::::::-;S:::;::-'::::::::::::::,,(.~,(.:::::::::::;:::::::::::-(.:;-;:::::::::"..».::::;:::;:::::::;:~m.:~%::::::?=~~:::W.h."Q.'Q.:%w .::x~:::'Q.'a.~'(':'::"Q.:::::::::::::::s:::::.~::::!~:::::,a:~:::~..;:::::~:~...:~:::::',::S::::S::::-:S::Y,:·;:::,.v,:::;:Q.::::::,;:xs:;s::·;::s::-.:s::::1:;::::::::~:::::::::;:::::::::::::'$::::::::::::::":::::::9;:::::::-~J:'''/.:w.,(.::-:~::::::::::::::~:::x::::~.::x-'!:,.::s::::::?:Example 11-16. Integer Division* TITLE INTEGER DIVISION******SUBROUTINE DIVIINPUTS:OUTPUT:SIGNED INTEGER DIVIDEND IN RO,SIGNED INTEGER DIVISOR IN R1.RO/R1 into RO.* REGISTERS USED: RO-R3, IRO, IR1****SIGNTEMPFTEMPCOUNTOPERATION:CYCLES:.globl.set. set.set.setDIVIR2R3IROIR1* DIVI SIGNED DIVISION1. NORMALIZE DIVISOR WITH DIVIDEND2. REPEAT SUBC3. QUOTIENT IS IN LSBs OF RESULT31-62 (DEPENDS ON AMOUNT OF NORMALIZATION)DIVI:* DETERMINE SIGN OF RESULT. GET ABSOLUTE VALUE OF OPERANDS.*XOR RO,R1,SIGN ; Get the signABSI ROABSI R1CMPI RO,R1 Divisor> dividend ?BGTD ZERO If so, return °* NORMALIZE OPERANDS. USE DIFFERENCE IN EXPONENTS AS SHIFT COUNT* FOR DIVISOR, AND AS REPEAT COUNT FOR 'SUBC'.*FLOAT RO,TEMPF Normalize dividendPUSHF TEMPF PUSH as floatPOP COUNT POP as intLSH -24, COUNT Get dividend exponent*FLOAT R1,TEMPF Normalize divisorPUSHF TEMPF PUSH as floatPOP TEMP POP as intLSH -24, TEMP Get divisor exponentSUBI TEMP, COUNT Get difference in exponentsLSH COUNT,R1 <strong>Al</strong>ign divisor with dividend* DO COUNT+1 SUBTRACT & SHIFTS.RPTS COUNTSUBC R1,RO*11-26Software Applications
and Arithmetic (Jm~mtlon.c;e = - 128. Then the calculation of x [0] yields an exponent equal to- (- 128) - 1 = 127, and the algorithm will overflow and saturate. On the otherhand, in the case of a very large number, e = 127, the exponent of x [0] will be- 127 - 1 = - 128. This will cause the algorithm to yield zero, which is a reasonablehandling of that boundary condition.11-28Software Applications
Logical and Arithmetic Operations~:;:::;~~;:;:::;m:~~::::7."~:;(.~",,~~:::-~;:",:;:;';:;:;:~:::::O::::::::: ~;~-=~;-:;~;:;::.;:::::~::~~;:;::::1::':::::;::~~~~~:::-:~::;::::::~w. ..-::::".. ~::~».;·~:::·~;:;:-~: ... ;·;·~x·;·:·:..·;·:·..;·;·;:;·......:·;.:.;.:.;.:...;:;.:.:.;:::::;... ;:;-;.~:.:.;:..;-:-:::.;.:.:::':-:'::;':::';';';-:';-;0;0:';';';';';';';':';';',-;-";';';';0,'.'1...·;...;v;·;·.·;·...•...•••.....•...•.•.....•••••••.•.•...•••••••......; •••••••••••••.•;.••;•••.•••••.:••••;.....;.......;.;.;.;:::;o••:.;:;.:.:.;.;:;••• ;:::::;o:::.::~?::;:~::::?::;~:;:::;~:;9:To start the operation, an initial estimate x[O] is needed. If v = a*28, a good initialestimate isx [0] = 1.0 * 2 - e/2Example 11-18 shows the implementation of this algorithm on theTMS320C3x, where the iteration has been applied 5 times. Both accuracy andspeed are affected by the number of iterations. If you want more accuracy, usemore iterations. If less accuracy is acceptable, reduce the number of iterationsto increase the execution speed of this implementation.11-31
Logical and Arithmetic Operations'.;Oo'!;:'.;:.~u.;:.~;:;:'.::O~;~::;:;!;:::;:::;:9:::;-~;::::-:;:"«:::::-;:;';:::::::::;:;:;:;:::::o:;:::::::--:::::::::;:::;:~:::::;::.;:;.:.:o;o;.::;:::;o.:::::;·:::::';'..;:;OO:::;:;::O;:;';';"Y::;,)';~::o::c::::;:--:;::·;,;:;o;:;9;:"..;::·;:..;.;o:.. o; ..:;:;~::o....:::::.::?;:;.;o;o;o;.....;...;o;v:.»;o;o;.;.:.....;.;.;oo.».;..·;o:::~·;o.:·;o.:'.......;·;o;o;o;,,·»»;v;o;o;.;o;...;·;o;y:y:.... y; ......·;o;o;·;,;",;';0:";,;,:,,';';';0;';';0;.;0:.'»:-;';0;';';';:;';0;':,,,;,;';';';-;';';·;::v;o:·;o;:;:o-;·;·os.:;::::::-:::::;:::::::;:::;:;:;:::::::;:;:::::::::::::;:;Example 11-18. Square Root of a Floating-Point Number** TITLE SQUARE ROOT OF A FLOATING-POINT NUMBER** SUBROUTINE SQRT* THE FLOATING POINT NUMBER v IS STORED IN RO. AFTER THE* COMPUTATION S COMPLETED, SQRT(v) IS ALSO STORED IN RO. NOTE* THAT THE ALGORITHM ACTUALLY COMPUTES l/SQRT(v).* TYPICAL CALLING SEQUENCE:*******LDF v, ROCALL SQRTARGUMENT ASSIGNMENTS:ARGUMENT I FUNCTION--------+-------------------------------------RO I v = NUMBER TO FIND THE SQUARE ROOT OFI (UPON THE CALL)RO I SQRT(v) (UPON THE RETURN)* REGISTER USED AS INPUT: RO* REGISTERS MODIFIED: RO, Rl, R2, R3* REGISTER CONTAINING RESULT: RO** CYCLES: 50 WORDS: 39*.global SQRT** EXTRACT THE EXPONENT OF V.*SQRT: LDF RO,R3 Save vRETSLEPUSHFPOPReturn if number non-positive*ASHADDIASHRORl-24,Rl1,Rl-l,RlThe 8 LSBs of Rl contain the exponent of v.Add a rounding bit in the exponente/2* X[O] FORMATION GIVEN THE EXPONENT OF V.*NEGI RlASH 24,RlPUSH RlPOPF RlNow Rl :-: [0] 1.0 * 2** (-e/2) .** GENERATE V/2.*MPYF 0.25,RO* NOW THE ITERATIONS BEGIN.*MPYFMPYFSUBRFRl,Rl,R2RO,R21.5,R2V/2R2R2R2and take rounding bit outx[O] * x[O](v /2 ) * :.: [ 0 ] * :.: [ 0 ]1.5 - (v/2) * x[O] * x[O]11-32Software Applications
Logical and Arithmetic Operations~Q.:s::z.;:;:o::s~!" ...:::o::::::~:;x:;.s->,:-;:.;::s:.::::::;:::::::::-.:::::~:::::-.(.::'«'~O;O;:::;:;:;';:;:;*:O"''::::>''''~;'~:X:;C";::::*;o'~':~~:::;':::::;!"$::Y.~:w.o!"~::==:;o.::::;:::::;:;==:::;~:~;==::.::*..~;::~::;O;:;:::;:O:;:::;:;::*;".(.::*;:
Logical and Arithmetic Operations;:::::::::::::::::::::::::::::::::::;:;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::;:::::::::::::::::;:;:;:;:;:::;.;:;:::::;:;:;.;::::::::::::y';:::;~:;:;:;::::::::::::::::';':':::::::::::::::::::::::::::::'::::;0:::::::;0;'::;';'::::::::::::::.:::::::::::::.::';:::;';::::::::::::::::.;::::::::::::::.;.:::: •• ::::::.::::.;:::::.:::: ... ;.;.;.;.;:::.: .. ;.:::.:::.::;-::;-:::.;.; ••••• ;0:;.;.;. ........ ;.; ... ;.;.; ....... ; .................................. :: ........ : ......... : ••• :; •••••••••••••••••••• :; •• ~ •• :.:-:::::;0:;';%:.:.:.:.:.:;:;';'::::::::::::::::::::::;:::::::::::::::::;:::::;:;:::;"0;:0:Example 11-19. 64-Bit AdditionExample 11-20. 64-Bit Subtraction* TITLE 64-BIT ADDITION* TWO 64-BIT NUMBERS ARE ADDED TO EACH OTHER PRODUCING* A 64-BIT RESULT. THE NUMBERS X (Rl,RO) AND Y (R3,R2)* ADDED, RESULTING IN W (Rl,RO).* Rl RO* + R3 R2* Rl RO*ADDI R2,ROADDC R3,Rl* TITLE 64-BIT SUBTRACTION* TWO 64-BIT NUMBERS ARE SUBTRACTED FROM EACH OTHER* PRODUCING A 64-BIT RESULT. THE NUMBERS X (Rl,RO) AND* Y (R3,R2) ARE SUBTRACTED, RESULTING IN W (Rl,RO).* Rl RO* + R3 R2* Rl RO*SUBI R2,ROSUBB R3,RlWhen two 32-bit numbers are multiplied, a 64-bit product results. The procedurefor multiplication is to split the 32-bit magnitude values of the multiplicandX and the multiplier Y into two parts (X1 ,XO) and (X3,X2), respectively, with 16bits each. The operation is done on unsigned numbers, and the product is ad-'justed for the sign bit. Example 11-21 shows the implementation of a 32-bit by32-bit multiplication.11-35
Logical and Arithmetic Operations;e~m~~~~:;:;:;:;:;,::;:;~:;::~,:ss::S'W'.;m-.:::::~Y;:;:::,:,:;>";:~:::~~~..:;~..:o:.»:;':~~~~;:;%~;';::S~~~"'~~~-;:;:::;::~.MYN...«-:v....;,o.;"Y.X,:~;.o«~y;·;:>·;w.;v;~"""""""''#M::....«.. v;y;W.-»Mo;~~''Mo;.; .. ~;:;SS ..:;w.;..·w......·~:~:;s:;,;Y»;::~s:;%~.:x~..sExample 11-21. 32-Bit by 32-Bit Multiplication* TITLE 32 X 32 BIT MULTIPLICATION* SUBROUTINE EXTMPY**********-**************FUNCTION: TWO 32-BIT NUMBERS ARE MULTIPLIED, PRODUCING A 64-BITRESULT. THE TWO NUMBERS (X and Y) ARE EACH SEPARATED INTO TWOPARTS (Xl XO) AND (Yl YO), WHERE XO, Xl, YO, AND Yl ARE 16 BITS.THE TOP BIT IN Xl AND Y1 IS THE SIGN BIT. THE PRODUCT ISIN TWO WORDS (WO AND W1). THE MULTIPLICATION IS PERFORMED ONPOSITIVE NUMBERS, AND THE SIGN IS DETERMINED AT THE END.*EXTMPY*XXl XOY1 YOXO*YOXO*YlX1*YOX1*Y1W1WOARGUMENT ASSIGNMENTS:ARGUMENT I FUNCTIONBITS OF PRODUCTS(NOT COUNTING SIGN)16+1616+1616+1616+16--------+-------------------------------------RO I MULTIPLIER AND LOW WORD OF THE PRODUCTR1 I MULT~PLICAND AND UPPER WORD OF THE PRODUCTREGISTERS USED AS INPUT: RO, R1REGISTERS MODIFIED: RO, R1, R2, R3, R4, ARO, AR1,REGISTER CONTAINING RESULT: RO,R1CYCLES: 28 (WORST CASE) WORDS: 25.global EXTMPYXOR3ABSIABSIRO,R1,AROROR1Store signAbsolute values of Xand Y* SEPARATE MULTIPLIER AND MULTIPLICAND INTO TWO PARTS-****LDILSH3ANDLSH3ANDCARRY OUT THEMPYI3MPYIMPYI-16,AR1AR1,RO,R2OFFFFH,ROAR1,R1,R3OFFFFH,R1MULTIPLICATIONRO,R1,R4R3,ROR2,R1R2ROR3R1XO*YOXO*Y1X1*YOXlXOY1YOP1P2P3UpperLowerUpperLowerPRODUCTP1P2P3P416 bits16 bits16 bits16 bitsof Xof Xof Yof Y11-36Software Applications
Logical and Arithmetic Operationso:.~~~:»':::s::s::':~»'!-~m~;'O;!::::"!l:""::S::;'~*"?~~~'!-"?::;c.:.::::;:::;:;o~>'>y'~~";:"o!'"";:':~~~~-:::>,::;::~>':~~~;:::"-:~::::::;:;:;:;O'::~::::::::-Q .. ~:';X;:;:'''»'::~"y'~~::;O;-':::):>"):?'~:::'';:;~~:;~.Y.;~:~:::;M>'~:;o~.«-y'N..w.-w.,,:~Y..:~-:~'.;,o%:.'~~-:::«~;:;:';~;O.;~;'~;':>'~:::;':~;"~~~:::~;:i';:;:;:::::~:, ..;:;.x:.~::;.:~*ADDI RO,Rl P2+P3MPYI R2,R3 Xl*Yl P4LDI Rl,R2LSH l6,R2 Lower 16 bits of P2+P3CMPI O,ARO Check the sign of the productBGED DONE If >0, mUltiplication complete (delayed)LSH -16,R1 Upper 16 bits of P2+P3ADDI3 R4,R2,RO WO RO Lower word of theADDC3 R1,R3,R1 W1 = R1 = Upper word of the* NEGATE THE PRODUCT IF THE NUMBERS ARE OF OPPOSITE SIGN**DONENOT ROADDI 1,RONOT R1ADDC 0,R1RETS.endproductproduct11-37
Logical and Arithmetic Operations~:.":::::::;m::.:::>sm::»"!'o!;:::;s~..z:::;::~%::w..::-.:::::::::::o.;~::WoS:l';%~!~~::::::::::W:~:::::::::.~::~,;~%~~ .. 9';.;m--~;m7.~~~::::::='.:.~~':~;::::-~?~~::';%::7.=?:*>.":::!:!~: ~!~"?'.b.~::ms:::.~;%::::~ .. ~::-;::?':::='~9.::~~>"~~:;(.~:*.::::w:.~ .. ~::S!;:;Y.:!:$~:;:O;W:o>':Ow..::xw.o!:?"o:'.(.S'"/Q .... ..w..::.~z::%::~:;ss~;ss11.3.7.1 IEEE to TMS320C3x Floating-Point Format ConversionExample 11-22 shows the fast conversion from IEEE to TMS320C3x floatingpointformat 1 . It properly handles the general case when 0 < e < 255, and alsohandles zeros (Le.,e = Oandf = 0). The other special cases (denormalized, infinity,and NaN) are not treated and, if present, will give erroneous results.Example 11~22.IEEE toTMS320C3x Conversion (Fast Version)* TITLE IEEE TO TMS320C3x CONVERSION (FAST VERSION)* SUBROUTINE FMIEEE* FUNCTION: CONVERSION BETWEEN THE IEEE FORMAT AND THE* TMS320C3x FLOATING POINT NUMBERS. THE NUMBER TO* BE CONVERTED is IN THE LOWER 32 BITS OF RO.* THE RESULT IS STORED IN THE UPPER 32 BITS OF RO.* UPON ENTERING THE ROUTINE, AR1 POINTS TO THE* FOLLOWING TABLE:***(0)(1)(2)(3)(4)OxFF800000
Logical and Arithmetic Operations.y..;y.;v..\ .... y.~.~~.::.:.»~~.:o~:.y.;:oy.;>:O:;:;:;9.;:;:;y.~;:;:;:;.~:~;~~:.:; :;Y.;':';:;':';:.:;Y..:':'''Y.Ho~,.w''''~~'''Y~~'''·''''''''%Y»';':';~;:~~';:;:;:X:h';'';:H~*' >·;.os~;y.;,;·m;S:;·~N~·~Example 11-23 shows the complete conversion between IEEE andTMS320C3x formats. In addition to the general case and the zeros, it handlesthe special cases as follows:QQQIf NaN (e = 255, f< >0), the number is returned intact.If infinity (e = 255, f = 0), the output is saturated t6 the most positive or negativenumber, respectively.If denormalized (e = 0, f< >0), two cases are considered. If the MSB of fis 1, the number is converted to TMS320C3x format. Otherwise, an unde~flowoccurs and the number is set to zero.Example 11-23. IEEE to TMS320C3x Conversion (Complete Version)* TITLE IEEE TO TMS320C3~ CONVERSION (COMPLETE VERSION)* SUBROUTINE FMIEEE1* FUNCTION: CONVERSION BETWEEN THE IEEE FORMAT AND THE TMS320C3x* FLOATING POINT NUMBERS. THE NUMBER TO BE CONVERTED* IS IN THE LOWER 32 BITS OF RO. THE RESULT IS STORED* IN THE UPPER 32 BITS OF RO.** UPON ENTERING THE ROUTINE, AR1 POINTS TO THE FOLLOWING TABLE:********(0)(1)(2)(3)(4 )(5)(6)(7)(8)0:.:FF800000
Logical and Arithmetic Operations::;:::;:;:;::::::::::-'::::::::::::;:;::::';:::::::;:;:::::;:;:::.':0:::::::;:::::::::::::::::::::;';-;:::;:;,:;:::;:;::::::,::::::::::::::::::::::::~::';:::;::::Y;::9;'l;::::::::-;-';':;';:;:;:::~':;:;:; :::;:;o":~;:;$:;:;:;o.(:·~;:i.;:::;:;:::::;o;:::;:;:;:;:~r.;:;-;·.:-.. ·.;·;:;:;:::;:;:;:::::::r.r.::;·.:::-,;::.::'l;:::::'-:::Xi;:;::-;:: •. ::::;.;:;:::; •. ::;: ••. :-,;.:; •. ;:::;:;:;./.::-.... :-.:::;::-.::::;0;:.·.~:;:~.· .... ·(;::w.:.-.·;· ..... :.'Io';·.·;:.:.:;:" .. ;:.· .. :.:;:;:::::.:.:.:.:.:.::·;:.::x4:.f.:::::;:::.:::;::::::::':::;:::;::(.:::::::;'::::::::::::::':::;::::S::::::':::::::::::::;:::;:;::!.:(Example continued from previous page)* NOTE: SINCE THE STACK POINTER SP IS USED, MAKE SURE TO INITIALIZE* IT IN THE CALLING PROGRAM.** CYCLES: 23 (WORST CASE)*.global FMIEEEI*FMIEEEI*LDIANDBZXORBNZRO,Rl*+ARl(5),RlUNNORM*+ARl(5),RlNORMAL* HANDLE NaN AND INFINITYWORDS: 34If e = 0, number is either 0 orunnormalizedIf e < 255, use regular routineTSTBRETSNZLDILDFGTLDFNRETS*+AR1(7),RORO,RO*+ARl(8),RO*+ARl(5),RO; Return if NaNIf positive, infinity=most positive numberIf negative, infinity=most negative number RETS* HANDLE ZEROS AND UNNORMALIZED NUMBERSUNNORMNEGITSTBLDFZRETSZXORBNDLSHSUBIPUSHPOPFRETSPOPFNEGFRETS*+ARl(6),RO*+ARl(3),RO*+ARl(6),RONEGI1,RO*+AR1(2),RORORORORO,ROIs the msb of f equal to I?If not, force the number to zeroand returnIf (msb of f) = 1, make it 0Eliminate sign bit and line up mantissaMake e = -127Put number in floating point formatIf negative, negate RO* HANDLE THE REGULAR CASES*NORMALAND3BNDADDISUBIPUSHPOPFRETSRO,*ARl,RlNEGRO,Rl*+ARl(2),RlRlROReplace fraction with 0Test signShift sign and exponent inserting 0Unbias e:.:ponentLoad this as a fIt. pt. numberNEGPOPFNEGFRETSRORO,ROLoad this as a fIt. pt. numberNegate if original sign negative11-43
Logical and Arithmetic Operations~o;c.~~»:..'.)~:;~;,;:::.::;:~;::ss:;:;::~:;:::;:-a.a:;~::;:;:::;:.:r&:*,a:;:::;:;:::;*.·~;,:~.:.:.:.*.!o.·;.:.~:."~~:.:..'o!w:.::.:;:;*;*;:;..;~.:;·::-~;·;:;·;:;.y';·,f.-!~;'~N.;. ... ~y;!o!o:;·:.:;:::;';';';::!;';:;';';';';'::.:::.:.~;o.!:'.'::;":!;":':';..:;.o;~!;o ...;.;·.·...·.·;·;·;o,;·;·;-:·;o;..:·;::·;·•..:·.v.;·;.;o;·;...."y;o;·;·;·;·;v~·....:y;·;.-u;·;v.;·;·;o;·.·;:;·;..:;o...;o:.::·.!O,.·:~·:!:·:·;·;.;..:·..;O....:.:••-!;.;o........:.;o..;o:•• o.;..: ..... ~;:. ••..::;.;v.::.::"-!;:;:;.:.::;:-:.:~::.:;:::::;~::::;o;:~
Logical and Arithmetic Operations~~::::m~::~::;.o;:::~~M::::::.:.:~:::>s-;~~:::;e:~ ...;*~:::::;...,;:::::::::m::::s,;:;::~'Y"~;'::::ZY~.c~Q.~':';:;»";::S~;::SI::?~;S5:~;e;::~::*::::,~::~~*,;~,:~-:::.:~:>.~..-.,::::;,:s~~s,s,;S':':';~;~~~~~Ii:::::;:;s· .•... ::W;~~Example 11-24. TMS320C3x to IEEE Conversion (Fast Version)* TITLE TMS320C3x TO IEEE CONVERSION (FAST VERSION)** SUBROUTINE TO IEEE* FUNCTION: CONVERSION BETWEEN THE TMS320C3x FORMAT AND THE IEEE* FLOATING POINT NUMBERS. THE NUMBER TO BE CONVERTED* IS IN THE UPPER 32 BITS OF RO. THE RESULT WILL BE IN* THE LOWER 32 BITS OF RO.* UPON ENTERING THE ROUTINE, ARI POINTS TO THE FOLLOWING TABLE:**(0)OxFF800000
Logical and Arithmetic Operations~.:6:;:;:-·;:,:;:-=~,:;:;:;:;:;:;~;:;:::::::::::-=::;:;:;:::::;-.::::::::::::::::::::::::::::;:;:::::;:;:;:::::::::;:::;:.:::.:::::.:. •••• ~:.:;:;:~:::.:::;O;:.!o'~.:;!o::::.;:::::::::::::;:;::~;::::-::::;:;::::'»:';';'::;';':';:;::';',,;.; ..:;.;:;.;....;::;..::;.;..:;::.;.;.;.;:::::::.:;...:.;.;.;-;-::;-:.;:;••:;....::.;.;:;.;-;·;·;v.;·;·~;·;o;·.·.·...·.v;·:·;..:·;·;·;·::;..·;-;·.·:·;·;·;.;.;..-;-;.;;;0••;.;0....;.;.;.........;.......;••••...;........;...»;...;•••...••••.,;·;o;·...·.·;·;·;·;·;..·:·x·;o.·;·;o..:·;::·;o.·;:;o:;·~;';:::;:;:::::::;:;o..'!;:::;~":::::::'::::;:::;:;:;:::;::X:Example 11-25. TMS320C3x to IEEE Conversion (Complete Version)* TITLE TMS320C3x TO IEEE CONVERSION (COMPLETE VERSION)** SUBROUTINE TOIEEE1** FUNCTION: CONVERSION BETWEEN THE TMS320C3:-: FORMAT AND THE IEEE* FLOATING POINT NUMBERS. THE NUMBER TO BE CONVERTED* IS IN THE UPPER 32 BITS OF RO. THE RESULT WILL BE* IN THE LOWER 32 BITS OF RO.********************UPON ENTERING THE ROUTINE, AR1 POINTS TO THE FOLLOWING TABLE:(0)(1)(2)(3)(4)(5)(6)(7)(8)OxFF800000
Logical and Arithmetic Operations6:«o"Y;~~~;;W;:::;'::;:;:;~~~:;~:;:;>:;::':':~>:~»:>AA;~:*m~:w::;:;,:~~~::.::,;ym.~~~..;:;*~~~~~~~:
Applications-Oriented Operations~;:;X;:o>:::;:;:>:;~~:::-o::::-:;:::;:>::-;:."!::::::;:'':::;::S:"-:;::::%:::;:::::~«:::::~::::--:"o:;:::::::" .. x.::,::,-,,;:>:::;:::::::::::::::::::::;::~:::::::::::-~:::::x::;x::;:"-::::::y'=':::9."
Applications-Oriented OperationsExample 11-28. A-Law Compression** TITLE A-LAW COMPRESSION** SUBROUTINE ACMPR** ARGUMENT ASSIGNMENTS:* ARGUMENT I FUNCTION* --------+-------------------------------------* RO I NUMBER TO BE CONVERTED* REGISTERS USED AS INPUT: RO* REGISTERS MODIFIED: RO, R1, R2, SP* REGISTER CONTAINING RESULT: RO* NOTE: SINCE THE STACK POINTER 'SP' IS USED IN THE COMPRESSION* ROUTINE 'ACMPR', MAKE SURE TO INITIALIZE IT IN THE* CALLING PROGRAM.** CYCLES: 22*.global*ACMPRLDIABSICMPIBLEDCMPILDIGTLSHWORDS: 19ACMPRRO,R1RO,RO1FH,ROENDOFFFH,ROOFFFH,RO-l,ROSave sign of numberIf ROO:-:FFF,saturate the resultEliminate rightmost bitFLOATMPYFLSHPUSHFPOPLSHROO.125,RO1,RORORO-20,RONormalize: (seg+3)OWXYZx ... xAdjust segment number by 2**(-3)(seg) WXYZ:-: ... xTreat number as integerRight-justifyEND*LDILDILDILTADDIXORRETS0, R2R1,R180H,R2R2,ROOD5H,ROIf number is negative,set sign bitRO = compressed numberInvert even bits for transmission11-51
Applications-Oriented Operationsl:::~:;X:;:"«;':::;:W:;:"«'o'!~o'!;y'
Applications-Oriented Operations~;9~ ..':'~»,~;::m~:>~"'.. ~:"«:",/.$ .. ~'.?;X'm;,::?'~w..:w.~~~l':'~~$;::-:!!::~;m9.::"«;?'~".::;.o;r..( .. ~@ .. ~},~;s:;~:;.::-~~~.:?'~:~~:m:o:» ..'%!~:;o~m::-;::Y.~~o:o'~:X-~~~~~~Example 11-31. IIR Filter (One Biquad)* TITLE IIR filter* SUBROUTINE I I R 1* IIRl == IIR FILTER (ONE BIQUAD)** EQUATIONS:d(n) a2 * d(n-2) + al * d(n-1) + x(n)*y(n) b2 * d(n-2) + b1 * d(n-1) + bO * d(n)** OR**y(n)* TYPICAL CALLING SEQUENCE:**loadloadloadloadCALLR2AROAR1BKIIR1a1*y(n-1) + a2*y(n-2) + bO*x(n)+ b1*x(n-1) + b2*x(n-2)* ARGUMENT ASSIGNMENTS:* ARGUMENT I FUNCTION* --------+-------------------------------------* R2 INPUT SAMPLE X (N)* ARO ADDRESS OF FILTER COEFFICIENTS (A2)* AR1 ADDRESS OF DELAY MODE VALUES (D (N-2) )* BK BK = 3***REGISTERS USED AS INPUT: R2, ARO, AR1, BKREGISTERS MODIFIED: RO, R1, R2, ARO, AR1REGISTER CONTAINING RESULT: RO* CYCLES: 11 WORDS: 8* FILTER*.global IIR1*IIR1**II*II*IIMPYF3MPYF3*ARO,*AR1,RO; a2 * d(n-2) -> RO*++ARO (1) , *AR1- -(1) % , Rl; b2 * d(n-2) -> RlMPYF3 *++ARO(1),*AR1,RO ; a1 * d(n-1) -> ROADDF3 RO,R2,R2 ; a2*d(n-2)+x(n) -> R2MPYF3ADDF3MPYF3STF*++ARO (1) ,*AR1--(1) %, RO ; b1 * d (n-1) -> RORO,R2,R2, a1*d(n-1)+a2*d(n-2)+x(n) -> R2*++ARO(1),R2,R2; bO * d(n) -> R2R2, *AR1++(1) %11-56Software Applications
Applications-Oriented Operations))!::::-«':;:"'::=;~~Y.:%:"-7"/.£~:.~;:;:''(Q."~~:l:'~~:~~~::%",''::::::$:"o!;~:~:~:::;:~~''::::;:;:~::;:;:;:;:::,.;:;:::msy....w..(.((.:."XX:-(.:;>::O:~h'$m~%::-.:w..(.t.::i!w.,,*::lS?::;9.'~«X'::"b.~.=:: ;'::;~:;:~"o':m.:-;;:~:~:::~~::-..":"~6:::::::'..::>."..;o;y-... ~;~:;:;:,b.;o',,;o;o;o;:;,~:~~:;::: .. ~::-.. ;o:~:~:::::;::-/.y.;o.:o;::Y.>::·:~~::::;o.::m.~~:"o':w.::~::::::Z:~:;:;w..m'.. ~~Q.>~~~Figure 11-3. Data Memory Organization for N BiquadsFilterCoefficientsLowAddress --~-... a2(O) Newest Delayb2(O)a1(0)b1 (0)bO(O)•a2(N -1)b2(N -1)a1(N-1)b1(N-1)High bO(N -1)Address .....----...........Oldest DelayInitial DelayNode Valuesd(O, n)d(O, n -1)d(O, n - 2)Empty•d(N -1, n)d(N-1, n-1)d(N-1, n-2)EmptyFinal DelayNode Valuesd(O, n -1)d(O, n-2)d(O, n)Empty•d(N -1, n -1)nCirc ular QueueWd(N -1, n - 2) Circular Queued(N-1, n)Em tyThe block register BK should be initialized to 3, and the beginning of each setof dvalues (Le., d [i,n], i = O ... N -1) should be at an address that is a multipleof 4 (the last two bits zero), as stated in the case of a single biquad .11-58. Software Applications·
Applications-Oriented OperationsExample 11-32. IIR Filters (N) 1 Biquads)* TITLE IIR FILTERS (N > BIQUADS)** SUBROUTINE IIR2*EQUATIONS: y(O,n) = x(n)** FOR (i = 0; i < N; i ++ )* {* d(i,n) = a2(i) * d(i,n-2) + a1(i) * d(i,n-1) * y(i-1,n)* y(i,n) = b2(i) * d(i,n-2) + b1(i) * d(i,n-1) * bO(i) *,d(i,n)* TYPICAL CALLING SEQUENCE:}* y (n) = y (N-l, n)* TYPICAL CALLING SEQUENCE:***********loadloadloadloadloadloadloadCALLR2AROAR1IROIR1BKRCIIR2* ARGUMENT ASSIGNMENT:ARGUMENT I FUNCTION* --------+-------------------------------------* R2 INPUT SAMPLE x (n)* ARO ADDRESS OF FILTER COEFFICIENTS (a2(O»******ARlBKIROIRlRCADDRESS OF DELAY NODE VALUESBK = 3IRO = 4IRl = 4*N-4NUMBER OF BIQUADS (N) -2(d(O,n-2»* REGISTERS USED AS INPUT; R2, ARO, AR1, IRO, IR1, BK, RC* REGISTERS MODIFIED; RO, Rl, R2, ARO, AR1, RC* REGISTERS CONTAINING RESULT: RO** CYCLES: 17 + 6 (N-1) WORDS: 17****IIR2*.global IIR2MPYF3MPYF3*ARO, *AR1, RO: a2(O) * d(O,n-2) -> RO*AR1++ (1), *AR1- -( 1) , Rl11-59
Applications-Oriented Operations~~"S"~~W~m%::-'..s.o;.sc;! .... "?"...s~..sc:.swd"q;~;S'm':*".$::!««:::=::X;Y~':~~~~~.$',,~";:;::~~...M:m::s:;:::;,;~~Y.,(.::~o;w.««~s:;?"....Y.::;,:~:;~~::~s:::;-.osw.~o;:».:~~~..::~::::::::~,(.m~.::~~«=~s:;s~S$**II*IIII***II*II*II*II**LOOP*MPYF3ADDFMPYF3ADDF3MPYF3STFRPTBMPYF3ADDF3MPYF3ADDF3MPYF3ADDF3MPYF3ADDF3b2(O) * d(O,n-2) -> R1*++ARO(1),*AR1,RO; al(O) * D(O,n-l) -> RORO, R2, R2 i First sum term of d(O,n).*++ARO(1),*AR1--(1)%,RO ib1(O) * d(O,n-l) -> RORO, R2, R2 i Second sum term of d(O,n) .*++ARO(1),R2,R2 ;bO(O) * d(O,n) -> R2R2, *AR1--(1) %LOOPStore d(O,n) ; Point to d(O,n-2)Loop for 1 R1R1,R2,R2 ; Second sum term of y(i-1,n) .*++ARO(1),*AR1,RO ;a1(i) * d(i,n-1) -> RORO,R2,R2 ; First sum of d(i,n).*++ARO (1) , *AR1--(1) %, RO ;b1 (i) * d (i, n-1) -> RORO,R2,R2 Second sum term of d(i,n) .STF R2, *AR1--(1) %; Store d(i,n) ; point to d(i,n-2)MPYF3 *++ARO(l), R2,R2; bO(i) * d(i,n) -> R2* FINAL SUMMATION*ADDF RO,R2ADDF3 Rl,R2,RO*NOP *AR1--( IR1)NOP *AR1--(1) %* RETURN SEQUENCE** end*RETS.endFirst sum term of y(n-1,n)Second sum term of y(n-1,n)Return to first biquadPoint to d(O,n-1)Return11-60Software Applications
Applications-Oriented Operations;Y,,$~.X"«~:;:;S:::;Y'h:"«,:;:;o;:::->::::x;::m.;';:;~;*;::X;:::::;:::::;:;:::;:;:;:;:i:~::x;~:::;:::i:::::;:;:::;:::':~%:::::::::::;';:;:;:::::;:::::::::::::::;:;:::::::::::;:: :::::::::;::::::::%::9.::::::::::::::::::::::::::::::::.::::::::::::"::: ::::::.;:::::::;...::::::.;:~::::;::».;:;..:::;:::::>:>o::::.;-;:;.;:::;:;:;.;::.;.:....:::-«>::.;..y:..:...;..:.;.:::.::..;.................. ~. _"·O;·;..·o"N:··~·::;...... ::.:>::::»:::~::~::::::.:::.:::=-:;:::::::::;:>':;:a):::;::::::x;:;:::::;:::;:;x::;:::~~/.~:::::11.4.2.3 Adaptive Filters (LMS <strong>Al</strong>gorithm)In some applications in digital signal processing, a filter must be adapted overtime to keep track of changing conditions. The book Theory and Design ofAdaptive Filters by Treichler, Johnson, and Larimore (Wiley-Interscience,1987) presents the theory of adaptive filters. <strong>Al</strong>though in theory, both FI RandIIR structures can be used as adaptive filters, the stability problems and thelocal optimum points that the IIR filters exhibit make them less attractive forsuch an application. Hence, until further research makes IIR filters a betterchoice, only the FIR filters are used in adaptive algorithms of practical applications.In an adaptive FIR filter, the filtering equation takes this form:y[n] = h [n,O] x[n] + h [n,1]x[n-1] + ... + h[n,N -1]x[n- (N -1)]The filter coefficients are time-dependent. In a least-mean-squares (LMS) algorithm,the coefficients are updated by an equation in this form:h[n+1,i]=h[n,1]+ ~x[n-i],i=O,1, ... ,N-1~ is a constant for the computation. The updating of the filter coefficients canbe interleaved with the computation of the filter output so that it takes 3 cyclesper filter tap to do both. The updated coefficients are written over the old filtercoefficients. Example 11-33 shows the implementation of an adaptive FIR filteron the TMS320C3x. The memory organization and the positioning of thedata in memory should follow the same rules as the above FIR filter with fixedcoefficients.11-61
Application-Oriented Operations .~~.w.::':':Y'::«;:;:;Y';~:'::;~::Y~;,:~,:-~~~ .. Y.«6'~.w,:,;::»~;~»Y .. ~M»~~~h~';'»~:'~'::~:>~Y,;~~;?m..;9.~;o,::;::~~;~~~~»,:,,:!oyN,.:e;:~>'~w.-~~~~~~~~Example 11-33. Adaptive FIR FHter (LMS <strong>Al</strong>gorithm)* TITL ADAPTIVE FIR FILTER (LMS ALGORITHM)*SUBROUTINE L M S************************************LMS*****LMS == LMS ADAPTIVE FILTEREQUATIONS: y(n) = h(n,O)*x(n) + h(n,l)*x(h-l) + ...+ h(n,N-l)*x(n-(N-l))FOR (i'= Oi i < Ni i++)h(n+l,i) = h(n,i) + tmuerr * x(n-i)TYPICAL CALLING SEQUENCE:loadloadloadloadloadCALLR4AROARlRCBKFIRARGUMENT ASSIGNMENTS:ARGUMENT I FUNCTION--------+-------------------------------------R4 I SCALE FACTOR (2 * mu * err)'ARO ADDRESS OF h(n,N-l)ARl ADDRESS OF x(n-(N-l))RC LENGTH OF FILTER - 2 (N-2)BKLENGTH OF FILTER (N)REGISTERS USED AS INPUT: R4, ARO, AR1, RC, BKREGISTERS MODIFIED: RO, R1, R2, ARO, AR1, RCREGISTER CONTAINING RESULT: ROPROGRAM SIZE: 10 wordsEXECUTION CYCLES: 12 + 3(N-1)SETUP (i = 0)MPYF3LDFMPYF3ADDF3.global LMS*ARO, *AR1, RO0.0,R2Initialize RO:h(n,N-1) * x(n-(N-1)) -> ROInitialize R2.Initialize R1:*AR1++(1)%, R4, R1; x (n-(N-1)) * tmuerr -> R1*ARO++(l) , R1, R1; h(n,N-1) + x(n-(N-1)) *11-62Software Applications
Application-Oriented Operations~y.~:::.: .•• :.!;:;:;:;:;:;:;:;:;%:::::;:;:::;:>:;:::::::;:;:::::::::::::::::::::::::::::::::::::::::::.:;:::::;:;:';:;0;:::;:::::::.:::.:::::::.:::.:::::::::::;0::::::::'.::::::::::x::::::;::::::::·.· .. ;·;:::;·;·;·;::::::·;:;·;:::::::;·~;o.;~.::;:; •• .,;:;.::;.;o;:::;~;:;:;:;.;.;::.;o.;:::; ••• ;o;.;o;.;.:.;.:·;·;:;·;·;·;· ... ·;o;·N ... o;o;o::.·;·;o;·;·.·.· ..... :.·.·.·.·.·;.;.; ••••• ; ••• ;:;.;.;.;:;.; ... ; ..... ;.;::.; ... ;.::;.;.;...;.;';';0;';:;';0.';0,';:::;';';::::0.-;'::;::9::;';-,-;0;';',-;0;::0;'::;o;.:: •• ;:::;o::;o:::; ••• ::.';:;';';o:;.;:::;:;:;:~::::::::.~;:;:::;~:::;:.~;:::;~;:;:::;:;:i11.4.3 Matrix-Vector MultiplicationIn matrix-vector multiplication, a K x N matrix of elements m(i,j) having K rowsand N columns is multiplied by an N x 1" vector to produce a K x 1 result. Themultiplier vector has elements v(j), and the product vector has elements p(i).Each one of the product-vector elements is computed by the following expression:p (i) = m (i, 0) v (0) + m (i,1) v (1) + ... + m (i, N -1) v (N -1) i = 0,1, ... , K -1This is essentially a dot product, and the matrix-vector multiplication contains,as a special case, the dot product presented in Example 11-2 on page 11-8.In pseudo-C format, the computation of the matrix multiplication is expressedbyfor (i = 0; i < K; i + +) {p(i)=Ofor ( j = 0; j < N ; j + +)p (i) = P (i) + m (i,j) * v (j)Figure 11-4 shows the data memory organization for matrix-vector multiplication,and Example 11-34shows the TMS320C3x assembly code to implementit. Note that in Example 11-34, K (number of rows) should be greater than 0,and N (number of columns) should be greater than 1.Figure 11-4. Data Memory Organization for Matrix- Vector MultiplicationIniJutResultMatrix Storage Vector Storage Vector StorageLowAddress I m(O,O)p(O)m(Oz1} v(1 ) p(1 )HighAddressI I v(O)I I• • •• • •• • •m(O N -1) v(N -1) p(K-1)m(1 0)m(1,1)•11-64 Software Applications
Application-Oriented Operations:-;:>:;-;:;:;:::;:::::::::::;:::::0::::::::::::':::::;:::::::::::::::::::::::;:::::::::::;~~o'!;:::;:::;:;:;::::::::%:::::::::::::;:;:::;:;:;:::::;:;:;:::::::;:::::-.. ;:~9.;9:;7..:;:::::::::::;:;::~::;:;::y.;:;:;:::;:;:;:;:;:;.;:::;:;:::;:::: :::::::::::;::::y;.;:;.;.;.;:::;.;.;,.;:::;-;.;-;:::.:,:::::::::,.;-;.;.;:::: ... ;o.;.;:. ••• ;::::::.;.:-;.::::;.;.;:;::~;:::;.;"
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Application-Oriented Operations:~.!:~.:.~;:;:;!.:;:;.;;~:::::;:::;:;:::::::;:::::::;:::;:::::::;:::::;:::::::::::::::::::::::::::::::::::::::::::;-;:::::::::::::::::::::::::::·';':::,:;-':::"':::':::':::::::::;';:;::::5:;y'::;o;~::;:::::::;:::;::::::::::::::';::9;:::;:::;';::");':::::':::,;:~:,;:;o::::::".:::;9;:::::;:::::;:::;:;o:,;:::;:;:;~::::::;:::::.:;·;·;·;·;·;·;·;·..:·:::::·.::·;·;.;·;·;::·:.....;v;·;.::.;.;••:.!>:;.::::••;.;.;..;••::..:....;.;.;.;:;-••;.;o....;.;:;•••;o;.;.;·..:v.';'o,;·;,.:.,::;.;.;.,;o;.;.;.;o;:•..;:.,;:.:::;,,:;••:.::::..:.....::::•• ;:::::::::::;:::;:;:::::::::::;:::::;:::;::::::::~:;:::::::;.:;:;Example 11-35. Complex, Radix-2, DIF FFTTITL COMPLEX, RADIX-2, DIF FFT** GENERIC PROGRAM FOR A LOOPED-CODE RADIX-2 FFT COMPUTATION IN TMS320C3x** THE PROGRAM IS TAKEN FROM THE BURRUS AND PARKS BOOK, P. 111.* THE (COMPLEX) DATA RESIDE IN INTERNAL MEMORY. THE COMPUTATION**IS DONE IN-PLACE, BUT THE RESULT IS MOVED TO ANOTHER MEMORYSECTION TO DEMONSTRATE THE BIT-REVERSED ADDRESSING.* THE TWIDDLE FACTORS ARE SUPPLIED IN A TABLE PUT IN A .DATA SECTION.* THIS DATA IS INCLUDED IN A SEPARATE FILE TO PRESERVE THE GENERIC* NATURE OF THE PROGRAM. FOR THE SAME PURPOSE, THE SIZE OF THE FFT* NAND LOG2(N) ARE DEFINED IN A .GLOBL DIRECTIVE AND SPECIFIED* DURING LINKING.*.globl.globl.globl.globlFFTNMSINEEntry point for e~ecutionFFT sizeLOG2(N)Address of sine tableINP.usect.BSS"IN", 1024OUTP,1024Memory with input dataMemory with output data.text* INITIALIZEFFTSIZ .wordLOGFFT .wordSINTAB .wordINPUT .wordOU1'PUT .wordFFT:LDPLDILSHLDILDILSHLDILDILDI* OUTER LOOPLOOP: NOPLDIADDILDISUBINMSINEINPOUTPFFTSIZ@FFTSIZ,IR1-2,IR10,AR6@FFTSIZ,IROl,IRO@FFTSIZ,R7l,AR7l,ARS*++AR6 (1)@INPUT,AROR7,ARO,AR2AR7,RCl,RCCommand to load data page pointerIR1=N/4, pointer for SIN/COS tableAR6 holds the current stage numberIRO=2*N1 (because ofreal/imag)R7=N2Initialize repeat counter of first loopInitialize IE inde~ (ARS=IE)Current FFT stageARO points to X(I)AR2 points to X(L)RC should be one less than desired #*' FIRST LOOPRPTBADDFSUBFBLK1*ARO, *AR2, RO ; RO=X (I) +X (L)*AR2++,*ARO++,R1; R1=X(I)-X(L)11-68Software Applications
;(.:;y'o~M::~'::W.6:;SSf.:;:os=:.x:'::;':::i(.~;$.~:;:::::'~S:O:,;:::O::S:.'?"::Ss.~s::::s::y;ss:;,:~~:::;SS.'.»::::.';~:::>:::;S:>,;:::"~~;"~,,.;.. S';S.:;S.*;~:::~;:::::;S":::"~':';":::::::;:;:".:>::"":: .. ~·:::",, ..·;o,;.. y;.,,:·:·;·;o,; .. v;S·:·;"":;:~·:·;';":;V;::·;::o;::·; ..·;..,:.,;·.·;o;·;·;·;"""·;,;..".."..::s·;·:..",,..•...•Application-Oriented Operations... ••• ... ••• ... ·.·;-.·.·.·.·.w ... ·.·;o, .. ·~;·;::·;·;:;:::::.· ... :.~.: .. :.s:;:::;ss:.:.:.,:Y.;,::·::s::.';::,::o~,:::::::::::Y.;:::::::::O:;:;,:.';:;s:;:;),::;:ADDF *AR2,*ARO,R2 R2=Y(I)+Y(L)SUBF *AR2,*ARO,R3 R3=Y (I)-Y (L)STF R2, *ARO-- Y(I)=R2 and ...II STF R3, *AR2-- Y(L)=R3BLKI STF RO, *ARO++ (IRO) ; X(I)=RO and ...IISTF* IF THIS ISCMPIBZD* MAIN INNERLDILDIINLOP: ADDILDIADDIADDIADDILDISUBILDF* SECOND LOOPRPTBSUBFSUBF*II*IIIIII*"*BLK2IIMPYFADDFMPYFSTFSUBFMPYFADDFMPYFSTFADDFSTFSTFCMPIBNERl, *AR2++ (IRO)THE LAST STAGE,@LOGFFT,AR6ENDLOOP2,ARI@SINTAB,AR4ARS,AR4ARl,ARO'2,ARI@INPUT,AROR7,ARO,AR2AR7,RC1,RC*AR4,R6X(L)=Rl and ARO,2 ARO,2 + 2*nYOU ARE DONEInit loop counter for inner loopInitialize IA index (AR4=IA)IA=IA+IEi AR4 points to cosineIncrement inner loop counter(X(I),Y(I» pointer(X(L),Y(L» pointerRC should be one less than desired #R6=SINBLK2*AR2,*ARO,R2 R2=X(I)-X(L)*+AR2,*+ARO,RlRl=Y(I)-Y(L)R2,R6,RO ; RO=R2*SIN and ...*+AR2,*+ARO,R3i R3=Y(I)+Y(L)Rl,*+AR4(IRl),R3 i R3 = Rl * COS and ...R3,*+ARO Y(I)=Y(I)+Y(L)RO,R3,R4 ; R4=Rl*COS-R2*SINRl, R6, RO i RO=Rl *SIN and ...*AR2,*ARO,R3 i R3=X(I)+X(L)R2,*+AR4(IRl),R3; R3 = R2 * COS and ...R3, *ARO++ (IRO)RO,R3,RSRS, *AR2++ (IRO)R4,*+AR2R7,ARlINLOPX(I)=X(I)+X(L) and ARO=ARO+2*NlRS=R2*COS+Rl*SINX (L)=R2*COS+Rl*SIN, incr AR2 and ...Y(L)=Rl*COS-R2*SINLoop back to the inner loopLSH 1,AR7Increment ,loop counter for next timeBRD LOOPNext FFT stage (delayed)LSH l,ARS IE=2*IELDI R7, IRO Nl=N2LSH -l,R7 N2=N2/2* STORE RESULT OUT USING BIT-REVERSED ADDRESSINGEND:LDISUBILDILDILDILDI@FFTSIZ,RC1, RC@FFTSIZ,IRO2,IRl@INPUT,ARO@OUTPUT,ARlRC=NRC should be one less than desired #IRO=size of FFT=N11-69
Application-Oriented Operations.:~~.:.:.:.u.;e.:..:N..y~;,;~:;:;,:;·;o..:x:;:::;m;:::;c;:::~:;.:;:;o;::-».:X!::;-£.:~.:.:b:;":':':Q."':.u.:.:.....'O!.:...•...:.Y..·u....:;..:;O;Y.;·~Y.NN.;Y.~:~;·.:M:.~Y.N;Y.~obw.W....•....;.)o.. ~;:;y~;·;. ..;o;o».;o~;..~;·~.;.......·.·;o;o»N.o;O..;O.·.w;O.·;YN»;·;:;o;oN;· ;oA~·;o.·N;..;.~.. o; ..'Y.......•... w;..YM.Yhw.v.-;.:N;.:..,; .. ~" ...........,;w.YhY.A......,,;·4.. W ..........·N~·;Y...o~~;~... ~'9Y~;eN~~~*~:*" .. ~IIBITRVIIRPTBLDFLDFSTFSTFBITRV*+ARO(l),RO*ARO++(IRO)B,RlRO,*+AR1(1)Rl, *AR1++ (IR1)SELFBR.endSELFBranch to itself at the end11-70Software Applications
Application-Oriented OperationsExample 11-36. Table With Twiddle Factors for a 64-Point FFT**TITL TABLE WITH TWIDDLE FACTORS FOR A 64-POINT FFT** FILE TO BE LINKED WITH THE SOURCE CODE FOR A 64-POINT, RADIX-2 FFT.*.globl.globl.globlSINENMNMSINECOSINE.set.set.data.float.float.float. float.float.float. float. float.float.float.float.float. float.float.float. float.float. float.float.float.float.float.float.float.float.float.float.float.float.float.float.float. float.float.float.float.float.float.float.float.float6460.0000000.0980170.1950900.2902850.3826830.4713970.5555700.6343930.7071070.7730100.8314700.8819210.9238800.9569400.9807850.9951851.0000000.9951850.9807850.9569400.9238800.8819210.8314700.7730100.7071070.6343930.5555700.4713970.3826830.2902850.1950900.0980170.000000-0.098017-0.195090-0.290285-0.382683-0.471397-0.555570-0.634393-0.70710711-71
Application-Oriented Operations~:::::;:::"«-:::;:""%:::;:::::".:;:;:::::::::;:;%:;:::::::"-:::::"-:::::::::::::;:::;:::::;:::,.:::::::;:::;:::::::;:::::::;:::,.:::::::~;:;:,.:::::::,.:::,.(.:::::o:::::::::::::::::::::::::;:';:::::::-«:%:::::::::::;:'(0:'.(.:::::::::::::::;:'.:'.::%:::::::;:,.:'-::::::::::::~:::,(.:::::::::::::::::::::r.::::::::::::::-:::::::~.:::::.~;:&;:::::O:~:~:;:::::::::::::::;:;:;:::;::::X::::::::N::::~:::::;:t:;:::;:::~:::::'(.(.:::;~;:::::;:::::',(,::::'::~::::::::::::::::::::::::::::'':;:::;:::;:::::::;::7.;:::::::::::::::::,..-::::::,-%:::''(':::'.::::::t.:::::".:::::::::::;::s:.::;. float -0.773010.float -0.831470.float -0.881921. float -0.923880.float -0.956940.float -0.980785. float -0.995185. float -1.000000.float -0.995185. float -0.980785.float -0.956940.float -0.923880.float -0.881921.float -0.831470.float -0.773010.float -0.707107.float -0.634393.float -0.555570.float -0.471397.float -0.382683. float -0.290285. float -0.195090. float -0.098017. float 0.000000. float 0.098017. float 0.195090.float 0.290285.float 0.382683.float 0.471397. float 0.555570. float 0.634393. float 0.707107.float 0.773010.float 0.831470.float 0.881921.float 0.923880.float 0.956940. float 0.980785.float 0.995185The radix-2 algorithm has tutorial value because it is relatively easy to understandhow the FFT algorithm functions. However, radix-4 implementations canincrease the speed ofthe execution by reducing the overall arithmetic required.Example 11-37 shows the generic implementation of a complex, DIF FFT inradix-4. A companion table, like the one in Example 11-36, should have a valueof M equal to the 10gN, where the base of the logarithm is four.11-72Software Applications
Application-Oriented OperationsFFT:* INITIALIZE DATA LOCATIONSLDP TEMP Command to load data page counterLDI @TEMP,AROLDI @STORE,ARILDI *ARO++,RO Xfer data from one ~emory to the otherSTI RO,*AR1++LDI *ARO++,ROSTI RO,*AR1++LDI *ARO++,ROSTI RO,*AR1++LDI *ARO,ROSTI RO,*ARlLDPLDILDILDILDISTILSHLSHLDISTILSHSTIADDISTISUBILSH* OUTER LOOPLOOP:LDIADDIADDIADDILDISUBI* FIRST LOOPRPTBADDF*ADDF**IIIIIIADDFSUBFSTFSUBFLDFLDFADDFADDFSTFADDFSUBFSTFFFTSIZ@FFTSIZ,RO@FFTSIZ,IRO@FFTSIZ,IRlO,AR7AR7,@STAGE1,IRO-2,IRl1,AR7AR7,@RPTCNT-2,ROAR7,@IEINDX2,RORO, @.JT2,RO1,RO@INPUT,ARORO,ARO,ARIRO,ARl,AR2RO,AR2,AR3@RPTCNT,RC1,RCBLKl*+ARO,*+AR2,Rl*+AR3,*+ARl,R3R3,Rl,R6*+AR2,*+ARO,R4R6,*+AROR3,Rl*AR2,R5*+ARl,R7*AR3,*AR1,R3R5,*ARO,RlRl,*+ARlR3,Rl,R6R5,*ARO,R2R6, *ARO++ (IRO)Command to load data page pointer@STAGE holds the current stage numberIRO=2*Nl (because of real/imag)IR1=N/4, pointer for SIN/COS tableInitialize repeat counter of first loopInitialize IE inde~JT=RO/2+2RO=N2ARO points to X(I)ARI points to X(Il)AR2 points to X(I2)AR3 points to X(I3)RC should be one less than desired #Rl=Y(I)+Y(I2)R3=Y(Il)+Y(I3)R6=Rl+R3R4=Y (I)-Y (12)Y (I) =Rl+R3Rl=Rl-R3R5=X (12)R7=Y(Il)R3=X (II) +X (13)Rl=X (I) +X (12)Y (Il) =Rl-R3R6=Rl+R3R2=X (I) -X (12)X(I)=Rl+R311-74Software Applications
Application-Oriented Operations-=~~'$::,;:~~~::,::-«::;,~~~o:~~..'X';:«-:;:::::;:;:;:l:::O:::»';~....,;:::;=",::;~.:::::::~~.:;qn";~:«-:o,,,,«,,:"·::-~;O»X·:~;V;·»7":"'W""""'N::""'»:·»'>""""""";'-;·~;O;·;O:so.:~M...;..·..;..·~N..;v;.-.. X ....................•...·_···._..•• o; .. y;o~;..; ...,;9'N.-WN...................................;................................;........... oYM~;:.~.w.~~>:;:>~ ..:;~.. :::;9.;,:.!':::
Application-Oriented Operations;;;:;Y;-';:;:;~:>:;':~':O:::::;:;Y/.::::;:;::9.:Y;:,::;:::;::::: .. ;:;:::;O~:;::::::::%:;~:;:;:;:;::y'>';::-;:;':~:;:«~:~>'::;::>:;:;~~~>:::~"'::;':Y.>~~,;y~~y;:~;:;:;~:>,::;y;:;:~::~>,;~:~y.;%%:";:'::;~:;SY;':';':~y.::;:;,;\o:;~~,:y.>,o::~:>:;,::;: .. .::::;,:s-m.s~:»>,:x:;y;:;~:::>,::::;,;,:,,~sy.>';:~y';':S~:S·>'~::~::N.:::s~>::~:»»·:s:;-~y;~~y.>,;~:~:;y.~~::*,,:>.;(.:::"o:"o:~.«::::::~***IIII*IIIIIIIIIIRPTBADDFADDFADDFSUBF; SECOND LOOPBLK2*+AR2,*+ARO,R3*+AR3,*+AR1,R5R5,R3,R6*+AR2,*+ARO,R4R3=Y(I)+Y(I2)R5=Y(I1)+Y(I3)R6=R3+R5R4=Y(I)-Y(I2)R3=R3-R5R1=X(I)+X(I2)R5=X(I1)+X(I3)SUBF R5,R3ADDF *AR2,*ARO,R1ADDF *AR3,*AR1,R5 ,MPYF R3,*+AR5(IR1)~R6 R6=R3*C02STF R6,*+ARO Y(I)=R3+R5ADDF R5,R1,R7 R7=R1+R5SUBF *AR2,*ARO,R2 R2=X (I) -x (I2)SUBF R5,R1 R1=R1-R5MPYF R1,*AR5,R7 R7=R1*SI2STF R7, *ARO++ (IRO) X(I)=R1+R5SUBF R7,R6 R6=R3*C02-R1*SI2SUBF *+AR3,*+AR1,R5R5=Y(I1)-Y(I3)MPYF Rl,*+AR5(IR1),R7 R7=Rl*C02STF R6,*+ARl Y(Il)=R3*C02-R1*SI2MPYF R3,*AR5,R6 R6=R3*SI2ADDF R7,R6 R6=R1*C02+R3*SI2ADDF R5,R2,R1 R1=R2+R5SUBF R5,R2 R2=R2-f-5SUBF *AR3,*AR1,R5 R5=X (11) -x (13)SUBF R5,R4,R3 R3=R4-R5ADDF R5,R4 R4=R4+R5MPYF R3,*+AR4(IR1),R6 R6=R3*C01STF R6, *AR1++ (IRO) X(I1)=R1*C02+R3*SI2MPYF R1,*AR4,R7 R7=R1*SI1SUBF R7,R6 ; R6=R3*C01-R1*SI1MPYF Rl, *+AR4 (IR1) ,R6 ; R6=R1*C01STF R6,*+AR2 Y(I2)=R3*C01-R1*SI1MPYF R3,*AR4,R7 R7=R3*SI1ADDF R7,R6 ; R6=R1*C01+R3*SI1MPYF R4, *+AR6 (IR1) , R6 ; R6=R4*C03STF R6, *AR2++ (IRO) X(I2)=R1*C01+R3*SI1MPYF R2,*AR6,R7 R7=R2*SI3SUBF R7,R6 R6=R4*C03-R2*SI3MPYF R2,*+AR6(IR1),R6 R6=R2*C03STF R6,*+AR3 Y(I3)=R4*C03-R2*SI3MPYF R4,*AR6,R7 R7=R4*SI3ADDF R7,R6 R6=R2*C03+R4*SI311-76Software Applications
Application-Oriented Operations::;::*:::y;-;:::;::::::::::::::>:;:;:::;:~:::::::::;::m:::::::::-;:;:::.::;:::::::::::;:;:;::::~~;y.;:;::>:;::::::::::s.;:::;so;y,;:::::;:;:::::;,;:::::;,~;::::::::*::;: :::X;:;:~~:*;":*;-'::;:'::;:':::::::::::';~::';~;",!::;'t:;*:::....::::::::::::;.;:~.J!:":::::::::v.::;::·;:;';~::;s:::;·::::;::,,,,:":y';::*-:·:y,::::::::;Y:*6'~::';';";:;::':y':.,;.:.... ~.;..:.;.;..; ...;.;.;:;:.. ~ ...........;.;....-;...;::.:.;,:*~:v.;",,;!.·:·o!;w.:::Y.':::::::'::;';":;ili:::::~;o,:::::::~:;::o;:::::;:,~::.:::e;::~:~::::y......x:::;s:BLK2*STFR6, *AR3++ (IRO)x(i3)=R2*C03+R4*SI3CMPIBPBR@LPCNT,ROINLOPCONTLOOP BACK TO THE INNER LOOP* SPECIAL BUTTERFLY FOR W=JSPCLLDILSHADDIIR1,AR4-1,AR4@SINTAB,AR4Point to SIN(4S)Create cosine index AR4=C021***II*IIIIIIBLK3IIRPTBADDFSUBFADDFSUBFADDFSUBFADDFADDFSUBFADDFSTFSTFSUBFSUBFSTFSTFADDFSUBFSUBFADDFSUBFMPYFADDFMPYFSTFSUBFMPYFSTFADDFMPYFSTFSTFBLK3*AR2,*ARO,R1*AR2,*ARO,R2*+AR2,*+ARO,R3*+AR2,*+ARO,R4*AR3,*AR1,RSR1,RS,R6RS,R1*+AR3,*+AR1,R5R5,R3,R7R5,R3R3,*+AROR1, *ARO++ (IRO)*AR3,*AR1,R1*+AR3,*+ARl,R3R6,*+ARIR7,*AR1++(IRO)R3,R2,RSR2,R3,R2R1,R4,R3R1,R4R5,R3,Rl*AR4,RlRS,R3*AR4,R3R1,*+AR2R4,R2,R1*AR4,RlR3, *AR2++ (IRO)R4,R2*AR4,R2R1,*+AR3R2, *AR3++ (IRO)Rl=X(I)+X(I2)R2=X(I)-X(I2)R3=Y(I)+Y(I2)R4=Y(I)-Y(I2)RS=X(Il)+X(I3)R6=RS-R1Rl=R1+RSR5=Y (11) +Y (I3)R7=R3-R5R3=R3+R5Y(I)=R3+R5X(I)=Rl+R5Rl=X (Il)-X (13)R3=Y(I1)-Y(I3)Y(Il)=R5-RlX(Il)=R3-R5RS=R2+R3R2=-R2+R3R3=R4-RlR4=R4+R1Rl=R3-R5Rl=Rl*C021R3=R3+RSR3=R3*C021Y(I2)=(R3-R5)*C021Rl=R2-R4Rl=Rl*C021X(I2)=(R3+R5)*C021R2=R2+R4R2=R2*C021Y(I3)=-(R4-R2)*C021X(I3)=(R4+R2)*C021CMPIBPD@LPCNT,ROINLOPLoop back to the inner loop11-77
Application-Oriented Operations..... Y.o";.y,.i:;-.. ;oo':.:;:O:';9...·;:;:;-)'.::;:.·... ~9:$~y;::-.:x:::!".:;:;:;:::::",z~...:::::"~ .. s:;s· ...:;:;...;-,·...•...•.................... M ...........-.:;o;o;......... M .. o;:x~y.y' ....;y;y;.m·;.;...»;....:·;..·x.....«"""......;««........·;y-........ M ....... m;y;w .............·;o;·;o;.... x«·;·;y; .......;...........;O';...;O;OXY~.......;o;y.·•..,......;.....;«.....;y........;O"~..... x ..........'»;~...... XOO~O;«:»' .... i:'~~~~CONT LDI @RPTCNT,AR7LDI @IEINDX,AR6LSH 2,AR7 Increment repeat counter for?< next timeSTI AR7,@RPTCNTLSH 2,AR6 IE=4*IESTI AR6,@IEINDXLDI RO,IRO Nl=N2LSH -3,ROADDI 2,ROSTI RO,@JT JT=:=N2/2+2SUBI 2,ROLSH 1,RO N2=N2/4BR LOOP Next FFT stage* STORE RESULT OUT USING BIT-REVERSED ADDRESSINGEND:LDI @FFTSIZ,RC RC=NSUBI 1,RC RC should be one less than desired #LDI @FFTSIZ,IRO IRO=size of FFT=NLDI 2,IRlLDI @INPUT,AROLDP STORELDI @STORE,ARlIIBITRVIISELF·RPTBLDFLDFSTFSTFBITRV*+ARO(l),RO*ARO++(IRO)B,RlRO,*+AR1(1)Rl, *AR1++ (IR1)BR SELF ; Branch to itself at the end..endMost often, the data to be transformed is a sequence of real numbers. In thiscase, the FFT demonstrates certain symmetries that permit the reduction ofthe computational load even further. Example 11-38 shows the generic implementationof a real-valued, radix-2 FFT. For such an FFT, the total storage requiredfor a length-N transform is only N locations; in a complex FFT, 2N arenecessary. Recovery of the rest of the points is based on the symmetry conditions.11-78Software Applications
Application-Oriented Operations-=::";w~=::;o;:;:;....;:;o:;...;~.:;:;zrH;::::-.:r.::"=;.»;:-;.:;!".(.::~-...::;:;'!:~~~~;~;:;:;:;:;:..w..:::;-;:;:~«.:::.:.:xo?)'.::-.(.;x:;e;-.... ~·~Q;:;:;(0:;~::-.. ~;:~.~~;:l:;:~:;:.::.;:· ...:.:.:.z:~:«6:::m;:;:.~;c..)!.y~~~~:.;:;.~,o:~:;~w;:;:~~,;:;oa~M~:'~;~~:;:;s:.1:Example 11-38. Real, Radix-2 FFT* TITL REAL, RADIX-2 FFT* GENERIC PROGRAM TO DO A RADIX-2 REAL FFT COMPUTATION IN TMS320C3x.* THE PROGRAM IS TAKEN FROM THE PAPER BY SORENSEN ET AL., JUNE 1987* ISSUE OF THE TRANSACTIONS ON ASSP.* THE REAL. DATA RESIDE IN INTERNAL MEMORY. THE COMPUTATION IS* DONE IN-PLACE. THE BIT-REVERSAL IS DONE AT THE BEGINNING OF* THE PROGRAM.THE TWIDDLE FACTORS ARE SUPPLIED IN A TABLE PUT IN A .DATA* SECTION. THIS DATA IS INCLUDED IN A SEPARATE FILE TO PRESERVE* THE GENERIC NATURE OF THE PROGRAM. FOR THE SAME PURPOSE, THESIZE OF THE FFT NAND LOG2(N) ARE DEFINED IN A .GLOBL DIRECTIVE* AND SPECIFIED DURING LINKING. THE LENGTH OF THE TABLE IS* N/4 + N/4 = N/2.**.globl.globl.globl.globlFFTNMSINEEntry point for executionFFT sizeLOG2(N)Address of sine table.bss.text* INITIALIZEINP,1024Memory with input dataFFTSIZ .word NLOGFFT .word MSINTAB .word SINEINPUT .word INPFFT: LDP FFTSIZ; Command to load data page printer* DO THE BIT-REVERSING AT THE BEGINNINGLDI @FFTSIZ,RC RC=NSUBI 1,RC RC should be one less than desired #LDI @FFTSIZ,IROLSH -1, IROIRO=half the size of FFT=N/2LDI @INPUT,AROLDI @INPUT,ARlIIIIRPTBCMPIBGELDFLDFSTFSTFBITRVAR1,AROCONT*ARO,RO*AR1,RlRO,*AR1R1,*AROExchange locations onlyif ARO
Application-Oriented OperationsCaNTBITRVNapNap*ARO++*AR1++(IRO)B* LENGTH-TWO BUTTERFLIESLDI @INPUT,ARO ARO points to X(I)LDI IRO,RC Repeat N/2 timesSUBI 1,RC RC should be one less than desired #RPTB BLK1ADDF *+ARO,*ARO++,RO* RO=X(I)+X(I+1)SUBF *ARO,*-ARO,R1* R1=X (I)-X (1+1)BLK1 STF RO,*-ARO X(I)=X(I)+X(I+1)II STF R1,*ARO++ X(I+l)=X(I)-X(I+l)* FIRST PASS OF THE DO-20 LOOP (STAGE K=2 IN DO-10 LOOP)LDILDILDILSHSUBI@INPUT,ARO2,IRO@FFTSIZ,RC-2,RC1,RCARO points to X(I)IRO=2=N2Repeat N/4 timesRC should be one less than desired #**IIBLK2*IIRPTBADDFSUBFNEGFSTFSTFSTFBLK2*+ARO(IRO),*ARO++(IRO),RO; RO=X (I) +X (1+2)*ARO,*-ARO(IRO),R1*+ARO,RORO, *-ARO (IRO)R1, *ARO++ (IRO)RO,_*+ARO* MAIN LOOP (FFT STAGES)LOOPLDILSHLDILDILDILSHLSHLSH@FFTSIZ,IRO-2,IRO3,R51,R42,R3-l,IRO1,R41,R3R1=X (I) -x (1+2)RO=-X (1+3)X(I)=X(I)+X(I+2)* INNER LOOP (DO-20 LOOP IN THE PROGRAM)INLOPLDILDIADDILDI@INPUT,AR5IRO,ARO@SINTAB,AROR4,IR1X(I+2)=X(I)-X(I+2)X (1+3) =-X (1+3)IRO=inde:.: for ER5 holds the current stage numberR4=N4R3=N2I;:=E/2N4=2*N4N2=2*N2AR5 points to X(I)ARO points to SIN/COS tableIR1=N4LDIADDILDIAR5,ARI1,AR1ARl,AR3ARl points to X(Il)=X(I+J)11-80Software Applications
Application-Oriented Operations~.:;'.'::;:;:::::::::;!o~;:~;:-.'!>!::;:::".::;:::::-.:;:::;:;:::::::::::~;:::;:::;:;:::;:;:;:::;:::::;:::;';:;:;:;';:.''' ••• :;.;.;.;:;.; •• :::: ..... ; ... ;.;.;.;.;.;-; ••• ; ..... ::; ••••• ::;:::;';'::;0;',';';';';',';';',';':',';';';';';';';',0;0 .. ;';' ........ ;.; ..... ;.;.;.;.;.:: •• ;.; ••• ;.;.; ... ;.;.; ••• ;.; ..... ; •• ' •••• ; •• 0;0;: •• ; ..... ; ....... ;.;.; ••• ; •• 0;0 .. ;.; ... ;.; ........... ; ••••••••• ;-:-•• ; ••••• ; ••••••• ; ....... ; ........... ; ......... ,' ........................................................................................ ,;: ................. : ... :.:.:.:::::.:.:.:::::;:~::::::::::::::;:::::::;::~.:;:;:;:;:;::?Example 11-38. Real, Radix-2 FFT (Concluded)ADDILDISUBIADDIR3,AR3AR3,AR22,AR2R3,AR2,AR4AR3 points to X(I3)=X(I+J+N2)AR2 points to X (I2) =X (I-J+N2)AR4 points to X (14) =X (I-J+Nl)***II*IILDFADDFSUBFSTFNEGFNEGFSTFSTF*AR5++(IR1),RO; RO=X (I)*+AR5(IR1),RO,Rl, Rl=X (I) +X (1+N2)·RO,*++AR5(IR1),RORO=-X (I) +X (I+N2)Rl, *-AR5 (IR1) X(I)=X(I)+X(I+N2)RORO=X (I) -X (I+N2)*++AR5(IR1),RlRO,*AR5Rl,*AR5*INNERMOST LOOPRl=-X (I+N4+N2)X(I+N2)=X(I)-X(I+N2)X(I+N4+N2)=-X(I+N4+N2)LDILSHLDISUBI@FFTSIZ,IRl-2,IRlR4,RC2,RCIR1=separation between SIN/COS tblsRepeat N4-1 times*II*IIIIIIBLK3RPTBMPYFMPYFMPYFADDFMPYFSUBFSUBFADDFSTFADDFSTFSUBFSTFSTFSUBIADDICMPIBLTDADDINOPNOPBLK3*AR3,*+ARO(IR1),RO; RO=X (13) *COS*AR4,*ARO,Rl ; Rl=X(I4)*SIN*AR4,*+ARO(IR1),Rl ; Rl~X(I4)*COSRO,Rl,R2 ; .R2=X(I3)*COS+X(I4)*SIN*AR3,*ARO++(IRO),RORO,Rl,RO*AR2,RO,Rl*AR2,RO,RlRl,*AR3++*AR1,R2,RlRl, *AR4--R2,*AR1,RlRl,*AR1++Rl, *AR2--.@INPUT, AR5R4,AR5@FFTSIZ,AR5INLOP@INPUT,AR5RO=X(I3)*SINRO=-X(I3) *SIN+X(I4) *COSRl=-X(I2)+RORl=X(I2)+ROX(I3)=-X(I2)+RORl=X(Il)+R2X(I4)=X(I2)+RORl=X(Il)-R2X(Il)=X(Il)+R2X (12) =X (Il)-R2AR5=I+NlLoop back to the inner loopADDI 1,R5CMPI @LOGFFT,R5BLE LOOPENDBR.endENDBranch to itself at the end.11-81
Application-Oriented OperationsTable 11-1. TMS320C3x FFT Timing BenchmarksThe TMS320C3x quickly executes FFT lengths up to 1024 points (complex)or 2048 (real), covering most applications, because it can do so almost entirelyin on-chip memory. Table 11-1 summarizes the execution time required forFFT lengths between 64 and 1024 points for the three algorithms inExample 11-35,11-37, and 11-38.Numberof PointsFFTTlmingIn millisecondsRADIX-2 RADlX-4 RADIX-2(Complex) (complex) (real)64 0.165 0.123 0.077128 0.370 - 0.174256 0.816 0.624 0.387512 1.784 - 0.8571024 3.873 3.040 1.8791024* 2.366• Code is found in Digital Signal Processing Applications With the TMS320 Family,Volume 3.11.4.5 Lattice FiltersThe lattice form is an alternative way of implementing digital filters; it has foundapplications in speech processing, spectral estimation, and other areas. In thisdiscussion, the notation and terminology from speech processing applicationsare used. .If H(z) is the transfer function of a digital filter that has only poles, A(z) = 1/H(z)will be a filter having only zeros, and it will be called the inverse filter. The inverselattice filter is shown in Figure 11-5. These equations describe the filterin mathematical terms:f(i,n) =f(i-1,n) +k(i) b(i-1,n-1)b(i,n) =b(i-1,n-1) +k(i) f(i-1,n)Initial conditions:f (O,n) = b (O,n) = x (n)Final conditions:y(n) = f( p,n).In the above equation, f (i,n) is the forward error, b (i,n) is the backward error,k (i) is the i-th reflection coefficient, x (n) is the input, and y (n) is the ou.tputsignal. The order of the filter (i.e., the number of stages) is p. In the linear predictivecoding (LPC) method of speech processing, the inverse lattice filter isused during analysis, and the (forward) lattice filter during speech synthesis.11-82Software Applications
Application-Oriented Operations~~:«
Application-Oriented Operations~;O),;O/.;O;:;~:::;:;O':::::::?::::;~~'9;:'::;::::::7"/,::::::?';:;!O:1')!~~?:$'»':~XQ.~::;:;o,::::::::;:::::~~::;o>':::~;9"'':::Y"''''N.~»:-rQY#P'~~»>,,*>>>.'.(q~"?~:?"~>;O~''''Q':';::9),$;:~.a;o» .... ».:::x~"'m~~:>':~.;o"/.a:;o;-'p~;e;.o;oY.Q'..x9m.:69»;:~»'~~;:;:)»>~>~;O.:c;o~:e>;o~ ROASSUME F(P,N) -> R2.SUBF3 RO,R2,R2 ; F(P,N)-K(P)*B(P~1,N-1) =F(P-1,N) _.> R2II MPYF3 *-~RO (1), *-~R1 (1) , RO; K(P-1) * B(P-2,N-1) -> ROSUBF3 RO,R2,R2 ; F(P-1,N)-K(P-1)*B(P-2,N-1) =F(p-2,N) -> R2IIMPYF3MPYF3ADDF3*-~RO (1), *-~R1 (1) ,ROK(P-2) * B(P-3,~-1) -> ROR2,*+ARO(1),R1; F(P-2,N) * K(P-1) -> R1R1,*+AR1(1),R3; F(P-2,N) * K(P-1) + B(P-2,N-l)B(P-1,N) -> R311-86Software Applications
Application-Oriented Operations;::-;::::s:;:;:::;::::~:;~:::::::::::::
Programming Tips~):::;:::::;:;:::~::~~:::;y';'»,:::::!;'»,::::::;:::::::«::::;';*::::;!(.~~;:;!~.:::i!o::::'::%:::::O:;Y,::::~::0:9:;';!::~;'):;O'::::;:;:~«~;Y,::::-O:~"::;Y;::!::::::>';'»';'h!'l':' ..;:;c::::::;:;Y,::::::::~:':~:Y.::~::>::*";:;::::*''::::::::;=>-'::'=l:"o:::;'»';C;9,::~::;Y,::«::~:,::~;:»,::::::::;:;,;:::::;o»::::!:~:~~ww.o:::;:~::;%:::~~::«::::::>::::!i%::M:*;:;:::::'«::~~::~::~'::~::;'':::::::!:!I:::o:o:::~11.5 Programming TipsProgramming style is highly personal and reflects each individual's preferencesand experiences. The purpose of this section is not to impose any particularstyle. Instead, it emphasizes some of the features of the TMS320C3x thatcan help in producing faster and/or shorter programs. The tips cover both Ccompiler and assembly language programming.11.5.1 C-Callable RoutinesThe TMS320C3x was designed with a large register file, software stack, andlarge memory space in orderto implement a high-level language (HLL) compilereasily. The first such implementation supplied is a C compiler. Use of the Ccompiler increases the transportability of applications that have been testedon large, general-purpose computers, and decreases their porting time.For best usage of the compiler, complete the following steps:1) Write the application in the high-level language.2) Debug the program.3) Estimate if it runs in real-time.4) If it doesn't, identify places where most of the execution time is spent.5) Optimize these areas by writing assembly language routines that implementthe functions.6) Call the routines from the C program as C functions.When writing a C program, you can increase the execution speed by maximizingthe use of register variables. For more information, refer to the TMS320C3xC Compiler Reference Guide.Certain conventions must be observed in writing a C-callable routine. Theseconventions are outlined in the Runtime Environment chapter of theTMS320C3x C Compiler Reference Guide. Certain registers are saved by thecalling function, and others need to be saved by the called function. The C compilermanual helps achieve a clean interface. The end result is the readabilityand natural flow of a high-level language combined with the efficiency and special-featureuse of assembly language.11.5.2 Hints for Assembly CodingEach program has particular requirements. Not all possible optimizations willmake sense in every case. The suggestions presented in this section can beused as a checklist of available software tools.11-88Software Applications
11-90 Software Applications
Hardware Applications
Hardware Applications
Chapter 12Hardware Applications:~:~:~:~:::::::::$::::;:;:;:;:;:;:::~:~:~::~::::::::::;:::::;:::;:~::::::~~;:~::::;~:::~~::::::::~~:~~::~::::::::::~:::::;:::;:;:;:~~:~f~::~:::;:;::;:~%:::~;~~~~:;:;:::~!§::~::~:~;::;:~::::;::~~~::;:;:::::::::::::::;::::;::::::~::::::::::;:::::::~: :::::~::;:*~:~;~::::::;::~:;:;:::;:::~::::x~::::::::*:*:::::::!::;::::::::::::::;:::::::::~:::;:::~~::~~:::::*::;:~::::;::;:::::;:::::::::::~::::::~::::;:::~;:::::::::*:;::~:::::::::::::~::~~:~:;~::;:~::::::X*:::::;:::::::::::::~;~::;::::X:~:;:::~::::::::::::::::;:;::::::::::;:::::The TMS320C3x's advanced interface design can be used to implement awide variety of system configurations. Its two external buses and DMA capabilityprovide a parallel 32-bit interface to external devices, while the interrupt interface,dual serial ports, and general-purpose digital 1/0 provide communicationwith a muHitude of peripherals.This chapter describes how to use the TMS320C3x's interfaces to connect tovarious external devices. Specific discussions include implementation of parallelinterface to devices with and without wait states, use of general-purpose110, and system control functions. <strong>Al</strong>l interfaces shown in this chapter havebeen built and tested to verify proper operation and apply to theTMS320C30-33. Comparable designs for the other TMS320C3x devices canbe implemented with appropriate logic.Major topics discussed in this chapter are as follows:[J System Configuration Options Overview (Section 12.1 on page 12-2)Q Primary Bus Interface (Section 12.2 on page 12-4)• Zero Wait-State Interface to RAMsII Ready Generation• Bank Switching Techniques[J Expansion Bus Interface (Section 12.3 on page 12-18)• AID Converter Interface• DIA Converter Interface[J System Control Functions (Section 12.4 on page 12-25).1'1 Clock Oscillator Circuitry• Reset Signal Generator[J Serial Port Interface (Section 12.5 on page12-30)[J User Target Design Considerations When Using the XDS1000(Section 12.6 on page 12-34)[J User Target Design Considerations When Using the Hewlett Package64776 AnalYSis Subsystem (Section 12.7 on page 12-37).[J TMS320C30 and TMS320C31 Differences (Section 12.8 on page 12-41).12-1
System Configuration Options Overview12.1 System Configuration Option$ OverviewThe various TMS320C3x interfaces connect to a wide variety of different devicetypes. Each of these interfaces is tailored to a particular family of devices.12.1.1 Categories of Interfaces on the T.MS320C3xThe interface types on the TMS320C3x fall into several different categories,depending on the devices to which they are intended to be connected. Eachinterface comprises one or more signal lines that transfer information and controlits operation. Shown in Figure 12-1 are the signal line groupings for eachof these various interfaces.Figure 12-1. External Interfaces on the TMS320C3xSystemControlprimar y {'BusExpansion BUS{(TMS320C30 only)DataAddressControl {System ResetMaster Clock {Clock Outputs {ROM Enable(TMS320C30 only)Boot load Enable(TMS320C31 only)~ ,32.: ,24"'" "~....~"'"~"'"~...."'".,~ D31-00A23-AOR/WSTRB~ RDY~ RESETX1~ X2/CLKINH1H3~ MC/MP. ~ MCBUMPHOLD ~HOLDA-- ....INT3-0 "lACK)(F1-0 .~TClKO ~TCLK1 I~CLKXO I~DXO ~FSXO ~ClKRO ~DRO ~FSRO ~ClKX1 ~' 4.... ,32DX1 I~Data~ XD31-XDO:: ,,13FSX1 ~....iAddress ....XA12-XAOClKR1 I~...........XRIWDR1 ~...~ XRDYFSR1....~ Control .... ....IOSTRB"'"MSTRBTMS320C3x...." ...........~.......................} External DMA Interface} External Interrupt InterfaceExternal Flags} Timer InterfaceSerial Port 0Serial Port 1(TMS320C30 only)<strong>Al</strong>l of the interfaces are independent of one another and different operationsmay be performed simultaneously on each interface.The primary and expansion buses implement the memory-mapped interfaceto the device. The external DMA interface allows external devices to cause theprocessor to relinquish the primary bus and allow direct memory access.12-2Hardware Applications
System ConfigurationOverview12.1.2 Typical System Block DiagramFigure 12-2. Possible System ConfigurationsThe devices that can be interfaced to the TMS320C3x include memory, DMAdevices, and numerous parallel and serial peripherals and 110 devices.Figure 12-2 illustrates a typical configuration of a TMS320C3x system with differenttypesof external devices and the interfaces to which they are connected.MemoryMemoryPeripheralsTMS320C3xExternal DMA InterfacePeripheralsPrimary BusExpansion BusPeripheralsInterruptInterfaceTimer InterfaceI/O DevicesExternal FlagsSystemControlSerial SerialPorts PortsBit 110TCM29C13CODECClock andResetGenerators,etc.TLC3204xAICAnalog I/OThis block diagram constitutes essentially a fully expanded system. In an actualdesign, any subset of the illustrated configuration may be used as appropriate.12-3
12.2 Primary Bus InterfaceThe TMS320C3x uses the primary bus to access the majority of itsmemory-mapped locations. Therefore, typically, when a large amount of externalmemory is required in a system, it is interfaced to the primary bus. The expansionbus (discussed in Section 12.3 on page 12-18) actually comprises twomutually exclusive interfaces, controlled by the MSTRB and IOSTRB signals,respectively. Cycles on the expansion bus controlled by the MSTRB signal areessentially equivalent to cycles on the primary bus, with the exception thatbank switching is not implemented on the expansion bus. Accordingly, the discussionof primary bus cycles in this section applies equally to MSTRB cycleson the expansion bus.<strong>Al</strong>though both the primary bus and the expansion bus may be used to interfaceto a wide variety of devices, the devices most commonly interfaced to thesebuses are memories. Therefore, detailed examples of memory interface arepresented in this section.12.2.1 Zero Wait-State Interface to Static RAMsZero wait-state read access time for the TMS320C3x is determined by the differencebetween the cycle time (specification 10 on page 13-21) and the sumof the times for H1 low to address valid (specification 11 on page 13-23) anddata setup before next H1 low (specification 15.1 on page 13-23). For example,for full-speed, zero wait-state interface to any device, the 60-nsTMS320C3x requires a read access time of 30 ns from address stable to datavalid. Because, for most memories, access time from chip select is the sameas access time from address, it is theoretically possible to use 30-ns memoriesat full speed with the TMS320C3x-33. This, however, dictates that there be nodelays present between the processor and the memories. This is usually notthe case in practice, because of interconnection delays and the fact that somegating is normally required for chip-select generation. Therefore, slightly fastermemories are generally required in most systems.Among currently available RAMs, there are two distinct categories of deviceswith different interface characteristics: RAMs without output enable controllines (OE), which include the 1-bit wide organized RAMs and most of the 4-bitwide RAMs, and those with OE controls, which include the byte-wide and a fewot"the 4-bit wide RAMs. Many of the fastest RAMs do not provide OE control;they use chip-select (CS) controlled write cycles to insure that data outputs donot turn on for write operations. In CS-controlled write cycles, the write controlline (WE) goes low before CS goes low, and internal logic holds the outputsdisabled until the cycle is completed. Using CS-controlled write cycles is an efficientway to interface fast RAMs without OE controls to the TMS320C30 atfull speed.In the case of RAMs with OE controls, the use of this signal can provide addedflexibility in many systems. Additionally, many of these devices can be inter-12-4Hardware Applications
I-'rIl7'l!l'-11 Bus Interfacefaced using CS-controlled write cycles with OE tied low, in the same manneras with RAMs without OE controls. There are, however, two requirements forinterfacing to OE RAMs in this fashion. First, the RAMs OE input must be gatedwith chip select and WE internally so that the device's outputs do not turn onunless a read is being performed. Second, the RAM must allow its address inputsto change while WE is low; some RAMs specifically prohibit this.Figure 12-3 shows the TMS320C3x interfaced to Cypress Semiconductor'sCY7C186 25-ns 8K x 8-bit CMOS static RAMs with the OE control input tiedlow and using a CS-controlled write cycle.Figure 12-3. TMS320C3x Interface to Cypress Semiconductor CY7C186 CMOS SRAM4 x CY7C186-25IPrimaryAddressBusA23-AOA23031A12 .1/07A12 030A111/06A11029A101/05A10028A91/04A9027A81/03A8026A71102A7025A61/01A6024AS1/00A5A4A4A3A3A2A2A1A1AOAO 1/08 023-016_(7-0)STRB CS1 8 015-08110CS2(7-0}RiWWE74AS048 07-00OE 1/0V (7-0)Primary Data Bus 031-00In this circuit, the two chip selects on the RAM are driven by STRB and A23,which are ANDed together internally. The use of A23 locates the RAM at addressesOOOOOh through 03FFFh in external memory, and STRB establishesthe CS-controlled write cycle. The WE control input is then driven by the12-5
t.Jrlrr'~rll Bus InterfaceFigure 12-5. Write.Operations Timing\'\"..._-11 \'\".._-11 \.\"..--~3-AO ____ -J)(~ _____________________________ )(~ ______ __CS1:;; STRB /--- \.'-___..-T!IWE:;; R/W\'~--------------:----IID31-DO -------------------ct"'"'_________;...__........t~~ __ t1 ---tl~ 1"-J t2 :.-1>>------If more complex chip-select decode is required than can be accomplished intime to meet zero-wait state timing, wait states or bank switching techniques(discussed in a later section) should be used.Note that the CY7C186's OE control is gated internally with CS; therefore, theRAM's outputs are not enabled unless the device is selected. This is critical ifthere are any other devices connected to the same bus; if there are no otherdevices connected to the bus, then OE need not be gated internally with chipselect.RAMs without OE controls can also be easily interfaced to the TMS320C3x byusing a similar approach to that used with RAMs with OE controls. If only onebank of memory is impl~mented, and no other devices are present on the bus,the memories' CS input can usually be connected to STRB directly. If severaldevices must be selected, however, a gate is generally required to AND the deviceselect and STRB to drive the CS input to generate the chip-select controlledwrite cycles. In either case, the WE input is driven by the TMS320C3xR/W signal. Provided sufficiently fast gating is used, 25-ns RAMs may still beused.As with the case of RAMs with OE control lines, this approach works well if onlya few banks of memory are implemented where the chip-select decode can beaccomplished with only one level of gating. If many banks are required to implementvery large memory spaces, bank switching can be used to provide formultiple bank select generation while still maintaining full-speed accesseswithin each bank. Bank switching is discussed in detail in a later section.12-7
IJnn1!:1r" Bus Interface12.2.2 Ready GenerationThe use of wait states can greatly increase system flexibility and reduce hardwarerequirements over systems without wait-state· capability. TheTMS320C3x has the capability of generating wait states on either the primarybus orthe expansion bus, and both buses have independent sets of ready controllogic.Thissubsection discusses ready generation from the perspective ofthe primary bus interface; however, wait-state operation on the expansion busis similarto that of the primary bus. Therefore, these discussions pertain equallywell to expansion bus operation. Accordingly, ready generation is not includedin the specific discussions of the expansion bus interface.Wait states are generated on the basis ofQthe internal wait-state generator,Q the external ready input (ROY), orQthe logical AND or OR of the two.When enabled, internally generated wait states effect all external cycles, regardlessof the address accessed. If different numbers of wait states are requiredfor various external devices, the external ROY input may be used to tailorwait-state generation to specific system requirements.If the logical AND (electrical OR) of the wait count and external ready signalsis selected, the later of the two signals will control the internal ready signal, andboth signals must occur. Accordingly, external ready control must be implementedfor each wait-state device, and the wait count ready signal must be enabled.If the logical OR (or electrical AND, since the signals are low true) of the externaland internal wait-coLint ready signals is selected, the earlier of the two signalswill generate a ready condition and allow the cycle to be completed. It isnot required that both signals be present.ORing of the Ready SignalsThe OR of the two ready signals can be used to implement wait states for devicesthat require a greater number of wait states than are implemented withexternal logic (up to seven). This feature is useful, for example, if a system containssome fast and some slow devices. In this case, fast devices can generatea ready signal externally with a minimum of logic, and slow devices can usethe internal wait counter for larger numbers of wait states. Thus, when fast devicesare accessed, the external hardware responds promptly with a ready signalthat terminates the cycle. When slow devices are accessed, the externalhardware does not respond, and the cycle is appropriately terminated after theinternal wait count.The OR of the two ready signals may also be used if conditions occur that requiretermination of bus cycles prior to the number of wait states implemented12-8Hardware Applications
I-lrIlTl!:ll-U Bus Interfacewith external logic. In this case, a shorter wait count is specified internally thanthe number of wait states implemented with the external ready logic, and thebus cycle is terminated after the wait' count. This feature may also be used asa safeguard against inadvertent accesses to nonexistent memory that wouldnever respond with ready and would therefore lock up the TMS320C3x.If the OR of the two ready signals is used, however, and the internal wait-statecount is less than the number of wait states implemented externally, the externalready generation logic must have the ability to reset its sequencing to allowa new cycle to begin immediately following the end of the internal wait count.This requires that, under these conditions, consecutive cycles must be fromindependently decoded areas of memory and that the external ready generationlogic be capable of restarting its sequence as soon as a new cycle begins.Otherwise, the external ready generation logic may lose synchronization withbus cycles and therefore generate improperly timed wait states.ANDing of the Ready SignalsThe AND of the two ready signals can be used to implement wait states for devicesthat are equipped to provide a ready signal but cannot respond quicklyenough to meet the TMS320C3x's timing requirements. In particular, if thesedevices normally indicate a ready condition and, when accessed, respond witha wait until they become ready, the logical AND of the two ready signals canbe used to save hardware in the system. In this case, the internal wait countercan provide wait states initially and becomes ready after the external devicehas had time to send a not ready indication. The internal wait counter then remainsready until the external device also becomes ready, which terminatesthe cycle.Additionally, the AND of the two ready signals may be used for extending thenumber of wait states for devices that already have external ready logic implementedbut require additional wait states under certain unique circumstances.External Ready GenerationIn the implementation of external ready generation hardware, the particulartechnique employed depends heavily on the specific characteristics of the system.The optimum approach to ready generation varies, depending on the relativenumber of wait-state and non-wait-state devices in the system and on themaximum number of wait states required for anyone device. The approachesdiscussed here are intended to be general enough for most applications andare easily modifiable to comprehend many different system configurations.In general, ready generation involves the following three functions:1) Segmentation of the address space in some fashion to distinguish fast andslow devices.12-9
Primary Bus Interface2) Generating properly timed ready indications.3) LogicallyORing all of the separate ready timing signals togetherto connectto the physical ready input.Segmentation of the address space is required to obtain a unique indicationof each particular area within the address spacethat requires wait states. Thissegmentation is commonly implemented in a system in the form of chip-selectgeneration. Chip-select signals may be used to initiate wait states in manycases; however, occasionally, chip-select decoding considerations may providesignals that will not allow ready input timing requirements to be met. In thiscase, coarse address space segmentation may be made on the basis of asmall number of address lines, where simpler gating allows signals to be generatedmore quickly. In either case, the signal indicating that a particular areaof memory is being addressed is normally used to initiate a ready or wait-stateindication.Once the region of address space being accessed has been established, a timingcircuit of some sort is normally used to provide a ready indication to the processorat the appropriate point inthe cycle to satisfy each device's unique requirements.Finally, since indications of ready status from multiple devices are typicallypresent, the signals are logically ORed by using a single gate to drive the RDYinput.Ready Control LogicOne of two basic approaches can be taken in the implementation of ready controllogic, depending upon the state of the ready input between accesses. IfRDY is low between accesses, the processor is always ready unless a waitstate is required; if RDY is high between accesses, the processor will alwaysenter a wait state unless a ready indication is generated.If ROY is low between accesses, control of full-speed devices is straightfor,ward; no action is necessary because ready is always active unless otherwiserequired. Devices requiring wait states, however, must drive ready high fastenough to meet the input timing requirements. Then, after an appropriatedelay, a ready indication must be generated. This can be quite difficult in manycircumstances because wait-state devices are inherently slow and often requirecomplex select decoding.If ROY is high between accesses, zero wait-state devices, which tend to be inherentlyfast, can usually respond immediately with a ready indication. Waitstatedevices may simply delay their select signals appropriately to generatea ready. Typically, this approach results in the most efficient implementationof ready control logic. Figure 12-6 shows a circuit of this type, which can beused to generate 0, 1, or 2 wait states for multiple devices in a system.12-10Hardware Applications
IJrll'TI!:lj-1/ Bus InterfaceFigure 12-6. Circuit for Generation of 0, 1, or 2 Wait States for Multiple Devices2 WaitStatusDevices74ALS138TMS320C30 { AAddress BBusCSTRB ----I G2AXJ---IJ PREQ74ACT112K CIRG1Other 1Wait StatusDevicesA ..--_....JDeviceSelects74AS32+5 VOther 0Wait-StateDevicesA4.7 knH1 ----~~----~----------------------~RESET------------~--------------------------....JExample CircuitIn this circuit, full-speed devices drive ready directly through the '74AS21, andthe two flip-flops delay wait-state devices' select signals one or two H1 cyclesto provide 1 or 2 wait states.Considering the TMS320C3x-33's ready delay time of 8 ns following address,zero wait-state devices must use ungated address lines directly to drive the inputof the '74AS21, since this gate contributes a maximum propagation delayof 6 ns to the ROY signal. Thus, zero wait-state devices should be grouped togetherwithin a coarse segmentation of address space if other devices in thesystem require wait states.With this circuit, devices requiring wait states may take up to 36 ns from a validaddress on the TMS320C3x to provide inputs to the '74AS20's inputs. Typically,this allows sufficient time for any decoding required in generating select signalsfor slower devices in the system. For example, the 74ALS138, driven byaddress and STRB, can generate select decodes in 22 ns, which easily meetsthe TMS320C3x-33's timing requirements.12-11
IJYin"!:lYI/ Bus InterfaceWith this circuit, unused inputs to eitherthe 74AS20s orthe 74AS21 should betied to a logic high level to prevent noise from generating spurious wait states.If more than 2 wait states are required by devices within a system, other approachesmay be employed for ready generation. If between three and sevenwait states are required, additional flip-flops may be included in the same mannershown in Figure 12-6, or internally generated wait states may be used inconjunction with external hardware. If more than seven wait states are required,an external circuit using a counter may be used to supplement the capabilitiesof the internal wait-state generators.12.2.3 Bank Switching TechniquesThe TMS320C3x's programmable bank switching feature can greatly easesystem design when large amounts of memory are required. Because, in general,devices take longer to release the bus than they take to drive the bus,bank switching is used to provide a period of time for disabling all device selectsthat would not normally bR present otherwise (refer to Section 7.4 for furtherinformation regarding bank switching). During this interval, slow devices areallowed time to turn off before other devices have the opportunity to drive thedata bus, thus avoiding bus contention.When bank switching is enabled, any time a portion of the high order addresslines changes, as defined by the contents of the BNKCMPR register, STRBgoes high for one full H1 cycle. Provided STRB is included in chip-select decodes,this causes all devices to be disabled during this period. The next bankof devices is not enabled until STRB goes low again.In general, bank switching is not required during writes, because these cyclesalways exhibit an inherent one-half H 1 cycle setup of address information beforeSTRB goes low. Thus, when you use bank switching for read/write devices,a minimum of half of one H1 cycle of address setup is provided for allaccesses. Therefore, large amounts of memory can be implemented withoutwait states or extra hardware required for isolation between banks. <strong>Al</strong>so, notethat access time for cycles during bank switching is the same as that of cycleswithout bank switching, and, accordingly, full-speed accesses may still be accomplishedwithin each bank.When you use bank switching to implement large multiple-bank memory systems,an important consideration is address line fanout. Besides parametricspecifications for which account must be made, AC characteristics are alsocrucial in memory system design. With large memory arrays, which co"mmonlyrequire large numbers of address line inputs to be driven in parallel, capacitiveloading of address outputs is often quite large. Because all TMS320C3x timingspecifications are guaranteed up to a capacitive load of 80 pF, driving greaterloads will invalidate guaranteed AC characteristics. Therefore, it is often necessaryto provide buffering for address lines when driving large memory ar-12-12Hardware Applications
#Jr"T1~"IJ' Bus InterfaceFigure 12~7.2rays. AC timings for buffer performance. may then be derated according tomanufacturer specifications to accommodate a wide variety of memory arraysizes.The circuit shown in Figure 12-7 illustrates the use of bank switching with CypressSemiconductor's 'CY7C185 25-ns 8K x 8 CMOS static RAM. This circuitimplements 32K 32-bit words of memory with one wait-state accesses withineach bank.Bank Switching for Cypress Semiconductor's CY7C185_r----------------------------------------,+ 1r V + 1r v + 1r V + 1r VBA12BA12BA12BA12A12VCCA12VCCA12VCCA12VCCBA11BA11BA11BA11A11A11A11A11BA10 BA10 BA10BA10A10A10A10'A10BAgDO ----.. BAgDO ---.. BAgDO BAgDO t-------A9A9A9A9BA8D1 ----.. BA8D1 ---.. BA8 D1 BA8 D1 !--------.A8 A8 A8 ------ A8BA7 ID2 ----.. BA7 D2 ---.. BA7 D2 ----.. BA7 D2 !--------.A7A7A7A7BA6D3 ----.. BA6D3 ---.. BA6D3 r------. BA6D3A6A6A6A6BA504 ----.. BA504 ---.. BA504 :----" BA504A5A5A5A5BA405 ----.. BA405 ---.. BA405 '---------- BA405A4A4A4A4 ------BA306 ----.. BA306 ---.. BA306 ----.. BA306A3A3A3A3BA207 ----.. BA207 ---.. BA207 '---------- BA2D7A2A2A2A2 ------BA1BA1BA1BA1A1A1A1A1BAOBAOBADBADAO 8 AO 8 AD 8 AO 8BANKSELOBSTRBBR;WBANKSEL1BANKSEL2BANKSEL3BANKSELBANKSELBANKSELBANKSELCS1CS1CS1CS1B~ CS2B~ CS2B~ CS2B~ CS2r- WE r- WE r- WE r- WEOE OE OE OEr GNO r GNO r GNO r GNOV V V VIII L _________ Bank 0---------- --------------------- JBank 1Bank 2rBank3r32rOata Bus 031-DO031-00A wait state is required with this implementation of bank memory because ofthe added propagation delay presented by the address bus buffers used in thecircuit. The wait state is not a function of the memory organization of multiplebanks or the use of bank switching. When bank switching is used, memory accessspeeds are the same as without bank switching, once bank boundariesare crossed. Therefore, no speed penalty is paid when bank switching is used,except for the occasional extra cycle inserted when bank boundaries arecrossed. Note, however, that if the extra cycle inserted when bank boundaries12-13
IJYlrt,!:!y" Bus Interfaceare crossed does impact software performance significantly, code can oftenbe restructured to minimize bank boundary crossings, thereby reducing the effectof these boundary crossings on software performance.The wait state forthis bank memory is generated by using the wait-state generatorcircuit presented in the previous section. Because A23 is the signal whichenables the entire bank memory system, the inverted version of this signal isANDed with STRS to derive a one wait-state device select. This signal is thenconnected in the circuit along with the other one-wait-state device selects.Thus, any time a bank memory access is made, one wait state is generated.Each of the four banks in this circuit is selected by using a decode of A 15-A 13generated by the 74AS138 (see Figure 12-8). With the BNKCMPR registerset to OSh, the banks will be selected on even 8K-word boundaries starting atlocation 080AOOOh in external memory space.12-14Hardware Applications
Primary Bus InterfaceFigure 12-8. Bank Memory Control Logic74ALS2541AOAiA2A3A4A5A6A?A1A2A3A4A5A6A7ABG1Y1Y2Y3Y4Y5Y6Y7YBG2BAaBA1BA2BA3BA4BA5BA6BA?74ALS2541ASA9A10A11A12R/WA1A2A3A4A5A6A7ABG1Y1Y2Y3Y4. Y5Y6Y7YBG2BASBA9BA10BA11BA12BR/W74AS13BA15 C Y1A14 B Y2A13 A Y3Y4Y5Y6A23 G1 Y7G2A YBG2B74AS04STRS -(:>0-BSTRBThe 74ALS2541 buffers used on the address lines are necessary in this designbecause the total capacitive load presented to each address line is a maximumof 20 x 5 pF or 100 pF (bank memory plus zero wait-state static RAM), whichexceeds the TMS320C3x rated capacitive loading of 80 pF. Using the manufacturersderating curves for these devices at a load of 80 pF (the load presentedby the bank memory) predicts propagation delays at the output of the12-15
JJrll'l'"l
W"""""""u Bus InterfaceFigure 12-9. Timing for Read Operations Using Bank Switching--., t1 j4- ~ t4~H1~ I I ~IIA23-A13X ;ValidIIIIII \ rA12-AOX valid; XIISTRB Ii---.11'14-~I~IBANKSELOBANKSEL1III~ t3 kI-II--.I t5 j4-Ij~tD31-DO Bank 0 on Bus ) ~ 6 Bank 1 on BusThis timing is summarized in Table 12-1.Table 12-1. Bank Switching Interface TimingTimeTimetIntervalEventPeriodt1 H1 falling to address vaiid/STRB rising 14 nst2 Address valid to select delay 10 nst3 Memory disable from STRB 10 nst4 H1 falling to STRB 10 nst5 STRB to select delay 4.5 nst6 Memory output enable delay 3 nst Timing for the TMS320C3x-33.12-17
F}(rl::ln(~i()n Bus Interface12.3 Expansion Bus InterfaceThe TMS320C30's expansion bus interface provides a second complete parallelbus, which can be used to implement data transfers concurrently with, andindependent of, operations on the primary bus. The expansion bus comprisestwo mutually exclusive interfaces controlled by the MSTRB and 10STRB signals,respectively. This subsection discusses interface to the expansion bususing 10STRB cycles; MSTRB cycles are essentially equivalent in timing to primarybus cycles and are discussed in Section 12.2. This section applies toTMS320C30 devices.Unlike the primary bus, both read and write cycles on the I/O portion of the expansionbus are two H1 cycles in duration and exhibit the same timing. TheXR/W signal is high for reads and low for writes. Since I/O accesses take twocycles, many peripherals that require wait states if interfaced either to the primarybus or by using MSTRB, may be used in a system without the need forwait states. Specifically, in cases where there is only one device on the expansionbus, devices with address access times greater than the 30 ns requiredby the primary bus, but less than 59 ns, can be interfaced to the I/O bus of theTMS320C30-33 without wait states.A/D Converter InterfaceA/D and D/A converters are components that are commonly required in DSPsystems and interface efficiently to the I/O expansion bus. These devices areavailable in many speed ranges and with a variety offeatures. While some mayrequire one or more wait states on the I/O bus, others may be used at fullspeed.Figure 12-10 illustrates a TMS320C30 interface to an Analog DevicesAD1678 analog-to-digital converter. The AD1678 is a 12-bit, 5-~s converterthat allows sample rates up to 200 kHz and has an input voltage range of 10volts bipolar or unipolar. The converter is connected according to manufacturer'sspecifications to provide 0- to + 1 O-volt operation .. This interface illustratesa common approach to connecting devices such as this to the TMS320C30.Note that the interface requires only a minimum amount of control logic.12-18Hardware Applications
~Expansion Bus InterfaceFigure 12-10. Interface to AD 1678 AID Converter-1--OSTRBXR/W -Y. 74AS04~XA12U74AS32~)XDO 18x D Bus. XD1 16XD2 14XD3 12XD4 9XD5 7XD6 5XD7 3XD8 18XD9 16XD10 14XD11 12XA12 -~] JlOW-74AS32~I lOR-1Y12Y174LS2441G2G1A12A1246811131517~1 I- ,.--74LS2441Y1 1A1 ~~681(3I-.1.L ONEr--+12 V +5 V_vccOEscCS12/8ONEL SYNCEOCENDOD1D2D3D4D5D6D7D8D9D10D11PGNDVDDREFOUTAD1678REFINBIPOFFAINEOCVEE AGNDJ I ~-12 V-I-:-:~ 50 n~ 20KnI NTOAnalogInputThe AD1678 is a very flexible converter and is configurable in a number of differentoperating modes. These operating modes include byte orword data format,continuous or noncontinuous conversions, enabled or disabled chip-selectfunction, and programmable end of conversion indication. This interfaceutilizes 12-bit word data format, rather than byte format to be compatible withthe TMS320C3x. Noncontinuous conversions are selected so that variablesample rates may be used because continuous conversions occur only at arate of 200 kHz. With noncontinuous conversions, the host processor determinesthe conversion rate by initiating conversions through write operationsto the converter.12-19
J-)([}Rn.'~Jnn Bus InterfaceThe chip-select function is enabled, so the chip-select input is required to beactive when accessing the device. Enabling the chip select function is necessaryto allow 'a mechanism for the AD1678 to be isolated from other peripheraldevices connected to the expansion bus. To establish the desired operatingmodes, the SYNC and 12/8 inputs to the converter are pulled high and EOCENis grounded, as specified in the AD1678 data sheet.In this application, the converter's chip select is driven by XA 12, which mapsthis device at 804000h in I/O address space. Conversions are initiated by writingany data value to the device, and the conversion 'results are obtained byreading from the device after the conversion is completed. To generate the device'sstart conversion (SC) and output enable (OE) inputs, 10STRB is ANDedwith XR/W. Therefore, the converter is selected whenever XA 12 is low; OE isdriven when reads are performed, while SC is driven when writes are performed.As with many AID converters, atthe end of a read cycle the AD1678 data outputlines enter a high-impedance state. This occurs after the output enable (OE)or read control line goes inactive. <strong>Al</strong>so common with these types of devices isthat the data output buffers often require a substantial amount of time to actuallyattain a full high-impedance state. When used with the TMS320C30-33, devicesmust have their outputs fully disabled no later than 65 ns following therising edge of 10STRB because the TMS320C30 will begin driving the data busat this point if the next cycle is a write. If this timing is not met, bus conflicts betweenthe TMS320C30 and the AD1678 may occur, potentially causing degradedsystem performance and even failure due to damaged data bus drivers.The actual disable time forthe AD1678 can be as long as 80 ns; therefore,buffers are required to isolate the converter outputs from the TMS320C30. Thebuffers used here are 74LS244s that are enabled when the AD1678 is read andturned off 30.8 ns following 10STRB going high. Therefore, theTMS320C30-33 requirement of 65 ns is met.When data is read following a conversion, the AD1678 takes 100 ns after itsOE control line is asserted to provide valid data at its outputs. Thus, includingthe propagation delay of the 74LS244 buffers, the total access time for readingthe converter is 118 ns. This requires two wait states on the TMS320C30-33expansion 1/0 bus.The two wait states required in this case are implemented using software waitstates; however, depending on the overall system configuration, it may be necessarytoimplement a separate wait-state generatorforthe expansion bus (referto section on ready generation). This would be the case if there were multipledevices that required different numbers of wait states connected to the expansionbus.Figure 12-11 shows the timing for read operations between theTMS320C30-33 and the AD1678. At the beginning of the cycle, the addressand XR/W lines become valid t1 = 10 ns following the falling edge of H1. Then,12-20Hardware Applications
Ex[.)am,ion Bus Interfaceafter t2 = 10 ns from the next rising edge of H1, IOSTRB goes low, beginningthe active portion of the read cycle. After t3 = 5.8 ns, the control logic propagationdelay, the lOR signal goes low, asserting the OE input to the AD1678. The'74LS244 buffers take t4 = 30 ns to enable their outputs, and then, followingthe converters access delay and the buffer propagation delay (t5 = 100 + 18= 118 ns), data is provided to the TMS320C30. This provides approximately46 ns of data setup before the rising edge of 10STRB. Therefore, this designeasily satisfies the TMS320C30-33's requiremenfof 15 ns of data setup timefor reads.Figure 12-11.Read Operations Timing Between the TMS320C30 and AD1678XA12-XAOH1 ~ {lOR',,-__ I',,-__ I , I~~:---------------~I4-*-t ~ t21 I~~--------------------------~I~t3I~--~ __________________________________ I'-R~A&~----------1i~~~~~~~~~~~~::::::::::::::~~~t4 Ij4 t5 ~Unlike the primary bus, read and write cycles on the 1/0 expansion bus aretimed the same with the exception that XRIW is high for reads and low for writesand that the data bus is driven by the TMS320C30 during writes. When writingto the AD1678, the '74LS244 buffers do not turn on and no data is transferred.The purpose of writing to the converter is only to generate a pulse on the converter'sSC input, which initiates a conversion cycle. When a conversion cycleis completed, the AD1678's EOC output is used to generate an interrupt on theTMS320C30 to indicate that the converted data may be read.It should be noted that for different applications, use of TLC 1225 or TLC 1550AID converters from Texas Instruments may be beneficial. The TLC1225 is aself-calibrating 12-bit-plus-sign bipolar or unipolar converter, which features1 0-IlS conversion times. The TLC1550 is a 10-bit, 6-lls converter with a highspeedDSP interface. Both converters are parallel-interface devices.01 A Converter InterfaceIn many DSP systems, the requirement for generating an analog output signalis a natural consequence of sampling an analog waveform with an AID converterand then processing the signal digitally internally. Interfacing D/A convertersto the TMS320C30 on the expansion I/O bus is also quite straightforward.12-21
Expansion Bus InterfaceAs with AID converters, D/A converters are also available in a number of varieties.One of the major distinctions between various types of D/A convertersis whether or not the converter includes both latches to store the digital valueto be converted to an analog quantity, and the interface to control those latches.With latches and control logic included with the converter, interface design isoften simplified; however, internal latches are often included only in slower D/Aconverters.Because slower converters limit signal bandwidths, the converter used in thisdesign was selected to allow a reasonably wide range of signal frequenciesto be processed, and to illustrate the technique of interfacing to a converter thatuses external data latches.Figure 12-12 shows an interface to an Analog Devices AD565A digital-to-analogconverter. This device is a 12-bit, 250-ns current output DAC with an onchip10-volt reference. Using an offchip current-to-voltage conversion circuitconnected according to manufacturers specifications, the converter exhibitsoutput signal ranges of 0 to + 10 volts, which is compatible with the conversionrange of the AID converter discussed in the previous section.12-22Hardware Applications
Expansion Bus Interface;:::;:;:;:::;:;:;s:'::;:::::;:::;::O';:'::':~::':::::::::::::::::::::::::::::::::::::::::;!:::;:;:::::::::::;::-'::::::::::::'::::::::::::::::::::::::::::::::;:;..:.::::;:::::::::x::::::!:::*~:::;:;*;::::::*::::~::;:::::::::;o.::::::::::;:;:::;:;..: :::::::;:::::.::::::~:::;:;~:::~::;·:*;:::;.::;...:::~::.:::.:::::;,.&u;,:::::0';-»'::::::.::::::::::::::::;::.';:::::::.:.:::::.::0';':.';::0.Y;:':::::;~:::':;:::':;:'W;,,,::b:':::::;'Y,;:.:;:-y~.·::::o!o·.,,:,·u..:..-=.y.:.:;:.:::.:.:.::::::y'::;:;:.:::;:«.::O'::::::.:.:::.::::::::::::::o;::::::::::::::::.:.:::::::::;:::::::::Figure 12-12. Interface Between the TMS320C30 and the AD565AXD BusXDO 3XD1 4XD2 7XD3 8XD4 13XD5 14XD6 17XD7 18,--XD8 3XD9 4XD10 7XD11 8.-lOW74lS3771D 10U2550Q :=256912151619+12VIVCCREF. OUT- REF. IN*REF.AGNDGNDBit 12 (lSB)111098765VEE20 V SPANAD565A10VSPANDACOUTClK EN r-- 4- 3- 2- Bit 1 (MSB)74lS377Power2 GND5ClKU2669EN~L~ 2.4KV-12 VOutBecause this DAC essentially performs continuous conversions based on thedigital value provided at its inputs, periodic sampling is maintained by periodicallyupdating the value stored in the external latches. Therefore, betweensample updates, the digital value is stored and maintained at the latch outputsthat provide the input to the DAC. This results in the analog output remainingstable until the next sample update is performed.The external data latches used in this interface are '74LS377 devices that haveboth clock and enable inputs. These latches serve as a convenient interfacewith the TMS320C30; the enable inputs provide a device select function, andthe clock inputs latch the data. Therefore, with the enable input driven by invertedXA 12 and the clock input by lOW, which is the AND of 10STRB andXR/W, data will be stored in the latches when a write is performed to I/O address805000h. Reading this address has no effect on the circuit.12-23
EXf../am;ion Bus InterfaceFigure 12-13 shows a timing diagram of a write operation to the D/A converterlatches.Figure 12-13. Write Operation to the DIA Converter Timing DiagramBecause the write is actually being performed to the latches, the key timingsfor this operation are the timing requirements for these devices. For proper operation,these latches require simply a minimal setup and hold time of data andcontrol signals with respect to the rising edge of the clock input. Specifically,the latches require a data setup time of 20 ns, enable setup of 25 ns, disablesetup of 10 ns, and data and enable hold tim~s of 5 ns. This design providesapproximately 60 ns of enable setup, 30 ns of data setup, and 7.2 ns of datahold time. Therefore, the setup and hold times provided by this design are wellin excess of those required by the latches. The key timing parameters for thisinterface are summarized in Table 12-2.Table 12-2. Key Timing Parameter for DIA Converter Write OperationtTimeTimetIntervalEventPeriodt1 H1 falling to address valid 10 nst2 XA12 to XA12 delay 5 nst3 H1 rising to IOSTRB falling 10 nst4 IOSTRB to lOW delay 5.8 nst5 Data setup to lOW 30 nst6 Data hold from lOW 7.2 nsTiming for the TMS320C30-33.12-24 Hardware Applications
Control Function12.4 System Control Functions12.4.1 Clock Oscillator CircuitryFigure 12-14. Crystal Oscillator CircuitSeveral aspects of TMS320C3x system hardware design are critical to overallsystem operation. These include such functions as clock and reset signal generationand interrupt control.You may provide an input clock to the TMS320C3x either from an externalclock input or by using the onboard oscillator. Unless special clock requirementsexist, the onboard oscillator is generally a convenient method for clockgeneration. This method requires few external components and can providestable, reliable clock generation for the device.Figure 12-14 shows the external clock generator circuit designed to operateat 33.33 MHz and to use the internal oscillator circuitry of the TMS320C3x.Since crystals with fundamental oscillation frequencies of 30 MHz and aboveare not readily available, a parallel-resonant third-overtone circuit is used.TMS320C3x-3347pF TX1X2/CLKIN33,33 MHz01----0---T T::~:: 20pFIn a third-overtone oscillator, the crystal fundamental frequency must be attenuatedso'that oscillation is at the third harmonic. This is achieved with an LCcircuit that filters out the fundamental, thus allowing oscillation at the third harmonic.The impedance of the LC circuit must be inductive at the crystal fundamentaland capacitive at the third harmonic. The impedance of the LC circuitis represented by'cz(w) = ,[ 1 ]J W L- wCL(3)Therefore, the LC circuit has a pole at1=!lE(4)12-25
.;,vsrem Control FunctionAt frequencies significantly lower than oop' the 1/(ooC) term in (3) becomes thedominating term, while ooL can be neglected. This is expressed asz(oo) = jcoL for co < cop , (5)In (5), the LC circuit appears inductive at frequencies lower than oop. On theother hand, at frequencies much higher than cop, the ooL term is the dominantterm in (3), and 1/(ooC) can be neglected. This is expressed as1z(oo) = jooC for 00 > oop (6)The LC circuit in (6) appears increasingly capacitive as the frequencyincreases above oop. This is shown in Figure 12-15, which is a plot of the magnitudeof the impedance of the LC circuit of Figure 12-14 versus frequency.Figure 12-15. Magnitude of the Impedance of the Oscillator LC NetworkI z(ro} ICapacitiveRegionro(rad/s)12-26Hardware Applications
System Control Function::::"..#.«::::"...:w/.~.m~;.~::::::::;:..-...:::::;:>:::::;:;:::;:~:::~;m:*-:::::::-;::::;,,~;:;:,.:".::::: ::'~:::'.!:;".:;:::;:;::::::::::::X:;:>::::-»':::-;:::::::::::::::::::::::::::::;:;:;-;-'::':::::-;:::;' .. ~: :::;';:::::::::::::;:::::>:::;:::::::::::::::::::;:::::;:::'.::~»'::::;::::::::::::-z .:::::-;:::~~::::::::::::::::::-.:..:::::::~:::::::~o!::::~:;:::;o.::::::::::::::::::~:::;::::::::::::::Y.«::::::::::::::::;;:::::::::::-':::::::::::':::::::::::::::::'.::-'::::;:::::;::::::::-'::::;::-'::::::::::::::;O;-;:;:;:;:::::::::::'.$:::::::::::::;:;:;eBased on the discussion above, the design of the LC circuit proceeds as follows:1) Choose the pole frequency cop approximately halfway between the crystalfundamental and the third harmonic.2) The circuit now appears inductive at the fundamental frequency and capacitiveat the third harmonic.In the oscillator of Figure 12-13, choose cop = 22.2 MHz, which is approximatelyhalfway between the fundamental and the third harmonic. ChooseC = 20 pF. Then, using equation (4), L = 2.6 jlH.12.4.2 Res~t Signal GenerationThe reset input controls initialization of internal TMS320C3x logic and alsocauses execution of the system initialization software. For proper system initialization,the reset signal must be applied at least ten H1 cycles, i.e., 600 nsfor a TMS320C3x operating at 33.33 MHz. Upon powerup, however, it can take20 ms or more before the system oscillator reaches a stable operating state.Therefore, the powerup reset circuit should generate a low pulse on the resetline for 1 00 to 200 ms. Once a proper reset pulse has been applied, the processorfetches the reset vector from location zero, which contains the address ofthe system initialization routine. Figure 12-16 shows a circuit that will generatean appropriate powerup reset circuit.Figure 12-16. Reset CircuitTMS320C3x+5VDGND12-27
System Control FunctionFigure 12-17. Voltage on the TMS320C30 Reset PinThe voltage on the reset pin (RESET) is controlled by the R1 C1 network. Aftera reset, this voltage rises exponentially according to the time constant R1 C1,as shown in Figure 12-17.VoltageVee_________ ~_---......a:.-V = Vee (1 - e -tIt)limeThe duration of the low pulse on the reset pin is approximately t1, which is thetime it takes for the capacitor C1 to be charged to 1.5 V. This is approximatelythe voltage at which the reset input switches from a logic 0 to a logic 1. The capacitorvoltage is expressed asv = Vcc[ 1-e-;](7)where't = R1 C1 is the reset circuit time constant. Solving equation (7) for t resultsinSetting the following:R1 = 100 KnC1 =4.7~FVee = 5. VV = V 1 = 1.5 Vresults in t = 167 ms. Therefore, the reset circuit of Figure 12-16 provides alow pulse of long enough duration to ensure the stabilization of the system os. cillator.(8)12-28Hardware Applications
System Control FunctionNote that if synchronization of multiple TMS320C3xs is required, all processorsshould be provided with the same input clock and the same reset signal.After powerup, when the clock has stabilized, all processors may then be synchronizedby generating a falling edge on the common reset signal. Becauseit is the falling edge of reset that establishes synchronization, reset must behigh for at least ten H1 cycles initially. Following the falling edge, reset shouldremain low for at least ten H1 cycles and then be driven high. This sequencingof reset may be accomplished using additional circuitry based on either RCtime delays or counters.12-29
Serial Port Interface12.5 Serial Port InterfaceFor applications such as modems, speech, control, instrumentation, and analoginterface for DSPs, a complete analog-to-digital (A/D) and digital-to-analog(D/A) inpuVoutput system on a single chip may be desired. The TLC32044analog interface circuit (AIC) integrates a bandpass, switched-capacitor, anti-. aliasing-input filter, 14-bit resolution A/D and D/A converters, and a lowpass,switched-capacitor, output-reconstruction filter, all on a single monolithic/CMOS chip. The TLC32044 offers numerous combinations of master clock inputfrequencies and conversion/sampling rates, which can be changed via digitalsignal processor control.Four serial port modes on the TLC32044 allow direct interface to TMS320C3xprocessors. When the transmit and receive sections of the AIC are operatingsynchronously, it can interface to two SN54299 or SN74299 serial-ta-parallelshift registers. These shift registers can then interface in parallel to theTMS320C30, to otherTMS320 digital processors, orto external FIFO circuitry.Output data pulses inform the processor that data transmission is complete orallow the DSP to differentiate between two transmitted bytes. A flexible contralscheme is provided so that the functions of the AIC can be selected and adjustedcoincidentally with signal processing via software control. Refer to theTLC32044 data sheet for detailed information.When you interface the AIC to the TMS320C3x via one of the serial ports, noadditional logic is required. This interface is shown in Figure 12-18. The serialdata, control, and clock signals connect directly between the two devices, andthe AIC's master clock input is driven from TClKO, one of the TMS320C3x'sinternal timer outputs. The AIC's WORD/BYTE input is pulled high, selecting16-bit serial port transfers to optimize serial port data transfer rate. TheTMS320C3x's XFO pin, configured as an output, is connected to the AIC's reset(RST) inputto allow the AIC to be reset by the TMS320C3x under program control.This allows the TMS320C3x timer and serial port to be initialized beforebeginning conversions on the AIC.12-30Hardware Applications
Serial Port InterfaceFigure ! 2-18. AIC to TMS320C30 InterfaceTMS320C30FSXODXOFSROOROClKXOClKRO ~TClKOXFOG2TlC32044FSXOXFSRDRSHIFT ClKMSTR ClKIN+IN-OUT+OUT-VDDVCC+Vce-AGNDAGNDWOR01 BYTERSTDGNDVDGNDAD V~AG NOn1-+51-+5r--- +5AO UTI- +5Vr---'i7AGNDTo provide the master clock input for the AIC, the TCLKO timer is configuredto generate a clock signal with a 50% duty cycle at a frequency of f(H1 )/4 or4.167 MHz. To accomplish this, the global control register for timer 0 is set tothe value 3C1 h, which establishes the desired operating modes. The periodregister for timer 0 is set to 1, which sets the required division ratio for the H1clock.To properly communicate with the AIC, the TMS320C30 serial port must beconfigured appropriately. To configure the serial port, several TMS320C30registers and memory locations must be initialized. First, the serial port shouldbe reset by setting the serial port global control register to 2170300h. (The AICshould also be reset at this time. See description below of resetting the AIC viaXFO). This resets the serial port logic and configures the serial port operatingmodes, including data transfer lengths, and enables the serial port interrupts.This also configures another important aspect of serial port operation: polarityof serial port signals. Because active polarity of all serial port signals is programmable,it is critical to set appropriately the bits in the serial port global controlregister that control this. In this application, all polarities are set to positiveexcept FSX and FSR, which are driven by the AIC and are true low.The serial port transmit and receive control registers must also be initializedfor proper serial port operation. In this application, both of these registers areset to 111 h, which configures all of the serial port pins in the serial port mode,rather than the general-purpose digital 110 mode.When the operations described above completed, interrupts are enabled, andprovided that the serial port interrupt vector(s) are properly loaded, serial port12-31
Serial Port Interfacetransfers may begin after the serial port is taken out of reset. This is accomplishedby loading E170300h into the serial port global control register.To begin conversion operations on the AIC and subsequent transfers of dataon the serial port, the AIC is first reset by setting XFO to zero at the beginningof the TMS320C3x initialiiation routine. Setting XFO to zero is accomplishedby setting the TMS320C3x IOF register to 2. This sets the AIC to a default configurationand halts serial port transfers and conversion operations until resetis set high. Once the TMS320C3x serial port and timer have been initializedas described above, XFO is set high by setting the IOF register to 6. This allowsthe AIC to begin operating in its default configuration, which in this applicationis the desired mode. In this mode, all internal filtering is enabled, sample rateis set at approximately 6.4 kHz, and the transmit and receive sections of thedevice are configured to operate synchronously. Conveniently, this mode ofoperation is appropriate for a variety of applications, and if a 5.184-MHz masterclock input is used, the default configuration results in an 8-kHz sample rate,which makes this device ideal for speech and telecommunications applications.In addition to the benefit of a convenient default operating configuration, theAIC can also be programmed for a wide variety of other operating configurations.Sample rates and filter characteristics may be varied, in addition towhich, numerous connections in the device may be configured to establish differentinternal architectures, by enabling or disabling various functionalblocks.To configure the AIC in a fashion different from the default state, the devicemustfirst be sent aserial data word with the two LSBs setto one. The two LSBsof a transmitted data word are not part of the transferred data information andare not set to one during normal operation. This condition indicates that thenext serial transmission will contain secondary control information, not data.This information is then used to load various internal registers and specify internalconfiguration options. There are four different types of secondary controlwords distinguished by the state of the two LSBs of the control informationtransferred. Note that each secondary control word transferred must be precededby a data word with the two LSBs set to one.The TMS320C3x can communicate with the AIC either synchronously orasynchronously, depending on the information in the control register. The operatingsequence for synchronous communication with the TMS320C30 shownin Figure 12-19 is as follows:1) The FSX or FSR pin is brought low.2) One 16-bit word is transmitted, or one 16-bit word is received.3) The FSX or FSR pin is brought high.4) The EODX or OEDR pin emits a low-going pulse.12-32Hardware Applications
Serial Port InterfaceFigure 12-19. Synchronous Timing of TLC32044 to TMS320C3xSHIFT elKFSR, FSX~OR 015OX 015-
XDS1000Considerations12.6 XDS1000 Target Design ConsiderationsFigure 12-21. 12-Pin Header SignalsThe TMS320C3x Emulator is an Extended Development System (XDS500and XDS1 000) that uses a revolutionary technology to accomplish completeemulation via a serial scan path and has all the features necessary for fullspeedemulation. To perform realtime emulation, you must provide a 12-pinheader on the target system that is using the TMS320C3x. Refer to theTMS320C30 Emulator User's Guide and to the TMS320C30 Hewlett-Packard64776 Analysis Subsystem User's Guide for a more complete description ofthe XDS500 and XDS1000.To use the emulation connector of the XDS500, supply the signals shown inFigure 12-21 to a 12-pin header (two rows of six pins) with pin 8 cut out to providekeying. Table 12-3 describes the pins and signals present on the header.Header Dimensions:Pin-to-pin spacing: 0.100 inches (X,V) EMU1t 2 GNDPin width:0.025 inches square postPin length: 0.235 inches nominal EMUOt 3 4 GNDEMU2t 5 6 GNDPD (+5V) 7 No Pin (Key)EMU3 9 10 GNDH3 11 12 GNDTop ViewtThese signals should always be pulled up with separate 20-kQ resistors to +5 V on theTMS320C3x.Table 12-3. Signal DescriptionSignalDescriptionTMS320C30Pin NumberTMS320C30Pin NumberEMUO Emulation pin 0 F14 124EMU1 Emulation pin 1 E15 125EMU2 Emulation pin 2 F13 126EMU3 Emulation pin 3 E14 123GNDGroundH3 TMS320C3x H3 Ai 82PDPresence detect indicates that the cable is connected and the target systemis powered up. It should be tied to +5 volts in the target system.12-34 Hardware Applications
XOS1000ConsiderationsFor unbuffered signals, the distance between the TMS320C30 emulation pins(EMUO, EMU1, EMU2, EMU3, and H3) and the 12-pin header should be lessthan two inches. If that distance is more than two inches but less than six inches,the EMU3 and H3 signals should be buffered. The buffer should be noninvertingwith a worst case propagation delay of 6.0 ns. For emulation pins-toheaderdistances greater than six inches, all emulation signals should be buffered.Recall that EMUO, EMU 1, and EMU2 are inputs, and EMU3 and H3 areoutputs. The buffer should have the same characteristics as those givenabove.12-36Hardware Applications
Hewlett-Packard 64776 Analysis Subsystem Target Design Considerations;:;~:;:;:;:;:;:;:;:;:::;:;:o.:;:::;:;:;:;:;:::;:;:;:o.:~:;:;:;:::;:;:::::;:::::;:::::::;:::::::;:::;:;:;:;:::::::::::::::::::::;:::::::::;:::0.:::;:::;:::;:::::;:::;:::::::;:;:::::::::;:;:;:::.::.;:::;:.:: •• : ••••• :.: ••• :::;:;:.: •• .:.:.: •• ;:::::.:;'.:.:.:.:;:.:.:;:;:;:.:;:.:::;'..:;:.:.:.:.';:.:;:;:::.:.: •• ;:.:.:;: ••••• : ••••• :.: ••• :.:.:;:.:.:;:.:.:.:.:.: ••••• :.: ••••• : •• ;: ••• : ••• : •••• ,.:.: ........... : •••••• .:.: ••••• : ••••••• : ••••• : ••• : ••• :.:.:.:.~: ••••• : ••••••••••••• : ••••••••••••• :.~ •• :.:.:.: ••• : ••• :.:.:.~:.: ••• :.:.:.:.';:.:.:.:.:.:.:.:;y.:.:.:::;:;:::;:::::;:;:.:;:::.:;:;:.:;:::::::;:::;:::;:;:.:;:;:;:;:the rising edge of the strobe (IOSTRB, STRB, or MSTRB). <strong>Al</strong>so, the strobecan fall and rise 0 ns after the falling and rising edges of the H 1 clock,respectively. Thus, if the data was not present 0 ns after the rising edgeof the clock, the TMS320C30 would still operate correctly. The analysissubsystem, however, requires a 5-ns hold time afterth.e rising edge of H1.Q Expansion and primary read/write (XR/W, R/W). The same electrical/timing specifications stated in Chapter 13 apply to these lines.Q H1 and H3. The same electrical/timing specifications stated in Chapter 13apply to these lines.QQRESET. While the analysis subsystem does load the reset line with someminor capacitance, it does not drive the line.EMUO-EMU6. The same electrical/timing specifications stated in Chapter13 apply to these lines.Q INTO-INT3. Requirements for levels and transitions are different.• Requirements for levels on the interrupt lines:aThe tck_clk=all setup time to falling H1 should be 18.5 ns, insteadof 15 ns, to see the first edge. However, because interrupts mustbe low for a minimum of one full clock cycle, you will always seeone low cycle.• The tck_clk=bus_cycle setup time to falling H 1 should be 15 ns.• Requirements for transitions on the interrupt lines:aThe tck_clk=bus_cycle setup time to falling H1 should be 15 ns.• The tck_clk=all setup time to falling H1 should be 15 ns.QlACK. The same electrical/timing specifications stated in Chapter 13 applyto these lines.Q HOLDA. The same electrical/timing specifications stated in Chapter 13apply to these lines.QXFO, XF1, TClKO, and TClK1. Requirements for levels and transitionsare different.II Requirements for levels on the XF and TCLK lines:• The tck_clk=all setup time to falling H1 should be 18.5 ns insteadof 12 ns.• The tck_clk=bus_cycle setup time to falling H1 should be 12 ns.12-39
Hewlett-Packard 64776 Analysis Subsystem TargetDesign Considerations:,:,,;o:;o/.;:;w)';o)"'>'~~::;-»';'7.~;:~~..;~;?;v./'m:::;?~""""""d.o:'l,::-Q),7.o'!:7)'):y,r.o:~:?h'!;':::;:"XI,lY.~:rI.I:;':~;O;:";O).;=::~:Oh'!«-")'»)'.:c;./.I,~"Z"~~"':·;cl;";'~«~Q.~""';O"'''»~%,»,~»)')'»):;,»,),;so;O).;t£.~"'I,"":;O»)'';-.l.;:=
TMS320C30 and TMS320C31 Differences12.8 TMS320C30 and TMS320C31 DifferencesTable 12-4. Feature Set ComparisonThis section addresses the major memory access differences between theTMS320C31 and the TMS320C30 devices. Observance of these considerationsis critical for achieving design goal success.Table 12-4 shows these differences, which are detailed in the following subsections.'DeviceFeature TMS320C31 TMS320C30Data/program bus Primary bus: one bus composed Two buses:of a 32-bit data and a 24-bit ad- 1) Primary bus: a 32-bit data and adress bus24-bit address2) Expansion bus: a 32-bit data and a13-bit addressSerial I/O ports 1 serial port (SPa) 2 serial ports '(SPa, SP1)User program/data ROM Not available 4K wordsl16K bytesProgram boot loader User selectable Not available12.8.1 Data/Program Bus DifferencesThe TMS320C31 uses only the primary bus and reserves the memory spacethat was previously used for expansion bus operations.12.8.2 Serial Port DifferencesSerial port 1 references in Section 8.2 of the TMS320C3x User's Guide are notapplicable to the TMS320C31. The memory locations identified for the associatedcontrol registers and buffers are reserved.12.8.3 Reserved Memory LocationsTable 12-5 identifies TMS320C31 reserved memory locations in addition tothose shown in Table 3-8.12-41
TMS320C30 and TMS320C31 DifferencesTable 12-5. TMS320C31 Reserved Memory LocationsDeviceFeature TMS320C31 TMS320C30OxOOOOOo-OxOOOFFF Reservedt Microcomputer program/data ROM mode tOx800000-ox801FFF Reserved Expansion bus MSTRB spaceOx80400o-0x805FFF Reserved Expansion bus IOSTRB spaceOx808050 Reserved SP1 global-control registerOx808052-0x808056 Reserved,SP1 local-control registers, Ox808058 Reserved SP1 data-transmit bufferOx80805C Reserved SP1 receive-transmit bufferOx808060 Reserved Expansion bus control registert Applies to the MCBL and MC modes only.12.8.4 Effects on the IF and IE Interrupt RegistersThe bits associated with serial port 1 in the IE (interrupt enable) register andthe IF (interrupt flag) register for the TMS320C30 are not applicable to theTMS320C31. Write only logic 0 data to IE register bits 6, 7, 22, and 23 and toIF register bits 6 and 7. Writing logic 1 s to these bits produces unpredictableresults.12.8.5 User Program/Data ROMThe user program/data ROM that is available for the TMS320C30 device doesnot exist for the TMS320C31. Rather, the' memory locations that were allocatedto support user program/data ROM operations have been reserved on the'TMS320C31 to support microcomputer/boot loader accessing. See Chapter3 for more information on using the microcomputer/boot loader function.12.8.6 Development ConsiderationsFor users who are developing application code using a TMS320C3x simulator,XDS, or ASM/LNK, TI recommends that you modify the .efm and .emdfiles byremoving these memory spaces from the tool's configured memory. This ensuresthat your developed application performs as expected when theTMS320C31 device is used.,'12-42Hardware Applications
TMS320C3x Signal Description and Electrical Characteristics
TMS320C3x Signal Description and Electrical" Characteristics"
Chapter 13TMS320C3x Signal Descriptions andElectrical Characteristics·;:;:;:;:;:;:;:;:;:;:;:::;:::::;:;:;:;:;:;:;:;=;:;:;:;:;:::::;:;:::;:;:;:;:;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.;.:.;.:.;.;.:.;.;.: ::;:::::::;::"';:::::::::::.:::::::::::::::::::::::;::::;.;::::::::::.:::::::::::::::::::::::::::::::::::::::; ;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:::;:;:;:;:;:;:;:.:;:;:;:;:;:;:::;:::;:;:;:::::::::::;:;:;:;:::;:;:;:;:;:::;:;:;:; ::;:;:;:;:::;:;:;:;:;:; ::::::;:;:::::::::::;:::::::;:::::.:::::;:::;:;:::::;:;:.:::::;:::;;::;:;:::::;:::::;:;:: ;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:::::::::::::::::::::::::::::::::::::::;;::::::::;::::;::::::;:::;:;:;;;:;:::::.:::::;:;:;!;:;:::;:;:;:;:;!;!;!::;:;:;:;:::;:;:;:::::::::;:;:::;:;:::;:::;:;:::;:;:::;:;:;:;:;:;:::;!;:;:;:!:;!;!:!::!;:::!;!::;!:!;:;!:!:;;!::;::;;:;!;:::::;::!::::::;:;:;:;::!;:::;:::; ;:;:;:;:;:;:::;:;:;:;:;:;:;:;:;:;:;:;:; ::::;:;:;:;!;:::;;;:;:;:.;::;:;:::;:::::::.:::;!;!;:;:::.;.:;:.;.:.!;!;::::::!;:::::::::;:;:;:;;!:;:;:;:;:;:;:::;:;:;;;:;:;:;;;:;;;:::;:;:;:!:;:;:;:;:;:;:;:;:;:;:;:;!;:;:;:;:;:;:;:::;:;:;;;:;:;:;:;:;;;;;:;:;: .;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;!;:;:::;:;!;:;:;:;:;:;:;:;!;:;:;:;:::;!;!;!;:;:;:;:;:;:;!;!;!;!;!;!::;!;:::;!;!;:;:;!:::!;!;:;;::::;!::;::!::;!:!;!!::!;!::;:!:::;:;:;!;!;::!;:;:;:;:;:::::::;:;!;'.;.;.;.;.;.;.;.;.;.;.;.;.;.;.:.;.;.;.:.:.;.:.:.:.;.;.;.:.;.:.:.:.;.:.:.:.:.;.:.:.:.:.;.:.:.;.:.;.:.:.;.;.:.;.;.;.;.:.:.;.:.;.:.:.;.!.:.;.;.;.;.;.:.;.;.;.:.!.:.:.;.;.:.;.:.:.!.;.;.;.;.: :.:.:.;.:.;.:.;.:.:.:..................................................................................................................... ..............................................................................................................................................................................................................................................................................:.;.;.:.:.:.;.:.:.:.!.;.:.;.:.:.:.:.:.;.;.;.;.; :.;.;.;.:.;.;.;.:.;.;.;.;.;.:.;;.:.;.;.:.:.:.;.;.;.:.:.;.:.:.:.;.;.:.;.:.!.:.:.:.;.:.:.:.;.;.;.;.:.:.:.:.!.:.:.;.:.; :.;.:.;.:.;.;.;.:.;.;.;.:.:.:.:.;.:.:.:.:.;.:.:.:.:.!.;.:.:.:.!.:.:.:.;.!.:.:.:.;.!.:.:.!.:.:.!.:.:.!.:.:.!.!.:.:.:.;.;.;.:.;.;.:.;.;.:.;.;.:.!.:.:.;.:.;.:.:.:.;.;.:.:.:.:.:.;.!.:.;.:.:.;.;.:.;.:.;.:.:.;.;.:.:.:.:.;.:.:.:.:.:.:.:.;.:.;.:.;.:.:.:.;.:.:.:.:.:.:.!.!.;.;.;.:.This chapter covers the TMS320C3x pinouts, signal descriptions, andelectrical characteristics.13-1
Pinout and Pin Assignments13.1 Pinout and Pin Assignments13.1.1 TMS320C30 Pinouts and Pin AssignmentsFigure 13-1. TMS320C30 Pinout (Top View)The TMS320C30 digital signal processor is available in a 181-pin grid array(PGA) package. The pinout of this package is shown in Figure 13-1 andFigure 13-2. The pin assignments are listed in Table 13-1 and Table 13-2.2 3 4 567 8 910 . 11 12 13 14 15AH3 02 03 07 010013016 017 019022 025 028 XAO X<strong>Al</strong> XA5BX2/CLKIN CVSS Hl 04 08011015 018 020024 027 031 XA4 IVSS XA6CEMU5 Xl OVSS DO 0509014 VSS 021026 030 XA3 OVSS XA7 XA10DXRm XROY VBBP OOVOO 0106012 VOO 023029 XA2 AOVoo XA9 X<strong>Al</strong>l MC/MPEROYHOLDA MSTRB VSUBSLOCATOROOVOOXA8 XA12 EMU3 EMUlFRESET STRB HOLD IOSTRBEMU4/SHZ EMU2 EMUO AOGHlACK XFO XFl RmVSS VOO MOVOOTMS320C30Top View<strong>Al</strong> A2 A3 A4AOVOO VOO VSS A6 ASJINT2 INT3 RSVO RSVl<strong>Al</strong>l A9 A8 A7KRSV2 RSV3 RSV5 RSV7A17 A14 A12 <strong>Al</strong>0LRSV4 RSV6 RSV9 CLKRlIOOVOOA22 <strong>Al</strong>B A15 A13MNpRRSV8 RSV10 FSRl POVOO CLKXO EMU6 X05 VOO X016 X022 X027 IOOVOO A21 A19 A16ORl CLKXl OVSS CLKRO TCLKl X02 X07 VSS X014 X019 X023 X028 OVSS A23 A20FSXl OXl FSRO TCLKO XOl X04 X08 X010 X013 X017 X020 X024 X029 CVss X031ORO FSXO OXO XOO X03 X06 X09 XOll X012 X015 X018 X021 X025 X026 X03013-2TMS320C3x Signal Descriptions and Electrical Characteristics
Pinout and Pin AssignmentsFigure 13-2. TMS320C30 Pinout (Bottom View)15 14 13 12 11 10 9 8 76 5 4 3 2XA5 X<strong>Al</strong> XAO 028• • • •XA6 IVss XA4 D31• • • •XA10 XA7 DVSS XA3• • • •• • •eEMUl EMU3 XA12 XA8MC/MP X<strong>Al</strong>l XA9 ADVDD XA2• • • •AO EMUO EMU2 EMU4/SHZ• • • oA4 A3 A2 <strong>Al</strong>• • • • •A7 A8 A9 <strong>Al</strong>l• • •<strong>Al</strong>0 A12 A14 A17• • • •A5 A6 Vss VDD ADVOD025 022 019 017 D16• • • • •027 024 020 D18 D15• • • • •030 026 D21 VSS D14• • • • •D29 D23 VDD D12• •DDVDD•TMS320C30Bottom View013 010 D7 D3 D2 H3• • • • • •• • • • • •D9 D5 DO DVSS Xl EMU5• • • • • •Dll D8 D4 Hl CVSS X2/CLKIN• GLOCATOR VSUBS MSTR6 HOLDAD6 D1 DDVDD VBBP XRDY XRiwRDY• • • •IOSTRB HOLD STRB RESET• • e·R/W XFl XFO lACK• • •• • • • •RSV1 RSVO INT3 INT2• • • •MDVDD VDD Vss INTO INTlRSV7 RSV5 RSV3 RSV2• • • •A13 A15 A18 A22IODVDDClKR1 RSV9 RSV6 RSV4• • • • • • • • •A16 A19 A21 IODVDD XD27 XD22 XD16 VDD XD5 EMU6 ClKXO PDVDD FSRl RSV10 RSV8• • • • • • • • • • • • • • •A20 A23 DVSS XD28 XD23 XD19 XD14 VSS XD7 XD2 TCLKl ClKRO DVSS CLKXl DRl• • • • • • • • • • • o • • •• • • • • • • • • • • • • • •• • • • • • • • • • • • • • •XD31 CVSS XD29 XD24 XD20 XD17 XD13 XD10 XD8 XD4 XDl TelKO FSRO DXl FSXlXD30 XD26 XD25 XD21 XD18 XD15 XD12 XD11 XD9 XD6 XD3 XDO DXO FSXO DROABCoEFGHJKLMNpR13-3
Pinout and PinTable 13-1. TMS320C30 Pin Assignments(by Function) (Figure 13-1 and Figure 13-2)Function Pin Function Pin Function Pin Function Pin Function PinAO F15 00 C4 FSRO P3 XAO A13 XOO R4Ai G12 01 05 FSXO R2 XA1 A14 X01 P5A2 G13 02 A2 CLKRO N4 XA2 011 X02 N6A3 G14 03 A3 ClKXO M5 XA3 C12 X03 R5A4 G15 04 B4 ORO R1 XA4 B13 X04 P6A5 H15 05 C5 OXO R3 XA5 A15 X05 M7A6 H14 06 06 FSR1 M3 XA6 B15 X06 R6A7 J15 07 A4 FSX1 Pi XA7 C14 X07 N7AS J14 OS B5 CLKR1 l4 XAS E12 XOS P7A9 J13 09 C6 ClKX1 N2 XA9 013 X09 R7A10 K15 010 A5 OR1 N1 XA10 C15 X010 PSA11 J12 011 B6 OX1 P2 XA11 014 X011 RSA12 K14 012 07 XA12 E13 X012 R9A13 l15 013 A6 EMUO F14 RSVO J3 X013 P9A14 K13 014 C7 EMU1 E15 RSV1 J4 X014 N9A15 l14 015 B7 EMU2 F13 RSV2 K1 X015 RiOA16 M15 016 A7 EMU3 E14 RSV3 K2 X016 M9A17 K12 017 AS EMU4/SHZ F12 RSV4 L1 X017 P10A18 L13 018 B8 EMU5 C1 RSV5 K3 X018 R11A19 M14 019 A9 EMU6 M6 RSV6 L2 X019 N10A20 N15 020 B9 Hi B3 RSV7 K4 X020 P11A21 M13 021 C9 H3 Ai RSVS M1 X021 R12A22 L12 022 A10 RSV9 L3 X022 M10A23 N14 023 09 Xi C2 RSV10 M2 X023 N11LOCATOR E5 024 B10 X2/ClKIN B1 AOVOO 012 X024 P12lACK G1 025 A11 TClKO P4 AOVOO H11 X025 R13INTO H2 026 C10 TClK1 N5 OOVOO 04 X026 R14INTi Hi 027 B11 OOVOO ES X027 M11INT2 J1 02S A12 XFO G2 IOOVOO LS X02S N12INT3 J2 029 010 XF1 G3 IOOVOO M12 X029 P13MC/MP 015 030 C11 VBBP 03 MOVOO H5 X030 R15MSTRB E3 031 B12 VSUBS E4 POVOO M4 X031 P15ROY E1 VOO H4 CVSS B2 OVSS C3RESET F1 HOlO F3 VOO 08 CVSS P14 OVSS C13R/W G4 HOLOA E2 VOO MS VSS CS OVSS N3STRB F2 XROY 02 VOO H12 VSS H3 OVSS Ni3IOSTRB F4 XR/W 01 VSS NS VSS H13 IVSS B14Notes: 1) AOVOO, OOVOO, IOOVOO, MOVOO, and POVOO pins (04, 012, E8, H5, H11, L8, M4, "and M12)are on a common plane internal to the device.2) VOO pins (OS, H4, H12, and MS) are on a common plane internal to the device.3) VSS, CVSS, and IVSS pins (B2, B14, CS, H3, H13, NS, and P14) are on a common plane internalto the device.4) OVSS pins (C3, C13, N3, and N13) are on a common plane internal to the device.13-4 TMS320C3x Signal Descriptions and Electrical Characteristics
Pinout and Pin Assignments••••••••••••••••••••. ~ ••••••••.• ; •••••••••••••••••••••• :; ......... ; •••••••••••.••••••••••.••.••••••••• ;......................................................................................... • •••• :;: ••• :.! ••••••• :.:.: ••••• :.:.:;:;:; •• :;:::.:;-::;.;:;:::;:;';:;::'.:.:.:.:;:':Table 13-2. TMS320C30 Pin Assignments(<strong>Al</strong>phabeticalj (Figure 13-1 and Figure 13-2)Signal Pin Signal Pin Signal Pin Signal Pin Signal PinAO F15 08 B5 EMUS C1 TCLK1 N5 X014 N9A1 G12 09 C6 EMU6 M6 VBBP 03 X015 R10A2 G13 010 AS FSRO P3 VOO H4 X016 M9A3 G14 011 B6 FSR1 M3 VOO 08 X017 P10A4 G15 012 07 FSXO R2 VOO M8 X018 R11A5 H15 013 A6 FSX1 P1 VOO H12 X019 N10A6 H14 014 C7 H1 B3 VSS N8 X020 P11A7 J15 015 B7 H3 A1 VSS C8 X021 R12A8 J14 016 A7 HaLO F3 VSS H3 X022 M10A9 J13 017 A8 HOLOA E2 VSS H13 X023 N11A10 K15 018 B8 lACK G1 VSUBS E4 X024 P12A11 J12 019 A9 INTO H2 X1 C2 X025 R13A12 K14 020 B9 INT1 H1 X2/CLKIN B1 X026 R14A13 L15 021 C9 INT2 J1 XAO A13 X027 M11A14 K13 022 A10 INT3 J2 XA1 A14 X028 N12A15 L14 023 09 IOOVOO M12 XA2 011 X029 P13A16 M15 024 B10 IOOVOO L8 XA3 C12 X030 R15A17 K12 025 A11 IVSS B14 XA4 B13 X031 P15A18 L13 026 C10 IOSTRB F4 XA5 A15 XFO G2A19 M14 027 B11LOCATORE5 XA6 B15 XF1 G3A20 N15 028 A12 MC/MP 015 XA7 C14 XROY 02A21 M13 029 010 MOVDO H5 XA8 E12 XR/W 01A22 L12 030 C11 MSTRB E3 XA9 013A23 N14 031 B12M4 XA10 C15P~OOAOVOO H11 R/WG4 XA11 014AOVOO 012 OOVOO E8 ROY E1 XA12 E13CLKRO N4 OOVOO 04 RESET F1 XOO R4CLKR1 L4 ORO R1 RSVO J3 X01 P5CLKXO M5 OR1 N1 RSV1 J4 X02 N6CLKX1 N2 OVss N13 RSV2 K1 X03 R5CVSS B2 OVSS N3 RSV3 K2 X04 P6CVSS P14 OVSS- C3 RSV4 L1 X05 M700 C4 OVSS C13 RSV5 K3 X06 R601 05 OXO R3 RSV6 L2 X07 N702 A2 OX1 P2 RSV7 K4 X08 P703 A3 EMUO F14 RSV8 M1 X09 R704 B4 EMU1 E15 RSV9 L3 X010 P805 C5 EMU2 F13 RSV10 M2 X011 R806 06 EMU3 E14 STRB F2 X012 R907 A4 EMU4/SHZ F12 TCLKO P4 X013 P9Notes: 1) AOVoo, OOVOO, IOOVoo, MOVOO, and POVOO pins (04, 012, E8, H5, H11, L8, M4, and M12)are on a common plane internal to the device.2) VOO pins (08, H4, H12, and M8) are on a common plane internal to the device.3) VSS, CVSS, and IVSS pins (B2, B14, C8, H3, H13, N8, and P14) are on a common plane internalto the device.4) OVSS pins (C3, C13, N3, and N13) are on a common plane internal to the device.13-5
Pinout and Pin Llc,c;nnrYI'onfc13.1.2 TMS320C31 Pinouts and Pin AssignmentsFigure 13-3. TMS320C31 Pinout (Top View)The TMS320C31 device is packaged in a 132-pin plastic quad flat pack(PQFP) JDEC standard package. Figure 13-3 shows the pinouts forthis package,Figure 13-5 on page 13-16 shows the mechanical layout, and Table 13-3shows the associated pin assignments alphabetically; Table 13-4 shows theassociated pin assignments numerically.15 14 13 12 11 10 9 6 7 6 5 4 3 2 1 132131 130129126127126125124 123122121 120119 116 117116A9 16 OXOvss 19 • 115 vOOA3 20 114 FSXOA7 21 113 vssA6 22 112 CLKXOA5 23 111 CLKROvOO 24 110 FSROA4 25 109 vssA3 26 106 OROA2 27 107 INT3A1 28 106 INT2AO 29 105 vOOvss 30 104 vOO031 31 103 INT1vOO 32 102 vSSvOO 33 101 vSS030 34 100 INTOvss 35 99 lACKvSS 36 98 XF1vss 37 97 vOO029 38 96 XFO028 39 95 RESETvOO 40 94 Riw027 41 93 STRBvss 42 92 ROY026 43 91 vOO025 44 90 HOLO_ 024 45 89 HOLOA023 46 88 X1022 47 87 X2/CLKIN021 48 86 vssvOO 49 85 vss020 50 84vss51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 8313-6 TMS320C3x Signal Descriptions and Electrical Characteristics
Pinout and Pin A.
Pinout and Pin AssignmentsTable 13-4. TMS320C31 Pin Assignments (Numerical) (Figure '13-3)Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal1 A21 31 031 61 Vss 91 Yon 121 VOO2 A20 32 Voo 62 012 92 ROY 122 TCLK13 Vss 33 Voo 63 011 93 STRB 123 EMU34 Vss 34 030 64 010 94 R/W 124 EMUO5 A19 35 Vss 65 Voo 95 RESET 125 EMU16 Voo 36 Vss 66 Voo 96 XFO 126 EMU27 A18 37 Vss 67 09 97 Voo 127 MCBUMP8 A17 38 029 68 08 98 XF1 128 Vss9 A16 39 028 69 Vss 99 lACK 129 A2310 A15 40 Voo 70 Vss 100 INTO 130 A2211 A14 41 027 71 Vss 101 Vss 131 Voo12 A13 42 Vss 72 07 102 Yss. 132 Voo13 A12 43 026 73 06 103 INT114 A11 44 025 74 Voo 104 Voo15 Voo 45 024 75 05 105 Voo16 A10 46 023 76 04 106 INT217 Vss 47 022 77 03 107 INT318 A9 48 021 78 02 108 ORO19 Vss 49 Voo 79 01 109 Vss20 A8 50 020 80 00 110 FSRO21 A7 51 Vss 81 H1 111 CLKRO22 A6 52 019 82 H3 112 CLKXO23 A5 53 018 83 Voo 113 Vss24 Voo 54 017 84 YEs 114 FSXO25 A4 55 016 85 Vss 115 Voo26 A3 56 015 86 Vss 116 OXO27 A2 57 vss 87 X2/CLKIN 117 Y.ss28 A1 58 014 88 X1 118 SHZ29 AO 59 Voo 89 HOLOA 119 Vss30 Vss 60 013 90 HOLO 120 TCLKO13-8 TMS320C3x Signal Descriptions and Electrical Characteristics
13.2 Signal Descriptions13.2.1 TMS320C30 Signal DescriptionsTable 13-5. TMS320C30 Signal DescriptionsTable 13-5 describes the signals that the TMS320C30 device uses in the microprocessormode. They are listed according to the signal name; the numberof pins allocated; the input (I), output (0), or high-impedance state (Z) operatingmodes; a brief description of the signal's function; and the condition thatplaces an output pin in high impedance. A line over a signal name (for example,RESET) indicates that the signal is active low (true at a logic 0 level). Pins labeledNC are notto be connected by the user. The signals are grouped accordingto function.Signal #Pins 1/0/Zt Description Condition WhenSignal Is in High Z*Primary Bus Interface (61 Pins)031-00 32 1I0/Z 32-bit data port of the primary bus interface. S H RA23-AO 24 OIZ 24-bit address port of the primary bus interface. S H RR/W 1 OIZ Read/write signal for primary bus interface. This pin is S H Rhigh when a read is performed and low when a write isperformed over the parallel interface.STRB 1 OIZ External access strobe for the primary bus interface. S HROY 1 I Ready signal. This pin indicates that the external device Sis prepared for a primary bus interface transaction tocomplete.HOLO 1 I Hold signal for primary bus interface. When HOLO is alogic low, any ongoing transactio..!!. is completed. TheA23-AO, 031-00, STRB, and R/W signals are placedin a high-impedance state, and all transactions over theprimary bus interface are held until HOLO becomes alogic high or the NOHOLO bit of the primary bus controlregister is set.HOLOA 1 OIZ Hold acknowledge signal for primary bus interface. This Ssignal is generated in response to a logic low on fiQLO.It signals that A23-AO, 031-00, STRB, and R/Wareplaced in a high-impedance state and that all transactionsover the bus will be held. HOLDA will be high in responseto a logic high of HOLO or when the NOHOLDbit of the primary bus control register is set.Expansion Bus Interface (49 Pins)XD31-XDO 32 I/OIZ 32-bit data port of the expansion bus interface. S RXA12-XAO 13 OIZ 13-bit address port of the expansion bus interface. S RXR/W 1 OIZ Read/write signal for expansion bus interface. When a S Rread is performed, this pin is held high; when a write isperformed, this pin is low.MSTRB 1 OIZ External memory access strobe for the expansion Sbus interface.t Input (I), output (0), high-impedance state (Z).:j: S = 8HZ active, H = Hold active, R = Reset active.13-9
Signal DescriptionsTable 13-5. TMS320C30 Signal Descriptions (Continued)Signal #Pins I/O/Zt Description Condition WhenSignal Is in High Z*Expansion Bus Interface (49 Pins) (Concluded)10STRB 1 O/Z External 110 access strobe for the expansion bus inter- Sface.XRDY 1 I Ready signal. This pin indicates that the external deviceis prepared for an expansion bus interface transactionto complete.Control Signals (9 Pins)RESET 1 I Reset. When this pin is a logic low, the device is placedin the reset condition. After reset becomes a logic high,execution begins from the location specified by the resetvector.INT3-INTO 4 I External interrupts.lACK 1 O/Z Interrupt acknowledge signal. lACK is set to 0 by the SlACK instruction. This can be used to indicate the beginningor end of an interrupt service routine.MC/MP 1 I Microcomputer/microprocessor mode pin.XF1, XFO 2 I/O/Z External flag pins. They are used as general-purpose S R1/0 pins or to support interlocked processor instructions.Serial Port a Signals (6 Pins)CLKXO 1 I/O/Z Serial port 0 transmit clock. This pin serves as the serial S Rshift clock for the serial port 0 transmitter.DXO 1 I/O/Z Data transmit output. Serial port 0 transmits serial data S Ron this pin.FSXO 1 I/O/Z Frame synchronization pulse for transmit. The FSXO S Rpulse initiates the transmit data process over pin DXO.CLKRO 1 IIO/Z Serial port 0 receive clock. This pin serves as the serial S Rshift clock for the serial port a receiver.DRO, 1 IIO/Z Data receive. Serial port 0 receives serial data via the S RORO pin.FSRO 1 I/O/Z Frame synchronization pulse for receive. The FSRO S Rpulse initiates the receive data process over DRO.Serial Port 1 Signals (6 Pins)CLKX1 1 I/O/Z Serial port 1 transmit clock. This pin serves as the serial S Rshift clock for the serial port 1 transmitter.DX1 1 I/O/Z Data transmit output. Serial port 1 transmits serial data, S Ron this pin.FSX1 1 IIO/Z Frame synchronization pulse for transmit. The FSX1 S Rpulse initiates the transmit data process over pin DX1.CLKR1 1 I/O/Z Serial port 1 receive clock. This pin serves as the serial S Rshift clock for the serial port 1 receiver.t Input (I), output (0), high-impedance state (Z).:t: S = SHZ active, H = Hold active, R = Reset active.13-10 TMS320C3x Signal Descriptions and Electrical Characteristics
Signal ue'SCJ~/Dt'IOfjISTable 13-5. TMS320C30 Signal Descriptions (Continued)Signals #Pins 1/0/Zt DescriptionSerial Port 1 Signals (6 Pins) (Concluded)OR1 1 I/O/Z Oata receive. Serial port 1 receives serial data via theOR1 pin.FSR1 1 I/O/Z Frame synchronization pulse for receive. The FSR1pulse initiates the receive data process over DR1.Timer 0 Signals (1 Pin)TClKO 1 I/OIZ Timer clock. As an input, TClKO is used by timer 0 tocount external pulses. As an output pin, TClKO outputspulses generated by timer O.Timer 1 Signals (1 Pin)TClK1 1 I/O/Z Timer clock. As an input, TClK1 is used by timer 1 tocount external pulses. As an output pin, TClK1 outputspulses generated by timer 1.Supply and Oscillator Signals (29 Pins)VOD3- VDOO 4 I Four +5-V supply pins. §IOOVOD1, 10DVDDO 2 I Two +5-V supply pins. §AOVOD1, ADVDDO 2 I Two +5-V supply pins. §PDVOD 1 I One +5-V supply pin. §DOVOD1, DOVDDO 2 I Two +5-V supply pins. §MOVOD 1 I One +5-V supply pin. §VSS3- VSSO 4 I Four ground pins.DVSS3- DVSSO 4 I Four ground pins.CVSS1, CVSSO 2 I Two ground pins.IVSS 1 I One ground pin.VSSP 1 NC VSS pump oscillator output.VSUSS 1 I Substrate pin. Tie to ground.X1 1 O/Z Output pin from the internal oscillator for the crystal. Ifa crystal is not used, this pin should be left unconnected.X2/ClKIN 1 I Input pin to the internal oscillator from the crystal or aclock.H1 1 OIZ External H1 clock. This clock has a period equal to twiceClKIN.H3 1 OIZ External H3 clock. This clock has a period equal to twiceClKIN.Condition When,Signal Is in High ZI:SSSSSSSRRRRReserved (18 Pins) ~EMU2- EMUO 3 I Reserved. Use pull-ups to +5 volts. See Section 12.6.EMU3 1 OIZ Reserved. See Section 12.6.t Input (I). output (0). high-impedance state (Z).:j: S = SHZ active, H = Hold active, R = Reset active.§ Recommended decoupling capacitor is 0.1 !IF.11 Follow the connections specified for the reserved pins. 18- to 22-kQ pull-up resistors are recommended. <strong>Al</strong>l +5 volt supplypins must be connected to a common supply plane, and all ground pins must be connected to a common ground plane.S13-11
Signal Descriptions~:;:-:.:.:.:.:;:;:.~.:;:;:;:.:.:;:;:::.:.:;:::;:::::.~;:::;:::;:;:::::.~.:.~::;:.~.~::.~;:;:;:::::;:;:.~~:;:;:;:~:;:;:.~::;:;:::.~::::.~:::;:.~;:::;:::;:;:;:;:;.;:::;.::;:; •• ~;~:;.;:;:;:::;:;.;~:;:;:::.:;:;:::;:;..:;:;:;:;:::;:::::;.~ ••• :;:;:::;.::::::;:;'::;:::;:::::::::;:;:::;:-:;:;:;.;:;:;:;:.~::;:.~:;:;:;:;:.~;:::.:;.;.;:.:::;:;:;:;~.;:::;.; .............. o;.;.;.;:;~o;~:.:;:.:;:-;:;::.;y;:: .. o;o;.;::o;::~::.:;.; ........... ; .. ..: ..... ~.;.;.; •• : •••• ; .. ..: ... ;..; ....... :..;.;.;.;:;:;:;:;.;:.~;:;:::.:; .. :-::: ..... :::..;:::;::y.;:;:.:::; :;:;:;:::;:;,::;:;:;:;:::;:::;:::;:;:;:;:.~:;:::;::::::Table 13-5. TMS320C30 Signal Descriptions (Concluded)Signals #Pins I/O/Zt Description Condition WhenSignal Is in High Z*Reserved (18 Pins) 11 (Concluded)EMU4/SHZ 1 I Shutdown high impedance. An active low shuts downthe TMS320C30 and places all pins in a high-impedancestate. This signal is used for board-level testingto ensure that no dual drive conditions occur. CAU-TION: An active low on the SHZ pin corruptsTMS320C30 memory and register contents. Reset thedevice with an SHZ=1 to restore it to a known operatingcondition.EMU6, EMUS 2 NC Reserved.RSV10- RSVO 11 I Reserved. Use pull-ups on each pin to +5 volts.Locator (1 Pin)Locator 1 NC Reserved. See Figure 13-1 and Table 13-1.t Input (I), output (0), high-impedance state (Z).:j: S = SHZ active, H = Hold active, R = Reset active.11 Follow the connections specified for the reserved pins. 18- to 22-kQ pull-up resistors are recommended. <strong>Al</strong>l +5 volt supplypins must be connected to a common supply plane, and all ground pins must be connected to a common ground plane.13.2.2 TMS320C31 Signal DescriptionsTable 13-6. TMS320C31 Signal DescriptionsTable 13-6 describes the signals that the TMS320C31 device uses in the microprocessormode. They are listed according to the signal name; the numberof pins allocated; the input (I), output (O), or high-impedance state (Z) operatgingmodes; a brief description of the signal's function; and the condition thatplaces an output pin in high impedance. A line overasignal name (for example,RESET) indicates that the signal is active low (true at a logic 0 level).Signal # Pins I/O/Zt Description Condition WhenSignal Is in High Z*Primary Bus Interface (61 Pins)031-00 32 I/O/Z 32-bit data port. S H RA23-:-AO 24 O/Z 24-bit address port .. S H RRIW 1 O/Z Read/write signal. This pin is high when a read is per- S H Rformed; low when a write is performed over the parallelinterface.STRB 1 . O/Z External access strobe. S HROY 1 I Ready signal. This pin indicates thatth~ external deviceis prepared for a transaction completion.HOLO 1 I Hold signal. When HOLO is a logic low, any ongoingtransaction i~ completed. The A23-AO, 031-00,STRB, and RIW signals are'placed in a high-impedancestate, and all transactions over the primary bus interfaceare held until HOLO becomes a logic high, or theNOHOLO bit of the primary bus control register is set.t Input (I), output (0), high-impedance (Z)state.:j: S = SHZ active, H = Hold active, R = Reset active.13-12 TMS320C3x Signal Descriptions and Electrical Characteristics
Table 13-6. TMS320C31 Signal Descriptions' (Continued)Signal # Pins 1I0lZt Description Condition WhenSignal Is in High Z*Primary Bus Interface (61 Pins) (Concluded)HOLDA 1 O/Z Hold acknowledge signal. This signal is generated in re- 8sponse to a logic low on !iOLD. It signals that A23-AO,D31-DO, STRB, and R/W are placed in a high-impedancestate and that all transactions over the bus will beheld. HOLDA will be high in response to a logic high ofHOLD, or the NOHOLD bit of the primary bus controlregister is set.Control Signals (10 Pins)RESET 1 I Reset. When this pin is a logic low, the device is placedin the reset condition. When reset becomes a logic 1,execution begins from the location specified by the resetvector .INT3-INTO 4 I . External interrupts.lACK 1 O/Z Interrupt acknowledge signal. lACK is set to 1 by the SlACK instruction. This can be used to indicate the beginningor end of an interrupt service routine.MCBUMP 1 I Microcomputer boot loader/microprocessor mode pin.8HZ 1 I Shut down high Z. An active low shuts down theTMS320C31 and places all pins in a high-impedancestate. This signal is used for board-level testing to ensurethat no dual drive conditions occur. CAUTION: Anactive low on the SHZ pin corrupts TMS320C31memory and register contents. Reset the device with anSHZ = 1 to restore it to a known operating condition.XF1, XFO 2 I/O/Z External flag pins. They are used as general-purpose 8 RI/O pins or to support interlocked processor instructions.Serial Port 0 Signals (6 Pins)CLKRO 1 I/O/Z Serial port a receive clock. This pin serves as the serial S Rshift clock for the serial port a receiver.CLKXO 1 I/O/Z Serial port a transmit clock. This pin serves as the serial S Rshift clock for the serial port a transmitter.DRO 1 I/O/Z Data receive. Serial port a receives serial data via the S RDRO pin.DXO 1 I/O/Z Data transmit output. Serial port a transmits serial data S Ron this pin.FSRO 1 I/O/Z Frame sychronization pulse for receive. The FSRO S Rpulse initiates the receive data process over DRO.FSXO 1 I/O/Z Frame synchronization pulse for transmit. The FSXO S Rpulse initiates the transmit data process over pin DXO.t Input (I), output (0), high-impedance state (Z).:j: S = SHZ active, H = Hold active, R = Reset active.13-13
TMS320C3x Mechanical Data13.3 TMS320C3x Mechanical DataFigure 13-4. TMS320C30 181-Pin PGA DimensionsPin A1Corner--~~Indicatorr------r---.~Thermal Resistance Characteristics40 ,4 (1.590)37 ,6 (1.480)LParameter°CIWReJC 3.81----- 1-----ReJA 21.6ReJA 13.3ReJA 9.7ReJA. 8.3ReJA 7.4ReJA 7.1Air FlowLFPMN/A----02004006008001000l---40,4 (1.590) 1>137,6 (1.480)4,95 (0.195)2,54 (0.1"00) l,1,40 (0.055)~~~~~~~~~----~Jr I IJ 1,14 (0.045)t f~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~rmC'o 508 (0 020) Il -e>I 1'.27 (0.050) Nom, . -. Ora (4 Places)4,06 (0.160)0,406 (0.016)2,54 (0.100)(181 Places)2,54 (0.100) T.P.R ee@@@@@@@@@@@@@fP@@@@@@@@@@@@@@@N @@@@@@@@@@@@@@@M@@@@@@@@@@@@@@@L @@@@ @ @@@@K @@@@ Bottom @@@@J @@@@ View @@@@35,6 (1.40) H @@@@@ @@@@@REF G @@@@ ;- Locator @@@@LF @@@@ ~@@@@E @@@@@ . @ @@@@D@@@@@@@@@@@@@@,e@C@@@@@@@@@@@@@@@. B @@@@@@@@@@@@@@ eH-----%.A @ e @@@@@@@@@@@@ e1ll------.-Index Corner 1 2 3 4 5 6 7 8 9 1011121314152,54 (0.100) TYP-ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES13-15
TMS320C3x Mechanical DataFigure 13-5. TMS320C31 f 32-Pin Plastic Quad Flat Pack0,635 (0.025) Nom 1 j4-0,254 (0.010) Nom lr4,45 (0.175)4,19 (0.165) M0,76 (0.030) No0 ~ ~27,56 (1.085)27,31 (1.075)24,18 (0.952)24,08 (0.948)24,18 (0.952)24,08 (0.948)27,56 (1.085)27,31 (1.075)Thermal Resistance CharacteristicsParameter°CIWAir FlowLFPMRaJC 11.0 N/Af------r.----- ----RaJA 55.1 0RaJA TBD 200RaJA TBD 400RaJA TBD 600RaJA TBD 800RaJA TBD 1000·ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES13-16 TMS320C3x Signal Descriptions and Electrical Characteristics
Electrical Spt3cil'icatior7s13.4 Electrical SpecificationsTable 13-7.Absolute Maximum Ratings over Specified Temperature'RangeCondition/CharacteristicSupply voltage range, VOOInput voltage rangeOutput voltage rangeContinuous power dissipationOperating case temperature rangeTMS320C30ITMS320C31 Range- 0.3 Vto 7 V- 0.3 Vt07V- 0.3V to 7 V3.15 W for TMS320C301.7 W for TMS320C31(See Note 3)OOCt085°CStorage temperature range - 55°C to 150°CNotes:1) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Thisis a stress rating only; functional operation of the device at these or any other conditions beyond those indicatedin the "Recommended Operating Conditions" section of this specification is not implied. Exposure to absolute-maximum-ratedconditions for extended periods may affect device reliability.2) <strong>Al</strong>l voltage values are with respect to VSS.3) Actual operating power will be less. This value was obtained under specially produced worst-case test conditions,which are not sustained during normal device operation. These conditions consist of continuous parallel writes ofa checkerboard pattern to both primary and expansion buses at the maximum rate possible. See nominal (100) currentspecification in Table 13-8 and also read Calculation of TMS320C30 Power Dissipation, Appendix E.Table 13-8.Recommended Operating ConditionstParameter Min Nom Max UnitVOO Supply voltages (OOVOO, etc.) 4.75 5 5.25 VVSS Supply voltages (CVSS, etc.) 0 VVIH High-level input voltage 2 VOO+ V0.3tVil low-level input voltage -0.3t 0.8 VIOH High-level output current -300 IlAIOl low-level output current 2 mAT Operating case temperature 0 85 °CVTH ClKIN high-level input voltage for ClKIN 2.6 VOO + 0.3t VNote:Guaranteed from characterization but not tested.Note 1 for Table 13-7 also applies to this table. <strong>Al</strong>l input and output voltages except for ClKIN are TTL-compatible. ClKINmay be driven by a CMOS clock.13-17
Signal Transition Levels13.5 Signal Transition Levels13.5.1 TTL-Level OutputsTTL-compatible output levels are driven to a minimum logic-high level of 2.4volts and to a maximum logic-low level of 0.6 volt. Figure 13-7 shows the TTLleveloutputs.Figure 13-7. TTL-Level OutputsJ---- ------------ -----~------ ---------------- ---2.4 V2.0V1.0 V0.6 VTTL-output transition times are specified as follows:a For a high-to-Iow transition, the level at which the output is said to be nolonger high is 2.0 volts, and the level at which the output is said to be lowis 1.0 volt.a For a low-to-high transition, the level at which the output is said to be nolonger low is 1.0 volt, and the level at which the output is said to be highis 2.0 volts.13.5.2 TTL-Level InputsFigure 13-8. TTL -Level Inputs----z- ~----- 20V--~-- -----. --------- ----- 90~'----. ----------------- . --- 10},o"'--- O.svTTL-compatible input transition times are specified as follows:a For a high-to-Iow transition on an input signal, the level at which the inputis said to be no longer high is 2.0 volts, and the level at which the input issaid to be low is 0.8 volt.a For a low-to-hightransition on an input signal, the level at which the inputis said to be no longer low is 0.8 volt, and the level at which the input is saidto be high is 2.0 volts.Figure 13-8 shows the TTL-level inputs.13-19
13.6 TimingTiming specifications apply to the TMS320C30 and TMS320C31.13.6.1 X2/CLKIN, H1, and H3 TimingFigure 13-9. Timing for X2/CLKINFigure 13-10. Timing for H1/H3Table 13-1 Odefinesthetiming parametersforthe ClKIN, H1, and H3 interfacesignals. The numbers shown in parentheses in Figure 13-9 and Figure 13-10correspond with those in the No. column of Table 13-10.X2/CLKIN-/4-- (5) ~i ~(4):(1)-.1 I II I III I14- (2) ~~ (10) ~I41 14- (9) --.I 14- (6) II I I I IH1 _~YT 1\1 ;r---l.aI l(8)~ 1_ Ir-(7)~1-.I j4-- (9.1) ~.14- (9.1)IIH3~~i ------------~;1~------~-----I I I II ~ j+- (9) ~ 14- (6):.~--- (7) ------ll l.-- (8)-.: :~ (10) ~I13-20TMS320C3x Signal Descriptions and Electrical Characteristics
Table 13-10. Timing Parameters for eLKIN, H1, and H3 (Figure 13-9 and Figure 13-10)No. Name Description(1 ) tf(C!) ClKIN fall time(2) tw(Cll) ClKIN low pulse durationtc(CI) = min(3) tw(CIH) ClKIN high pulse durationtc(Ci) = min(4) tr(CI) ClKIN rise time(5) t~lCIl ClKIN cycle time(6) tf(H) H1/H3 fall time(7) tw(HL) Hi IH3 low pulse duration(8) tw(HH) H1/H3 high pulse duration(9) tr(H) Hi IH3 rise time(9.1 ) td(HL-HH) Delay from Hi (H3) low toH3(H1) high(10) tc(Hl Hi IH3 cycle timet Guaranteed from characterization but not tested.:j: Guaranteed by design but not tested.Note: P = tc(CI)TMS320C30-27 TMS320C30-33 TMS320C30-40TMS320C31-27 TMS320C31-33Min Max Min Max Min Max6:j: 5:j: 5:j:14 10 914 10 96:j: 5:j: 5:j:37 303 30 303 25 3034 3 3P-6 P-6 P-5P-7 P-7 P-65 4 3ot 6 ot 5 ot 474 606 60 606 50 606Unitnsnsnsnsnsnsnsnsnsnsns13-21
13.6.2 Memory Read/Write TimingTable 13-11 defines memory read/write timing parameters. The numbersshown in parentheses in Figure 13-11 and Figure 13-12 correspond withthose in the No. column of Table 13-11.Figure 13-11. Timing for Memory ((M)STRB = 0) ReadH3H1(11)-.! ~(M)STRB : :.1(X)RIWiiii~(X)A __ ..J~(X)DI: --.j /4- (d)i i L---....~---I iI i I1 1\: i I ~ ______ _~ (~4.1/14.2) i -.l:.- (13.1/13.2)I ~ ~'-~5-'1-/1-5-'2-)---(26) -.I ~ t-+I ~ (16)-----~il~II-~OI 1>-----(17.1/17.2)~ j4-____ ~ ~~(1.....;8)~ __________ _~yI13-22TMS320C3x Signal Descriptions and Electrical Characteristics
Table 13-11. Timing Parameters for a Memory ((M)STRB) = 0) Read/Write (Figure 13-11 and Figure 13-12)TMS320C30-27 TMS320C30-33 TMS320C30-40TMS320C31-27 TMS320C31-33No. Name Description Min Max Min Max Min Max Unit(11 ) td(H1 L-(M)SL) H1 low to (M)STRB low delay 0+ 13 0+ 10 0+ 6 ns(12) id(H1 L-(M)SH) H1 low to (M)STRB high delay 0+ 13 0+ 10 0+ 6 ns(13.1 ) td(H1 H-RWL) H1 high to R/W low delay 0+ 13 0+ 10 0+ 9 ns(13.2) td(H1 H-XRWL) H1 high to XR/W low delay 0+ 19 0+ 15 0+ 13 ns(14.1 ) td(H1 L-A) H1 low to A valid delay 0+ 16 0+ 14 0+ 10 ns(14.2) td(H1 L-XA) H1 low to XA valid delay 0+ 12 0+ 10 0+ 9 ns(15.1 ) tsu(D)R D setup before H1 low (read) 18 16 14 ns(15.2) tsu(XD)R XD setup before H1 low (read) 21 18 16 ns(16) th«X)D)R (X)D hold time after H1 low 0 0 0 ns(read)(17.1) tsu(RDY) RDY setup before H1 high 10 8 8 ns(17.2) tsu(XRDY) XRDY setup before H1 high 11 9 9 ns(18) th((X)RDY) (X)RDY hold time after H1 high 0 0 0 ns+ Guaranteed by design but not tested.Figure 13-12. Timing for Memory ( (M)STRB = 0) WriteH3H11 1~ l4 (12)1(11)-.1 /+-1(M)STRB I l'i II: \1 1 11 1 1 1(X)RIW(X)A(X)D--.I 1+-1 (13.1/13.2) 11 1'i~I--.I !+ (14.1/14.2)I I=X : ~;~ ti4-- (22.1/22.2)(20) ~ ~ 14-(21)___ I:-.! 14- (19)~~----+----------)~-----~.,((17.1/17.2) ~ Jf (18)(X)RDY'i J{II~ ____________ JX ___________ _~ ______ -J)r-----------\ I13-23
Table 13-11. Timing Parameters for a Memory ((M)STRB = 0) Read/Write (Figure 13-11 and Figure 13-12)(Concluded)No. Name Description(19) td(H1 H-(X)RWH) H1 high to (X)R/W high (write)delay(20) tv((X)D)W (X)D valid after H1 low (write)(21) th((X)D)W (X)D hold time after H1 high(write)(22.1) td(H1H-A) H1 high to A valid on back-tobackwrite cycles (write) delay(22.2) td(H1H-XA) H1 high to XA valid on back-tobackwrite cycles (write) delay(26) td(A-(X)RDY) (X)RDY delay from A valid delayt Guaranteed from characterization but not tested.=1= Guaranteed by design but not tested.TMS320C30-27TMS320C31-27Min0=1=Max1325233210tTMS320C30-33 TMS320C30-40 UnitTMS320C30-33Min Max Min Max Unit10 9 ns20 17 ns0=1= 0=1= ns18 15 ns25 21 ns8t 7t ns13-24 TMS320C3x Signal Descriptions and Electrical Characteristics
Figure 13-13. Timing for Memory ( IOSTRB = 0) ReadH3H1II ,I (11.1)~ ~ (12.1)~ IcC-- I'I , , I: ~ : /-L---t:----I ~--------~, I--.I 14- (13.1) ,-.J. ~ (23)ITable 13-12. Timing Parameters for a Memory (IOSTRB = 0) Read (Figure 13-13 and Figure 13-14)TMS320C30-27 TMS320C30-33 TMS320C30-40No. Name Description Min Max Min Max Min Max Unit(11.1 ) td(H1 H-IOSL) H1 high to IOSTRB low delay 0+ 13 0+ 10 0+ 9 ns(12.1) td(H1 H-IOSH) H1 high to IOSTRB high 0+ 13 0+ 10 0+ 9 nsdelay(13.1 ) td(H1 L-XRWH) H1 low to XR/W high delay 0+ 13 0+ 10 0+ 9 ns(14.3) td(H1L-XA) H1 low to XA valid delay 0+ 13 0+ 10 0+ 9 ns(15.3) tsu(XD)R XD setup before H1 high 19 15 13 ns(16.1 ) th(XD)R XD hold time after H1 high 0 0 0 ns(17.3) tsu(XRDY) XRDY setup before H1 high 11 9 9 ns(18.1 ) th(XRDY) XRDY hold time after H1 0 0 0 nshigh+ Guaranteed by design but not tested.13-25
Figure 13-14.Timing for Memory (IOSTRB = 0) WriteH3H11 11 1 1(11.1)-'1 14- (12.1)-.1 14- 1! \l ! /I"'"--i-: ----1 1 ~I -----+'1 ~1!4- (13.1)(2~3). 14- 1 1 1 II 1 1 1 IXRiW 1 1 1 1 1// I 1 1--.1 \4-'(14.3) : I: ~XA---JX : ' I' A-l4- (24) I -'1 :+- (25)XD-----«_~~-2)---(17.3) -.! r4=~ 14- (18.1)\l Y'--~--Table 13-13. Timing Parameters for a Memory (IOSTRB = 0) Write (Figure 13-14)TMS320C30-27 TMS320C30-33 TMS320C30-40No. Name Description Min Max Min Max Min Max(23) td(H1 L-XRWL) H1 low to XRIW low delay 0+ 19 0+ 15 0+ 13(24) tv(XD)W XD valid after H1 high 38 30 25(25) th(XD)W XD hold time after H1 low 0 0 0+ Guaranteed by design but not tested.Unitnsnsns13-26 TMS320C3x Signal Descriptions and Electrical Characteristics
13.6.3 XFO and XF1 Timing When Executing LOFI or LOllTable 13-14 defines timing parameters for XFO and XF1 when you executeLDFI or LDII. The numbers shown in parentheses in Figure 13-15 correspondwith those in the No. column of Table 13-14.Figure 13-15. Timing for XFO and XF1 When Executing LDFI or LDIIH3FetchLDFlorLDIl Decode ReadExecuteH1(M)STRB(X)RIW(X)A(X)D(X)RDYXFO PinXF1 Pin(2) ~ 14-Ir.; 14- (3)-=\lV-----,:X\\ /IIIX __----!heI\l(1) -.I 14-Table 13-14. Timing Parameters for XFO and XF1 When Executing LDFI or LDII (Figure 13-15)TMS320C30-27 TMS320C30-33 TMS320C30-40TMS320C31-27 TMS320C31-33No. Name Description Min Max Min Max Min Max(1 ) td(H3H-XFOL) H3 high to XFO low delay 19 15 13(2) tsu(XF1) XF1 setup before H1 low 13 10 9(3) th(XF1) XF1 hold time after H1 low 0 0 0Unitnsnsns13-27
13.6.4 XFO Timing When Executing STFI and STIITable 13-15 defines the timing parameters for the XFO and XF1 when you executeSTFI or STII. The numbers shown in parentheses in Figure 13-16 correspondwith those in the No. column of Table 13-15.Figure 13-16. Timing for XFO When Executing a STFI or STIIH3Hi(M)STRBIII \I(x)RiW ~ ;-(X)A~: >C(X)DI-{ ~(X)RDY ~ ~(1)~rIIXFO PinTable 13-15. Timing Parameters for XFO When Executing STFI or STII (Figure 13-16)IIIIITMS320C30-27 TMS320C30-33 TMS320C30-40TMS320C31-27 TMS320C31-33No. Name Description Min Max Min Max Min Max Unit(1 ) td(H3H-XFOH) H3 high to XFO high delay 19 15 13 ns/13-28'TMS320C3x Signal Descriptions and Electrical Characteristics
13.6.5 XFO and XF1 Timing When Executing SIGITable 13-16 defines the timing parameters for the XFO and XF1 when you executeSIGI. The numbers shown in parentheses in Figure 13-17 correspondwith those in the No. column of Table 13-16.Figure 13-17. Timing for XFO and XF1 When Executing SIGIH3FetchSIGI Decode Read ExecuteH1XFOXF1(3) ~ r-IIIIII~~(4)~lC~ ~ (1) ..J ~ (2)__\i....olliO...:__~--'!-Table 13-16. Timing Parameters for XFO and XF1 When Executing SIGI (Figure 13-17)TMS320C30-27 TMS320C30-33 TMS320C30-40TMS320C31-27 TMS320C31-33No. Name Description Min Max Min Max Min Max(1 ) td(H3H-XFOL) H3 high to XFO low delay 19 15 13(2) td(H3H-XFOH) H3 high to XFO high delay 19 15 13(3) tsu(XF1) XF1 setup before H1 low 13 10 9(4) th(XF1 ) XF1 hold time after H1 low 0 0 0Unitnsnsnsns13-29
13.6.6 Loading When the XF Pin Is Configured as an OutputTable 13-17 defines the timing parameters for loading the XF register whenthe XF pin is configured as an output. The numbers shown in parentheses inFigure 13-18 correspond with those in the No. column of Table 13-17.Figure 13-18. Timing for Loading XF Register When Configured as an Output PinH3Fetch LoadInstruction Decode Read ExecuteH1OUTXFBitXF Pin~10ro~ !4- (1)------------------------------------~~I___Table 13-17. Timing Parameters for Loading XF Register When Configured as an OUlput Pin (Figure 13-18)TMS320C30-27 TMS320C30-33 TMS320C30-40TMS320C31-27 TMS320C31-33No. Name Description Min Max Min Max Min Max Unit(1 ) tv(H3H-XF) H3 high to XF valid 19 15 13 ns13-30 TMS320C3x Signal Descriptions and Electrical Characteristics
Timing13.6.7 Changing the XF Pin From an Output to an InputTable 13-18 defines the timing parameters for changing the XF pin from anoutput pin to an input pin. The numbers shown in parentheses in Figure 13-19correspond with those in the No. column of Table 13-18.Figure 13-19. Timing for Change of XF From Output to Input ModeH3ExecuteI Load of IOFBuffers Gofrom Ouput Synchronizer Value on Pin Ito Input Delay I Seen in IOFH1IOXFBitXFPinOutput--.I 14- (1)I4\ t+- (2)-t'J-- (3)I IINXF BitTable 13-18. Timing Parameters of XF Changing From Output to Input Mode (Figure 13-19),TMS320C30-27 TMS320C30-33 TMS320C30-40TMS320C31-27 TMS320C31-33No. Name Description Min Max Min Max Min Max(1 ) th(H3H-XF01) XF hold after H3 high 19 15 13(2) tsu(XF) XF setup before H1 low 13 10 9(3) th(XF) XF hold after H1 low 0 0 0Unitnsnsns13-31
Timing~:.:; •••••;.•:••• ~ •••••••••;:.:;:;:.:;!;~~;~!:!;:;~!::;:;::::*:;;:::::~::::;;;:;::~;:::;:::::;:::;~:::::;:!;:;:;:::;:;::;;:;:.;:::;~;:;:;:::::::;:;:;::::;;:::;:;:;::::::::~.:;::;:::;::::::;:'.:;:~;:::;::~;':::~~';:;y;o-..."::";';:::'-;";::":;Y:::':';';';O;';"";';O;':':;••;0;.;:;.;0;0;.;0;.;•••::;.;.;0......::.:;0••;0;0;.;0;.;.......;.;0...0;-:.;.;.;0;-:.;.;.;.;0;::-:-,-••;0;0;0••; •••;0;0;0:0;0;0........;.........;•• 9; .... y;·;·: ..·;o.·;o;..·;o.·::;.....;·;....·;:;o;v;o::;o•.;o;:;-;.............;::~;·x·::;.;:::;:::::::::;:>:;:::::;:;:;:::;:;:::::::::,.(.:;:::::::;:;~13.6.8 Changing the XF Pin From an Input to an OutputTable 13-19 defines the timing pa~ameters for changing the XF pin from an inputpin to an output pin. The numbers shown in parentheses in Figure 13-20correspond with those in the No. column of Table 13-19.,Figure 13-20. Timing for Change of XF From Input to Output ModeExecution ofLoad of IOFH3H1IOXFBitXFPinIII--+I 14- (1)------------------------------------~
Timing:';:Jo':!;::"~,:~::-«=:O:;O;:J::.:y::~:e;:;Y~~:;Y;O;»S':;OMY.M':·;~y';V,;(
Table 13~20. Timing Parameters for RESET (Figure 13-21)TMS320C30-27 TMS320C30-33 TMS320C30-40TMS320C31-27 TMS320C31-33No. Name Description Min Max Min Max Min Max Unit(1 ) tsu(RESET) Setupfor RESETbeforeClKIN 28 Pt 10 Pt 10 Pt nslow(2.1 ) td(ClKINH-H1 H) ClKIN high to Hi high delay § 6 20 6 16 4 14 ns(2.2) td(ClKINH-H1 l) ClKIN high to Hi low delay § 6 20 6 16 4 14 ns(3) tsu(RESETH-H1 l) Setup for RESET high 13 10 9 nsbefore Hi low and after 10 Hiclock cycles(5.1 ) td(ClKINH-H3l) ClKIN high to H3 low delay § 6 20 6 16 4 14 ns(5.2) td(ClKINH-H3H) ClKIN high to H3 high delay § 6 20 6 16 4 14 ns(8) tdis(H1 H-(X)D) Hi high to (X)D disabled (high 19t 1St 13t nsimpedance)(9) tdis(H3H-(X)A) H3 high to (X)A disabled (high 13t 10t 9t nsimpedance)(10) td(H3H-CONTROlH) H3 high to control signals high 13t 10t 9t nsdelay(11 ) td(H1 H-IACKH) Hi high to lACK high delay 13t 10t 9t ns(12) tdis(RESETl-ASYNCH) RESET low to asynchronously 31t 2St 21t nsreset signals disabled (high impedance)t Characterized but not tested.§ See Figure 13-22 for temperature dependence for the 33 MHz TMS320C30.Note: P = tc(CI)Figure 13-22. eLKIN to H11H3 as a Function of Temperature222018TMS320C30·334.75 V::; VDD::; 5.25 V(/)16.sC')~It412.9z:;z10...J()84oo 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 COCase Temperature (Co)13-35
13.6.10 5HZ Pin TimingFigure 13-23. Timing for SHZ PinTable 13-21 defines the timing parameters for the 8HZ pin. The numbersshown in parentheses in Figure 13-23 correspond with those in the No. columnof Table 13-21.<strong>Al</strong>l I/O PinsH3~~H1~~___ 14- __\ I ----~~/jY----J*I(1_)-3"""")0---'1\1.,.1;_(2_)::_I4-=--:,,~-.t{p,-_____.:________Note:Enabling SHZ destroys TMS32aC3x register and memory contents. Assert SHZ = 1 and reset the TMS32aC3x to restoreit to a known condition.Table 13-21. Timing Parameters for SHZ Pin (Figure 13-23)TMS320C30-27 TMS320C30-33 TMS320C30-40TMS320C31-27 TMS320C31-33No. Name Description Min Max Min Max Min Max Unit(1 ) tdis(SHZ) SHZ low to all 0, I/O pins dis- at 2Pt at 2Pt at 2Pt nsabled (high impedance)(2) ten(SHZ) SHZ high to all 0, 110 pins en- at 2Pt at 2Pt at 2Pt nsabled (active)t Characterized but not tested.Note: P = tc(CI)13-36 TMS320C3x Signal Descriptions and Electrical Characteristics
13.6.11 Interrupt Response TimingFigure 13-24. Timing for INT3-INTO ResponseTable 13-22 defines the timing parameters for the INT signals. The numbersshown in parentheses in Figure 13-24 correspond with those in the No. columnof Table 13-22.H3IIReset orInterruptVector ReadH1~ !.f- (1)INT3 -IN~~ ~I1+--(2)~INT3 -I~I~~ _____;1----:.___........____ADDR----------------~Data----------------------------~~----------~_Table 13-22. Timing Parameters for INT3-INTO (Figure 13-24)TMS320C30-27 TMS320C30-33 TMS320C30-40TMS320C31-27 TMS320C31-33No. Name Description Min Max Min Max Min Max Unit(1 ) tsu(INT) INT3-INTO setup before H1 19 15 13 nslow(2) tw(INT) Interrupt pulse duration toguarantee only one interruptp 2Pt P 2Pt P 2Pt nsseent Characterized but not tested.Note: P = tc(H)The interrupt (INT) pins are asynchronous 'inputs that can be asserted at anytime during a clock cycle. The TMS320C3x interrupts are level sensitive, notedge sensitive. Interrupts are detected on the falling edge of H1. Therefore,interrupts must be set up and held to the falling edge of H 1 for proper detection.13-37
For the processor to recognize only one interrupt on a given input, an interruptpulse must be set up and held to:Qa minimum of one H1 falling edge, andQno more than two H1 falling edges.The TMS320C3x can accept an interrupt from the same source every two H1clock cycles.If the specified timings are met, the exact sequence shown in Figure 13-24 willoccur; otherwise, an additional delay of one clock cycle may occur.13-38TMS320C3x Signal Descriptions and Electrical Characteristics
13.6.12 Interrupt Acknowledge TimingFigure 13-25. Timing for lACKThe lACK output is active for the entire duration of the bus cycle. Its activity isextended if the bus cycle utilizes wait states.Table 13-23 defines the timing parameters for the lACK signal. The numbersshown in parentheses in Figure 13-25 correspond with those in the No. columnof Table 13-23.Fetch lACKInstructionlACK DataReadH3HiADDR__\1___II1
II13.6.13 Data Rate Timing ModesFigure 13-26. Timing for Fixed Data Rate ModeUnless otherwise indicated, the data rate timings shown in Figure 13-26 andFigure 13-27 are valid for all serial port modes, incll:Jding handshake. For afunctional description of serial portoperation, refer to subsection 8.2j 2 of theTMS320C3x User's Guide.Table 13-24 defines the timing parameters forthe serial port timing. The numbersshown in parentheses in Figure 13-26 correspond with those in the No.column of Table 13-24.H114-1 14- (3) ~ I I I ICLKX/R J(li=-i --"'~ X- ~ (3) --:x N. !J~ \ rI I I I T I -.I k- (5) II I I I -.! 14- (4) II : ~1 ~ ~.~ ~(1~OX BijO )DR ~ ~~=~~~~=~~FSRIII! III ~ (10) I4t- 1(9) -+: r- : i ~ (9) 14-FSX(INT) I f -.I 14- (11) \.1 IfI I ~ j~X(EXn~: :I I (11)--.1 k--(12) -.I i4-Notes: 1) Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = o.2) Timing diagrams depend upon the length of the serial port word, where n = 8, 16, 24, or 32 bits, respectively.13-40 TMS320C3x Signal Descriptions and Electrical Characteristics
Figure 13-27. Timing for Variable Data Rate ModeCLKX/R ----.it '- IF ''--_--'I ~~~ I+- (9) r I II 1-FSX(INT) I I 1 1 1I ~ 14-1 (14) I I(12) -JIll L.- I 1 I IFSX(EXT) &);-Ij/;:: (6) ~ II :1;: ~ (15)~DX (13) ~J Bit n-1 ~;'-----B-it -n--2---X Bit n-3 :: Bit 0 }-~ J4- (11)FSR ------JX i ::~(10) -.! *-DR "m~~~~~~_1 ~ Bitn-2 ~ Bitn-3 ~~(7) ~(8)Notes: 1) Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = O.2) Timing diagrams depend upon the length of the serial port word, where n = 8, 16, 24, or 32 bits, respectively.3) The timings that are not specified expressly for the variable data rate mode are the same as those that are specifiedfor the fixed data rate mode.13-41
Table 13-24. Serial Port Timing Parameters (Figure 13-26 and Figure 13-27)No. Name Description(1 ) td(H1-SCK) H1 high to internal CLKX/R delay(2) tc(SCK) CLKX/R cycle time CLKX/R ext(3) tw(SCK) CLKX/R high/low pulse duration(4) tr(SCK) CLKX/R rise time(5) tf(SCK) CLKX/R fall timeCLKX/R intCLKX/R extCLKX/R int(6) td(DX) CLKX to DX valid delay CLKX extCLKX int(7) tsu(DR) DR setup before CLKR extCLKR lowCLKR int(8) th(DR) DR hold from CLKR extCLKR lowCLKR int(9) td(FSX) CLKX to internal CLKX extFSX high/low delay(10) tsu(FSR) FSR setup before CLKRlow(11 ) th(FS) FSX/R inputCLKX/R low(12) tsu(FSX) External FSX setup beforeCLKXCLKX intCLKR extCLKR inthold from CLKX/R extCLKX/R intCLKX extCLKX int(13) td(CH-DX)V CLKX to first DX bit, FSX pre- CLKX extcedes CLKX high delayCLKX int(14) td(FSX-DX)V I FSX to first DX bit, CLKX precedes FSX delay(15) td(DXZ) CLKX high to DX high impedance following lastdata bit delayt Guaranteed by design but not tested.+ Not tested.Mintc(H)x2.6tTMS320C30-27TMS320C31-27Max19tc(H)x2 tc(H)X2 32 +tc(H)+ 12t[tc(SCK)/2]-1513311301313130-[tc(H)-8]-[tc(H)-21 ][tc(SCK)/2]+510t10t44254021[tc(SCK)/2]-10+tc(SCK)/2+45264525tUnitnsnsnsnsnsnsnsnsnsnsnsnsnsnsns13-42 TMS320C3x Signal Descriptions and Electrical Characteristics
Table 13-24. Serial Port Timing Parameters (Figure 13-26 and Figure 13-27) (Continued)t:j:No. Name Description(1 ) td(H1-SCK) H1 high to internal CLKX/R delay(2) tc(SCK) CLKX/R cycle time CLKX/R ext(3) tw(SCK) CLKXlR high/low pulse duration(4) tr(SCK) CLKX/R rise time(5) tf(SCK) CLKX/R fall timeCLKX/R intCLKX/R extCLKX/R int(6) td(OX) CLKX to OX valid delay CLKX extCLKX int(7) tsu(OR) DR setup before CLKR extCLKR lowCLKR int(8) th(OR) DR hold from CLKR extCLKR lowCLKR int(9) td(FSX) CLKX to internal CLKX extFSX high/low delayCLKX int(10) tsu(FSR) FSR setup before CLKR extCLKR lowCLKR int(11 ) th(FS) FSX/R input hold from CLKX/R extCLKX/R lowCLKX/R int(12) tsu(FSX) External FSX setup before CLKX extCLKX(13) td(CH-OX)V CLKX to first DX bit, FSX precedesCLKX high delayCLKX intCLKX extCLKX int(14) td(FSX-OX)V FSX to first OX bit, CLKX precedes FSX delay(15) td(OXZ) CLKX high to OX high impedance following lastdata bit delayGuaranteed by design but not tested.Not tested.MintciHlx2.6ttc(H)x2tC(H)+12t[tc(SCK)/2]-1510251001010100-[tc(H)-8][tc(H)-21]TMS320C30-33TMS320C31-33Max15tc(H)x232:j:[tc(SCK)/2]+58t8t35203217[tc(SCK)/2]-10:j:tc(SCK)/2:j:36213620tUnitnsnsnsnsnsnsnsnsnsnsnsnsnsnsns13-43
Table 13-24. Serial Port Timing Parameters (Figure 13-26 and Figure 13-27) (Concluded)No. Name Description(1 ) td(H1-SCK) H1 high to internal CLKX/R delay(2) tc(SCK) CLKX/R cycle time CLKX/R extCLKX/R int(3) tw(SCK) CLKX/R high/low pulse du- CLKX/R extration(4) tr(SCK) CLKX/R rise time(5) tf(SCK) CLKX/R fall timeCLKX/R int(6) td(DX) CLKX to DX valid delay CLKX extCLKX int(7) tsu(DR) DR setup before CLKR extCLKR lowCLKR int(8) th(DR) DR hold from CLKR extCLKR lowCLKR int(9) td(FSX) CLKX to internal CLKX extFSX high/low delayCLKX int(10) tsu(FSR) FSR setup before CLKR extCLKR lowCLKR int(11 ) th(FS) FSX/R input hold from CLKX/R extCLKX/R lowCLKX/R int(12) tsu(FSX) External FSX setup before CLKX extCLKX(13) td(CH7""DX)V CLKX to first OX bit, FSX precedesCLKX high delayCLKX intCLKX extCLKX intMintc(H)x2.6ttc(H)x2tc(H)+10t[tc(SCK)/21-5921909990-[tc(H)-8]-[tc(H)-21 ]TMS320C30-40Max13tc(H)x232:f:[tc(SCK)/2]+57t7t30172715[tc(SCK)/2]-10:f:tc(SCK)/2:f:3018Unitnsnsnsnsnsnsnsnsnsnsnsnsnst:f:(14) td(FSX-OX)V FSX to first OX bit, CLKX precedes FSX delay(15) td(OXZ) CLKX high to OX high impedance following lastdata bit delay .Guaranteed by design but not tested.Not tested.3017tnsns13-44 TMS320C3x Signal Descriptions and Electrical Characteristics
13.6.14 HOLD TimingFigure 13-28. Timing for HOLD/HOLDAHOLD is an asynchronous input that can be asserted at any time during a clockcycle. If the specified timings are met, the exact sequence shown inFigure 13-28 will occur; otherwise, an additional delay of one clock cycle mayoccur.Table 13-25 defines the timing parameters for the HOLD and HOLDA signals.The numbers shown in parentheses in Figure 13-28 correspond with those inthe No. column of Table 13-25.The NOHOLD bit of the primary bus control register (refer to Chapter 7, subsection7.1.1) overrides the HOLD signal. When this bit is set, the devicecomes out of hold and prevents future hold cycles from occurring.H3H1~ l.- (1) I -t!*-(1)HOLD~(4)VIIII I ~ /4- (3) -.! *- (3)I I ~ (6) ~IHOLDA I I I~111(7) -.I~ 1 j4-(8) ~ ~(9)STRB 71 I' I ~\:I::-J 1+-(11)~(10)II~~ 14- (12) -.I 14- (13)IIR/W ) IIA ):~~ 14-(16)ID Write Data )Note:HOLDA will go low in response to HOLD going low and will continue to remain low until one H1 cycle after HOLD goes backhigh as shown in Figure 13-28.13-45
Table 13-25. Timing Parameters for HOLD/HOLDA (Figure 13-28)No. Name Description(1 ) tsu(HOLD) HOLD setup before H1 low(3) tv(HOLDA) HOLDA valid after H1 low(4) tw(HOLD) HOLD Iqw duration(6) tw(HOLDA) HOLDA low duration(7) td(H1 L-SH)H H1 low to STRB high for a HOLDdelay(8) tdis(H1 L-S) H1 low to STRB disabled (high-impedancestate)(9) ten(H1 L-S) H1 low to STRB enabled (active)(10) tdis(H1 L-RW) H1 low to RIW disabled (high-impedancestate)(11 ) ten(H1 L-RW) Hi low to R/W enabled (active)(12) tdis(H1 L-A) H1 low to address disabled (highimpedancestate)(13) ten(H1L-A) H1 low to address enabled (valid)(16) tdis(H1 H-D) H1 high to data disabled (high-impedancestate)TMS320C30-27TMS320C31-27Min Max190=1= 142tc(H)tcH-5t0=1= 130:1= 13t0:1= 130=1= 13t0:1= 130=1= 13t0=1= 190=1= 13tTMS320C30-33 TMS320C30-40TMS320C31-33Min Max Min Max Unit15 13 ns0=1= 10 0=1= 9 ns2tc(H) 2tc(H) nstcH-5t tcH-5t ns0=1= 10 0=1= 9 ns0:1= 10t 0:1= 9t ns0+ 10 0+ 9 ns0=1= 10t 0=1= 9t nsa; 10 a; 9 nsa; 10t 0=1= 9t ns0=1= 15 0=1= 13 ns0=1= 10t 0=1= 9t nst Characterized but not tested.=1= Not tested.Note: HOLD is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, theexact sequence shown will occur; otherwise, an additional delay of one clock cycle may occur.13-46 TMS320C3x Signal Descriptions and Electrical Characteristics
13.6.15 General-Purpose 1/0 Timing13.6.15.1 Peripheral Pin 110 TimingPeripheral pins include CLKXO/1 , CLKRO/1, DXO/1, DRO/1, FSXO/1, FSRO/1,and TelKO/1. The contents of the internal control registers associated witheach peripheral define the modes for these pins.Table 13-26 defines peripheral pin general-purpose I/O timing parameters.The numbers shown in parentheses in Figure 13-29 correspond with those inthe No. column of Table 13-26.Figure 13-29. Timing for Peripheral Pin General-Purpose 110Table 13-26. Timing Parameters for Peripheral Pin General-Purpose 110 (Figure 13-29)TMS320C30-27 TMS320C30-33 TMS320C30-40TMS320C31-27 TMS320C31-33No. Name Description Min . Max Min Max Min Max Unit(1 ) tsu (GPIOH1 L) General-purpose input setup before 15 12 10 nsH110w(2) th(GPIOH1 L) General-purpose input hold time 0 0 0 nsafter H1 low(3) td(GPIOH1 H) General-purpose output delay after 19 15 13 nsH1 highNote:Peripheral pins include CLKXO/1 , CLKRO/1 , DXO/1 , DRO/1 , FSXO/1 , FSRO/1 , and TCLKO/1. The modes of these pins aredefined by the contents of internal control registers associated with each peripheral.13-47
13.6.15.2 Changing the Peripheral Pin 110 ModesTable 13-27 and Table 13-28 show the timing parameters for changing the peripheralpin from a general-purpose output pin to a general-purpose input pinand vice versa. The numbers shown in parentheses in Figure 13-30 andFigure 13-31 correspond to those shown in the No. column of Table 13-27and Table 13-28. ~Figure 13-30. Timing for Change of Peripheral Pin From General-Purpose Output to Input ModeExecuteStore OfPeripheralControlRegisterBuffers Gofrom Outputto InputSynchronizer DelayValue on PinSeen inPeripheralControlRegisterH3H110---....Control Bit(2) ~ itt!!\4: (3)Data Bit~SampledTable 13-27. Timing Parameters for Peripheral Pin Changing From General-Purpose Output to Input Mode(Figure 13-30)TMS320C30-27 TMS320C30-33TMS320C31-27 TMS320C31-33TMS320C30-40No. Name Description Min Max' Min Max Min Max Unit(1 ) th(H3H} Hold after H1 high 19 15 13 ns(2) tsu (GPIOH1 L) Peripheral pin setup before H1 low 13 10 9 ns(3) th(GPIOH1 L) Peripheral pin hold after H1 low 0 0 0 ns13-48 TMS320C3x Signal Descriptions and Electrical Characteristics
Figure 13-31. Timing for Change of Peripheral Pin From General-Purpose Input to Output ModeExecution of Storeof Peripheral ControlRegisterH3H110 ControlBit14-(1 )Peripheral --------------------fVPin,'----Table 13-28. Timing Parameters for Peripheral Pin Changing From General-Purpose Input to Output Mode(Figure 13-31)TMS320C30-27 TMS320C30-33 TMS320C30-40TMS320C31-27 TMS320C31-33No. Name Description Min Max Min Max Min Max Unit(1 ) td(GPIOH1 H) H1 high to peripheral pin switching 19 15 13 nsfrom input to output delay13-49
13.6.16 Timer Pin TimingFigure 13-32. Timing for Timer PinH3Valid logic level periods and polarity are specified by the contents of the internalcontrol registers.ITable 13-29 defines the timing parameters for the timer pin. The numbersshown in parentheses in Figure 13-32 correspond with those in the No. columnof Table 13-29.~~Hi~~!4-- (2) ~ (3) ~ j4- L! LL-(1)--1 j4- ~. ! ...... ~_-_(_3) ____Peripher~1 X 't' . ~~:::x:Pin _--.J·T"""--~j4--(5-)-~-I ------~ (4) ~Table 13-29. Timing Parameters for Timer Pin (Figure 13-32)TMS320C30-27TMS320C31-27No. Name· Description* Min Max(1 ) tsu (TCLKH1 L) TCLK ext setup before Hi low TCLK ext 15(2) th{TCLKH1 L) TCLK ext hold after Hi low TCLK ext 0(3) td(TCLKH1 H) Hi high to TCLK int valid delay TCLK int 13(4) tc(TCLK) TCLK cycle time TCLK ext tc(H)x2.6tnsTCLK int tcJH)x2 tc(H1X2 32 t ns(5) tw(TCLK) TCLK high/low pulse duration TCLK ext tc(H)+12tnsTCLK int [tC(TCLK)/2]-15 [tc (TCLK)/2]+5 nst Guaranteed by design but not tested.:j: Timing parameters 1 and 2 are applicable for a synchronous input clock. Timing parameters 4 and 5 are applicable for anasynchr~nous input clock.Unitnsnsns13-50 TMS320C3x Signal Descriptions and Electrical Characteristics
Table 13-29. Timing Parameters for Timer Pin (Figure 13-32) (Continued)t:j:TMS320C30-33TMS320C31-33No. Name Description* Min Max Unit(1 ) tsu(TCLKH1 Lt TCLK ext setup before H1 low TCLK ext 12 ns(2) th(TCLKH1 L) TCLK ext hold after H 1 low TCLK ext 0 ns(3) td(TCLKH1 H) H1 high to TCLK int valid delay TCLK int 10 ns(4) tc(TCLK) TCLK cycle time TCLK ext t c (H)x2.6t nsTCLK int tc(H)x2 tc(Htx232t ns(5) tw(TCLK) TCLK high/low pulse duration TCLK ext tc(H)+12t nsTCLK int [tcLTCLK)/2]-15 [tcJTCLKy2]+5 nsGuaranteed by design but not tested.Timing parameters 1 and 2 are applicable for a synchronous input clock. TIming parameters 4 and 5 are applicable for anasynchronous input clock.Table 13-29. Timing Parameters for Timer Pin (Figure 13-32) (Continued)t:j:TMS320C30-40No. Name Description=l= Min Max Unit(1 ) tsu(TCLKH1 L) TCLK ext setup before H1 low TCLK ext 10 ns(2) th(TCLKH1 L) TCLK ext hold after H1 low TCLK ext 0 ns(3) td(TCLKH1 H) H1 high to TCLK int valid delay TCLK int 9 ns(4) tc(TCLK) TCLK cycle time TCLK ext tc(H)x2.6t nsTCLK int tc(H)x2 tc(H)x2 32 t ns(5) tw(TCLK) TCLK high/low pulse duration TCLK ext tc(H)+10t nsTCLK int [tc(TCLK)/2]-5 [tc(TCLK)/2]+5 nsGuaranteed by design but not tested.TIming parameters 1 and 2 are applicable for a synchronous input clock. TIming parameters 4 and 5 are applicable for anasynchronous input clock.•13-51
13-52 TMS320C3x Signal Descriptions and Electrical Characteristics
~ ______ ln_s_tr_u_c_ti_o_n_o __ p_CO_d_e_s ________________________________ ~" ...'II1II
~~ ______________________________ ln_s_tr_u_C_ti_on __ o_p_C_O_de_s ______ ~
Appendix AInstruction Opcodes::;;;;::::~::::::;::::;:;;::::::::~:::;:~:;:Z:::;;:;::;;r:;:::;:;:::::;:;::;::;:;;;:::::::;:::;;::::;::~::;::!;:;:;!;!;!;:;!;!:!;:;!;:;::!;;;!;:;;::;:;:;:;:;!;!;!;:;:;:;:;:;!;:;:;:;:;:;' ::;:::::;:::::::;;;:::::::::;:::::;~:::::;:::;:::::;:;:::;!;!;:;!::;!;!:!;!::::;:;!;:;:;!;:;!;!;!;!: :;:;:;:;:;:;:::;:::;.;.;.;.;.;.;.... . ..•.•.......... ',' ...•.....•..••.. '.;.:.;!;:;:;:;:;:;:;:;:;:;:;!;:;:;:;!;:;:;!;:;:;:;:;:::: ... ...•...•.•.••....••.. .. •••.... .•..•.. ' ........ :::::~;::::;:::::::: ....• '.Table A-1. TMS320C3x Instruction OpcodesThe opcode fields for all the TMS320C3x instructions are shown in Table A-1.Bits in the table marked with a hyphen are defined in the individual instructiondescription (see Chapter 11). Table A-1, along with the instruction descriptions,fully defines the instruction words. The opcodes are listed in numericalorder.INSTRUCTION 31 30 29 28 27 26 25 24 23ABSF 0 0 0 0 0 0 0 0 0ABSI 0 0 0 0 0 0 0 0 1ADDC 0 0 0 0 0 0 0 1 0ADDF 0 0 0 0 0 0 0 1 1ADDI 0 0 0 0 0 0 1 0 0AND 0 0 0 0 0 0 1 0 1ANON 0 0 0 0 0 0 1 1 0ASH 0 0 0 0 0 0 1 1 1CMPF 0 0 0 0 0 1 0 0 0CMPI 0 0 0 0 0 1 0 0 1FIX 0 0 0 0 0 1 0 1 0FLOAT 0 0 0 0 0 1 0 1 1IDLE 0 0 0 0 0 1 1 0 0LDE 0 0 0 0 0 1 1 0 1LDF 0 0 0 0 0 1 1 1 0LDFI 0 0 0 0 0 1 1 1 1LDI 0 0 0 0 1 0 0 0 0LOll 0 0 0 0 1 0 0 0 1LDM 0 0 0 0 1 0 0 1 0LSH 0 0 0 0 1 0 0 1 1MPYF 0 0 0 0 1 0 1 0 0MPYI 0 0 0 0 1 0 1 0 1NEGB 0 0 0 0 1 0 1 1 0NEGF 0 0 0 0 1 0 1 1 1NEGI 0 0 0 0 1 1 0 0 0A-1
Instruction Opcodes~~~~:;:;~:-!>:;:;:;s~:;:;:~:;:;~.:;:;:;:;:;::::::>::::::::::::~:::::::::".:::::::::;:::;:::::::::::::::::::::;:;:;:;:;:;:::::;~.:::::::::::::;:::::::;:"(.:::::::;:"':;:::"':::::::::".(,:::;:::;~:;:;:::::::;:;';:"N. ••• :;o;~.~.;~::.~;.;:::;::'::::::::::::::Io:::::::::;:;:::::.:".:::::::;·;·:·;·;.;:~::h..::.::••.:.•.:::••;.:::.M!:::......:.......:;O;.;::::::::..::.:::'......;.::•••::.;.;:;..::.;.;:;o;.......;•••:•• ~ .....:.:.......... o;o ..........::;o:....:•• ;.;.~:;.;:;:.:;••!>'«.,;:......;::.::;:;:;:;:::;:".....::::::;.;:::::::"..;:;.:::.;:::::::;::~::"~(.:::::::::::;:::::::::".:0TableA-1.TMS320C3x Instruction Opcodes (Continued)INSTRUCTION 31 30 29 28 27 26 25 24 23NOP 0 0 0 0 1 1 0 0 1NORM 0 0 0 0 1 1 0 1 0NOT 0 0 0 0 1 1 0 1 1POP 0 0 0 0 1 1 1 0 0POPF 0 0 0 0 1 1 1 0 1PUSH 0 0 0 0 1 1 1 1 0PUSHF 0 0 0 0 1 1 1 1 1OR 0 0 0 1 0 0 o· 0 0RND 0 0 0 1 0 0 0 1 0ROL 0 0 0 1 0 0 0 1 1ROLC 0 0 0 1 0 0 1 0 0ROR 0 0 0 1 0 0 1 0 1RORC 0 0 0 1 0 0 1 1 0RPTS 0 0 0 1 0 0 1 1 1STF 0 0 0 1 0 1 0 0 0STFI 0 0 0 1 0 1 0 0 1STI 0 0 0 1 0 1 0 1 0STI! 0 0 0 1 0 1 0 1 1SIGI 0 0 0 1 0 1 1 0 0SUBS 0 0 0 1 0 1 1 0 1SUBC 0 0 0 1 0 1 1 1 0SUBF 0 0 0 1 0 1 1 1 1SUBI 0 0 0 1 1 0 0 0 0SUBRB 0 0 0 1 1 0 0 0 1SUBRF 0 0 0 1 1 0 0 1 0SUBRI 0 0 0 1 1 0 0 1 1TSTB 0 0 0 1 1 0 1 0 0XOR 0 0 0 1 1 0 1 0 1lACK 0 0 0 1 1 0 1 1 0ADDC3 0 0 1 0 0 0 0 0 0ADDF3 0 0 1 0 0 0 0 0 1ADDI3 0 0 1 0 0 0 0 1 0AND3 0 0 1 0 0 0 0 1 1ANDN3 0 0 1 0 0 0 1 0 0ASH3 0 0 1 0 0 0 1 0 1CMPF3 0 0 1 0 0 0 1 1 0CMPI3 0 0 1 0 0 0 1 1 1A-2 Instruction Opcodes
Instruction UpCOC'1esTableA-1.TMS320C3x Instruction Opcodes (Continued)INSTRUCTION 31 30 29 28 27 26 25 24 23LSH3 0 0 1 0 0 1 0 0 0MPYF3 0 0 1 0 0 1 0 0 1MPYI3 0 0 1 0 0 1 0 1 0OR3 0 0 1 0 0 1 0 1 1SUBB3 0 0 1 0 0 1 1 0 0SUBF3 0 0 1 0 0 1 1 0 1SUB13 0 0 1 0, 0 1 1 1 0TSTB3 0 0 1 0 0 1 1 1 1XOR3 0 0 1 0 1 0 0 0 0LDFcond 0 1 0 0 - - - - -LDlcond 0 1 0 1 - - - - -BR(D)t 0 1 1 0 0 0 0 - -CALL 0 1 1 0 0 0 1 - -RPTB 0 1 1 0 0 1 0 - -SWI 0 1 1 0 0 1 1 - -. Bcond(D)t 0 1 1 0 1 0 - - -DBcond(D) t 0 1 1 0 1 1 - - -CALLcond 0 1 1 1 0 0 - - -TRAPcond 0 1 1 1 0 1 0 - -RETlcond 0 1 1 1 1 0 0 0 0RETScond 0 1 1 1 1 0 0 0 1MPYF311ADDF3 1 0 0 0 0 0 0 0 -1 0 0 0 0 0 0 1 -1 0 0 0 0 0 1 0 -1 0 0 0 0 0 1 1 -MPYF311SUBF3 1 0 0 0 0 1 0 0 -1 0 0 0 0 1 0 1 -1 0 0 0 0 1 1 0 -1 0 0 0 0 1 1 1 -MPYI311ADDI3 1 0 0 0 1 0 0 0 -1 0 0 0 1 0 0 1 -1 0 0 0 1 0 1 0 -1 0 0 0 1 0 1 1 -t Opcode same for standard and delayed instructions.A-3
Instruction V/J(;UUf;t::;TableA-1.TMS320C3x Instruction Opcodes (Concluded)INSTRUCTION 31 30 29 28 27 26 25 24 23MPYI311SUBI3 1 0 0 0 1 1 0 0 -1 0 0 0 1 1 0 1 -1 0 0 0 1 1 1 0 -1 0 0 0 1 1 1 1 -STFIISTF 1 1 0 0 0 0 0 - -STIIISTI 1 1 0 0 0 0 1 - -LDFIILDF 1 1 0 0 0 1 0 - -LDIlILDI 1 1 0 0 0 1 1 - -ABSFIISTF 1 1 0 0 1 0 0 - -ABSIIiSTI 1 1 0 0 1 0 1 - -ADDF311STF 1 1 0 0 1 1 0 - -ADDI311STI 1 1 0 0 1 1 1 - -AND311STI 1 1 0 1 0 0 0 - -ASH311STI 1 1 0 1 0 0 1 - -FIXIISTI 1 1 0 1 0 1 0 - -FLOATIISTF 1 1 0 1 0 1 1 - -LDFIISTF 1 1 0 1 1 0 0 - -LDIIISTI 1 1 0 1 1 0 1 - -LSH311STI 1 1 0 1 1 1 0 - -MPYF311STF 1 1 0 1 1 1 1 - -MPYI311STI 1 1 1 0 0 0 0 - -NEGFIISTF 1 1 1 0 0 0 1 - -NEGIlISTI 1 1 1 0 0 1 0 - -NOTIISTI 1 1 1 0 0 1 1 - -OR311STI 1 1 1 0 1 0 0 - -SUBF311STF 1 1 1 0 1 0 1 - -SUBI311STI 1 1 1 0 1 1 0 - -XOR311STI 1 1 1 0 1 1 1 - -Reserved for reset,traps, and interrupts0 1 1 1 1 1 1 1 1A-4 Instruction Opcodes
L.-___ D_e_v_el_o_p_m_e_n_t_S_u_p_p_o_r_tl_P_a_rt_O_rd_e_r_1_n ..... fO_r_m_a_t_io_n _______--i,_=..
___________ D_e_v_e_lo_p_m_e_"_t_s_u_p_p_o_r_tl_p_art_O_r_d_e_r_I"_f_O_rm_at_io_" ___ ~
Appendix BDevelopment Support/Part Order Information~~~=~~~~~~~::~::::::;::~::~;;::~~;;::~::[:;:[{~~~~:~::;::~:mm:~~i;:;:;;:~Wxt~~~~~:~:~~~~:§::::;::;§:~:~:~~;m-:::::::~~:::::::::::::::::::::~:~m~:::~~~mill~:'::;:!$:~m;~~~~:~§~:~::;:;:::~m::m~~::;$~:~::;:::m;:;:r~~~:~:::~:~::~mm§~:~ill~a~:;:;::::~~~::~~~:~§~::~~~::::::_~: .._.::._::::_:::_n'_,,,,,'1:'''''''-:-:'''''':':-:_--''''-,__"'*"'"__' _::':_::::-""":::1_"_I::*""' .........,_,...., _::::"""c:·~_:::_::::_;"_::0::_::_,___,_==_'_'
TMS320C3x Development Supportv.-:::;:;:;:::::;:::;:::::;::::::::.:::::;:::;:::::;:;:::;~.:;:;:;:; ~:"~:::~:::~-::::::-:;:::;:;:::;:;:;:;:;:;:;:;:::;:;:::::::;:;:::;:;:.:;:::;:~;:~:,:,:;:::::::::;:;:::;:;:;:;.::;o(o'!::::;:::"I.;:~::;:;:::::;:~:::::;:::::::;.::::::--:::::::::::::'.:::::::::::::;.;... ;:;:::::::::::::::::::::::::::::::;::~.:;:::::::::;:'.. :.;:::::::;:;::::.;-::;:;.;o::;:;:::'.:::::::::::~-::.;:::;.;:::;:::::::;:::::::;:;.;.;o;.:.;.:::::.::;~;:::;:::;:;:;:;O;'::;o;o.:;:.-::;:::::;:,.:::::::::::;:,..:::::::~:.;:::::::::;:;:,I.::::;:::::;:;::.;:,,y::::;:::::;:::::-.:::::::;:::;:~;:::::::;::::::~:;::~::;B.1 TMS320C3x Development SupportTexas Instruments supplies extensive development support and completedocumentation for the TMS320C3x generation of digital signal processors. TIalso offers a complete line of software and hardware tools (shown in Table B-2on page B-15) to support in application development, evaluation of the processorperformance, algorithm implementations, and full integration of designmodules.Software development tools includeQ TMS320C3x Macro Assembler/LinkerQ TMS320C3x Optimizing ANSI C Compiler[:I TMS320C3x SimulatorQ SPOX (the TMS320C3x Operating System).Hardware development tools consist ofQ TMS320C30 Evaluation Module (EVM)Q TMS320C3x XDS500 EmulatorQ TMS320C30 XDS 1000 Development SystemQ TMS320C30 Hewlett-Packard 64776 Analysis SubsystemThe macro assembler/linker converts assembly language into executable objectcode. The TMS320C3x optimizing C compiler supports high-level languageprogramming and is a full implementation of the standard ANSI C language.The simulator is a software program that simulates nonreal-time operationof the TMS320C3x, allowing verification and monitoring of the state of theprocessor.Both the TMS320C3x ~DSSOO Emulator and the TMS320C30 XDS 1000 DevelopmentEnvironment provide full-speed, in-circuit emulation forTMS320C3x system design and debug on the IBM PC/AT and compatible devices.The TMS320C3x XDS500 supports hardware and software debug ofyour target system. The TMS320C30 XDS1 000 provides system needs fromconcept to prototype. It includes the XDSSOO Emulator Board and theTMS320C30 Application Board (a predefined sample target system that containsa TMS320C30).These hardware and software products are easy to use and offer the designerthe tools needed to significantly reduce TMS320C3x system development timeand cost.A description of key features for each TMS320C3x development support toolis provided in the following subsections. For ordering information, see SectionB.4. For detailed information on these tools, refer to TMS320 Family DevelopmentSupport Reference Guide (literature number SPRU011 B). Call the CustomerResponse Center at 800-336-S236 to request a copy.8-2Development Support/Part Order Information
t.TMS320C3x Development Support............ ; ... ;.............................. ....•.........•. ....•.......• ;.;.... . ........ .8.1.1 Macro Assembler/LinkerThe TMS320C3x Macro Assembler/Linker is a software tool that convertssource mnemonics to executable object code. It is distinguished by these keyfeatures:a Macro capabilities and library functionsa Conditional assemblya Relocatable modulesa Complete error diagnosticsa Symbol table and cross-referenceTo address specific needs, the TMS320C3x Macro Assembler/Linker isshipped with four programs:1) The assembler translates assembly language source files into machinelanguage object files.2) The archiver collects a group of files-object, source, or macros-into asingle archive file.3) The linker combines object files into a single executable object module.4) The object format converter changes the object file into Intel, Tektronix,or TI-tagged object format. The converted file can be downloaded to anEPROM programmer; the EPROM code can then be executed on theTMS320C3x device.The main purpose of this development process, shown in Figure 8-1, is to producea module that can be executed in a system that contains a TMS320C3xdevice or the software or hardware development tools.The macro assembler/linker is currently available for PC/MS-DOS (versions3.0 and up) and OS/2, Macintosh MPW, VAX VMS, SUN-3, and SUN-4 UNIXoperating systems.8.1.2 Optimizing ANSI C CompilerThe TI C compiler translates the widely used ANSI C language directly intohighly optimized assembly code. This code is then assembled and linked usingTI's assembler/linker, which is shipped with the compileLThe C compiler provides for enhanced productivity by enabling the applicationdesigner to program in C, thus making code easier to prototype, debug, andbenchmark. Furthermore, already existing code can be directly compiled andexecuted on a TMS320C3x.8-3
TMS320C3x Development Support; ................••.•...•......•...••.•.•.....•.•. ;.; ... : .•.•.... :.y .•••.... ; ........................ , .........•.....•...........•.•.•.............•...............••..••..••.......... ; ....••The TMS320C3x Optimizing ANSI C Compiler is a full-featured C compiler.Compiler features includeQQComplete and exact conformity to the ANSI C specification.Highly efficient code. The compiler incorporates state-of-the-art genericand target-specific optimizations.Q C programs that can be linked with assembly language routines, allowinghand coding of time-critical functions in TMS320C3x assembly language.QQQQQANSI-standard run-time library.A C shell program to facilitate one-step translation from C source to executablecode.A variety of listing files.Fast compilation to increase productivity.Complete and useful diagnostics (error messages).Q Validation with the de facto industry standard Plum Hall and Perennial validationsuites. -Below are key optimizations performed by the compiler.QQTMS320C3x-specific optimations• Register variables• Register tracking/targeting• Cost-based register allocation• Autoincrement addressing modes• Repeat blocks• TMS320C3x parallel instructions• Conditional instructions• TMS320C3x delayed branchesGeneral-purpose C optimizations• <strong>Al</strong>gebraic reordering/symbolic simplification/constant folding• Data flow optimizations• Copy propagation• Common subexpression elimination• Redundant assignment elimination• <strong>Al</strong>ias disambiguation• Branch optimizations/controlled-flow simplification• Loop induction variable optimizations/strength reduction• Loop unrolling• Loop rotation8-4Development Support/Part Order Information
TMS320C3x DevelopmentII Loop-invariant code motion• In-line expansion of run-time support library functionsThe compiler supports DEC VAX/VMS, IBM-PC with PC-DOS (versions 3.0and up) or OS/2 compatibles, Macintosh MPW, and SUN-3 and SUN-4 UNIXsystems.The assembler/linker is included with the shipment of the C compiler.8.1.3 SimulatorThe TMS320C3x Simulator is a software program that simulates operation ofthe TMS320C3x. These key features make the simulator effective and flexiblein TMS320C3x software development:QQQQQQSimulation of the entire TMS320C3x digital signal processor instructionsetSimulation of the key TMS320C3x peripheral features (DMA, timers, andserial port)Command entry either from menu-driven keystrokes (menu mode) orfroma batch file (line mode)Help menus for all screen modesStandard interface that can be user customizedQuick storage and retrieval of simulation parameters from fjles to facilitatepreparation for individual sessions .QReverse assembly that allows editing and reassembly of source statementsa Memory contents that c'an be displayed in hexadecimal 32-bit values andassembled source at the same time.a Execution modes including single-step, until, while, for, and run to breakpointor user halt.QBreakpointsa Simulation of cache utilizationa Cycle countingThe simulator allows verification and monitoring of the state of the processor.Simulation occurs at thousands of instructions per second (VAX/VMS andSUN-3/SUN-4 UNIX) or hundreds of instructions per second (PC/MS-DOS).The user interface in the simulator is identical to that in the XDS. SeeFigure B-2 for an example.8-5
TMS320C3xFigure 8-2. TMS320C3x Simulator User Interfacepulldownmenus~ ~.t~i:M~~~t~) Watch >\ ~Emlory i.Col,o.r .•.•.•. ~ope. f0002d 62f00042£0002e 19840001£0002£ 6aOOOOOc£00030 08510b02disassembly ~ .•.display ~gggi~ g~~~~g~iC sourcedisplayinteractive ~command entryand historywindowf00033 04£10003f00034 51£10004f00035 08484011CALLSUBIBULOIANDLOICMPILOIHILOIxcall1,SPcall+30 90xf0003c)'I< AR3 (2), IRO3';"IRO@02051H,ARO3,IRO4,IRO*+ARO (IRO) , ARO£00 FILE: sample. 0------------..1."'-'..;...;;...-'--"-,£00 00052 } .:£00 00053fOO 00054 call (newvalue}fOO 00055 int newva1ue;fOO 00056 {fOO 00057 static int value'" 0;fOO 00058- 0005900060switch (newvalue & 3)(00061 case 0 : str.a '" newvalue ; break;ggg~~ ~::: ~ ~ :~ 0151': astr(7]--, return _ :00064 case 3 : xc ~ ;~~ ~reak;··00065 c 75435 DI5P:1 astr(7] .f4-1.~O::.;;O~O 6=..:6:'-'~""""""'-"' __--l fl 3 (0] 0 •COMMANDwhatis strstruct xxx str;,§,tep»> Il~; ~xOOfOOO gl ~ I:•.mf4 [ •.. ] [3] 54.. [4] 3II m !23y L....>,.;9;.L,....:7-=.8:;,..9 -..,..__"~ yE-~"!"-'fl'MrMl1'~H-function calltracebacknatu ral-fa rmatdata displaysscrolling datadisplays with~ on-screen,interactiveediting·The simulator currently supports PC/MS-DOS, VAX VMS, and VAX Ultrix oper.ating systems, and SUN-3 and SUN-4 UNIX systems.8.1.4 The TMS320C3x Operating System (SPOX)SPOX, developed by Spectron Microsystems Inc., is the industry's first hardware-independentsoftware base for a real-time DSP operating system. SPOXfeatures a set of high-level C-callable software functions, which are independentof the underlying hardware platform, thus insulating real-time DSP applicationsfrom many low-level system details.SPOX differs from other operating systems or real-time kernels (such as UNIX)just as the TMS320C3x differs from a general-purpose microprocessor: bothSPOX and the TMS320C3x are application-specific. SPOX affords its userstwo important benefits: software productivity and application portability.Functional ComponentsThe SPOX software interface augments high-level programming languageslike C by accessing a virtual DSP machine that consists of four functional components:1) DSP MATH furnishes application software with a rich set of operationsused to manipulate vectors, matrices, and filters.8-6 Development Support/Part Order Information
TMS320C3x DevelopmentFigure 8-3. Internal SPOX Architecture2) Hierarchical Memory Managementgives the application explicit control inallocating data storage from different segments of system memory.3) Stream liD presents a device-independent application interface used toinput and outputs blocks of data from a variety of peripherals.4) Realtime Kerne/provides primitives for scheduling and synchronizing multiple,prioritized tasks.Figure B-3 illustrates the functional components of SPOX.DSP Memory DeviceMath Management DriversProcessor Memory PeripheralsSPOX Product OfferingThe SPOX software interface is supported in different execution environments,Including Sun workstations, IBM personal computers, and VAX minicomputers.On these host systems, DSP application programs written in high-levellanguages such as C can be developed and debugged in familiar software engineeringenvironments equipped with powerful tools and utilities. Afterward,these same programs can be recompiled with the TMS320C3x C compileravailable for these same hosts, then benchmarked on the TMS320C3x softwaresimulator for time and space using a version of SPOX designed specificallyfor use with the TMS320C3x simulator or a hardware development systemsuch as the XDS1 000.Spectron also offers a SPOX Porting Kit. This product includes an unbundledversion of SPOX, whose generic components can be configured forthe specificTMS320C3x application and integrated with system-dependent software(drivers, math functions, etc.) supplied by the developer.SPOX is currently packaged with the TMS320C3x XDS1 000 Development Environment.For more information regarding SPOX, contact Spectron Microsysternsat (805) 967-0503.8-7
TMS320C3x Development Support8.1.S TMS320C3x Evaluation ModuleWith the introduction of the TMS320C30 Evaluation Module (EVM), Texas Instrumentshas removed the cost barrier to evaluating and developing floatingpointDSP applications. The TMS320C30 EVM is the first floating-point DSPtool that bridges the price-performance gap between software simulators andfull-featured development platforms.Each EVM comes complete with a PC halfcard and software package. TheEVM board containsa One TMS320C30, a 33-MFLOP, 32-bit floating-point DSPa 16K-word zero-wait-state SRAM, allowing coding of most algorithms directlyon the boarda A speaker/microphone-ready analog interface for multimedia, speech,and audio applications developmenta A multiprocessor serial port interface for connecting to multiple EVMsa A host port for PC communicationsThe system also comes with all the software required to begin applications developmenton a PC host. Equipped with a C and assembly language sourcelevel debugger for DSP, the EVM has a window-oriented, mouse-driven interfacethat enables the downloading, executing, and debugging of assemblycode or C code. See subsection 8.1.6, Emulator User Interface, for more information.The TMS320C3x Assembler/Linker is also included with the EVM. For userswho prefer programming in a high-level language, an optimizing ANSI C compilerand Ada compiler are offered separately.8.1.6 TMS320C3x Emulator - Extended Development System (XDSSOO andXDS1000)The TMS320C3x XDS500 and XDS1000 Emulators are user-friendly, PCbaseddevelopment systems, which provide all the features necessary to performfull-speed in-circuit emulation with the TMS320C3x. These emulators allowyou to develop software and hardware and to integrate the software andhardware with the target system. A revolutionary scan path interface gives controland access to every memory location and register of the TMS320C3x. Keyfeatures of the TMS320C3x emulators includea no cable length/transmission problems,a a nonintrusive system,a no loading problems on signals,8-8Development Support/Part Order Information
TMS320C3x Ue1i1etC)Dm 'entQQQQQno artificial memory limitations,a common screen interface for ease of use,easy installation,in-system emulation,no variance from data sheet.Full-speed execution and monitoring of the target system is performed by the4-wire interface or scan path via a 12-pin target connector. This scan path controlsthe TMS320C3x in the target application and provides access to all theregisters as well as to internal and external memory of the device. Since programexecution takes place on the TMS320C3x in the target system, there areno timing differences during emulation. This new design offers significant advantagesover traditional emulators:QQQno cable length/transmission problems,a nonintrusive system,no loading problems on signals,Q no artificial memory limitations,Q a common screen interface for ease of use,QFigure 8-4. Multiprocessing Emulationeasy installation,Q in-system emulation,Qno variance from data sheet.The 12-pin target connector allows for emulation of multiprocessing applications.For example, if five TMS320C3xs exist on one board, as shown inFigure 8-4, each device is emulated by simply moving the 12-pin target connectorfrom one TMS320C3x connector to the next. Real-time emulation is stillmaintained, and the information of each processor is preserved.I TMS320C3x I I TMS320C3x I I TMS320C3x I I TMS320C3x I I TMS320C3x I12-Pin Connectors8-9
TMS320C3x Uel(elcloment SupportThe TMS320C3x XDS 1000 is a full-speed emulator that comes with a prebuilttarget system for early design development. The TMS320C3x XDS1 000 canhelp debug hardware in real time, debug software in real time, and integratethe hardware and software together.The XDS500 and XDS1 000 are available on an IBM PC/AT or compatible machinewith 640K of memory running PC/MS-DOS. The XDS500 is shipped withthe macro assembler/linker. The XDS1000 is shipped with the optimizing Ccompiler, macro assembler/linker, and SPOX.Emulator User InterfaceIncluded with the XDS500 and XDS1 000 systems is the C/assembly sourcedebugger and a new menu-, mouse-, and window-oriented environment thatis the standard for all TMS320 DSP interfaces. The user-friendly, state-of-theartinterface is flexible and easily customized for color display or monochromemonitors. Its features includeQQQQQQQFields that can be edited through the point-and-click capability of themouse.Menus that provide a quick and easy alternative to the keyboard.Resize and drag capabilities that allow you to define window size and locationand to view as much information as you need.Smart displays that reconfigure the format of displayed data to fit windowsize and shape.Highlighted fields whenever program execution changes the field values.A command that allows you to save the screen configurations.Eight types of windows for debugging and configuring an environment.The windows can be in one of the modes described above or can be in anyuser-defined combination of up to 120 windows. The windows providedare the same as the simulator, shown in Figure B-2, and includea) Command Window for entering commands and displaying outputand error messages.b) Memory Window for displaying, viewing, and editing contents ofmemory.c) Disassembly Window for displaying disassembled code.d) File Window for displaying the contents of any text file.e) CPU Window for displaying, viewing, and editing the CPU registers.f) Calls Window for displaying the current function call that a C programhas made.8-10Development Support/Part Order Information
TMS320C3x Uel/eIC'Dm'enrg) Watch Window for displaying values of selected variables, registers,or other C expressions.h) Display Windows for displaying all field elements of a selected structureor array.8.1.7 Hewlett-Packard 64700 Analysis SubsystemThe HP 64700 TMS320C30 Analysis Subsystem is an analysis tool that canbe used with the TMS320C30 XDS500/1000 emulators to captureTMS320C30 bus cycle information in real time. The subsystem collects tracesamples during a bus cycle and stores them into a trace buffer, which can beviewed for analysis and debugging.An enhanced version of the TI user-friendly, windowed C/Assembly SourceLevel Debugger (the current emulator interface) is included with the subsystem.The debugger's basic feature set has been extended with additional windowsand commands to provide access to the logic analysis capabilities of thesubsystem.The analysis subsystem features are integrated into the window-driven C/assemblysource debugger. This means the currentTMS320C30 developer doesnot need to learn a new interface or new software to take advantage of the subsystem'senhanced feature set. The interface utilizes the debugger's symboltable information so that trace information can be displayed in either assembly,C, or both simultaneously, further reducing debug time.The key features of the HP 64700 Subsystem include[J Hardware breakpoints[J Selectable tracing on the primary or expansion bus[J Up to 1 024-deep trace buffer[J Two-deep prestore buffer[J Flexible triggeringa Complete timing analysis[J Comprehensive display[J Action on external signals8-11
TMS320C3x De\/e/C'Dment8.1.8 TMS320 Third PartiesThe TMS320 family is supported by product and service offerings from morethan 100 independent vendors and consultants, known as third parties. Thesesupport products take various forms (both software and hardware) from crossassemblers,simulators, and DSP utility packages to logic analyzers and emulators.The expertise of those involved in support services ranges from speechencoding and vector quantization to software/hardware design and systemanalysis.For a more detailed description of services and products offered by third parties,referto the TMS320 Third Party Support Reference Guide (literature numberSPRU052). Call the Customer Response Center at 800-336-5236 to requesta copy.8-12Development Support/Part Order Information
TMS320 Literature/OSP Hotline/Bulletin Board ServicesB.2 TMS320 Literature/DSP Hotline/Bulletin Board ServicesExtensive DSP documentation is available; this includes data sheets, user'sguides, and application reports. In addition, D8P textbooks that aid researchand education have been published by Prentice-Hall, John Wiley and Sons,and Computer Science Press. To order literature or to subscribe to the DSPnewsletter "Details on Signal Processing" (for up-to-date information on newproducts and services), call the TI Customer Response Center (CRC) at (800)336-5236.For answers to TMS320 technical questions on device problems, developmenttools, documentation, upgrades, and new products, call the TI DSP Hotline at(713) 274-2320 Monday-Friday from 8:00 a.m. to 6:00 p.m. central time. Toask about third-party applications and algorithm development packages, contactthe third party directly. Refer to the TMS320 Third-Party Support ReferenceGuide (SPRU052) for addresses and phone numbers.For information onQ TMS320 devices,QQSpecification updates for current or new devices and development tools,Development tool and silicon revisions and enhancements,a New DSP application software as it becomes available, andQSource code from the TMS320C3x User's Guide,call the TMS320 DSP Bulletin Board Service (BB8). You can access this telephone-linecomputer service by dialing (713) 274-2323 on a 300-, 1200-, or2400-bps modem. To find out more about the BBS, look in the TMS320 FamilyDevelopment Support Reference Guide (literature number SPRU011 8).Contact the nearest TI Field Sales Office for prices and availability of TMS320devices and support tools. See the list of sales offices and distributors at theend of this book.8-13
TMS320C3x Part Order Information8.4 TMS320C3x Part Order InformationThis section provides the device and support tool part numbers. Table B-1 liststhe part numbers for the TMS320C30 and TMS320C31, and Table B-2 givesordering information forTMS320C3x hardware and software support tools. Anexplanation of the TMS320 family device and development support tool prefixand suffix designators follows the two tables to assist in understanding theTMS320 product numbering system.Table 8-1. TMS320C3x Digital Signal Processor Part NumbersOperating Package Typical PowerDevice Technology Frequency Type DissipationTMS320C30GBl 1.0-llm CMOS 33 MHz Ceramic 181-pin PGA 1.00WTMS320C30GBl27 1.0-llm CMOS 27 MHz Ceramic 181-pin PGA 0.88WTMS320C30GBL40 1.0-llm CMOS 40 MHz Ceramic 188-pin PGA 1.25WTMS320C31 PQl O.8-llm CMOS 33 MHz Plastic 132-pin QFP 0.75WTMS320C31 PQl27 O.8-llm CMOS 27 MHz Plastic 132-pin QFP O.63WSMJ320C30GBM28 1.0-llm CMOS Ceramic 181-pin PGA 1.00WSMJ320C30HUM2828 MHzor Ceramic 196-pin QFP 1.00WSMJ320C30HTM28SMJ320C30GBM25 1.0-llm CMOS Ceramic 181-pin PGA 1.00WSMJ320C30HUM2525 MHzor Ceramic 196-pin QFP 1.00WSMJ320C30HTM25Table 8-2. TMS320C3x Support Tool Part NumbersTool Description Operating System Part NumberSoftwareC Compiler & Macro Assembler/ Linker VAXVMS TMDS3243255-08PC-DOS/MS-DOSTMDS3243855-02SUNUNIXtTMDS3243555-08VAX UltrixTMDS3243265-08MAC-MPWTMDS3243565-01Evaluation Module (EVM) PC-DOS/MS-DOS TMDX3260030HP Trace Analyzer PC-DOS/MS-DOS TMDX326HP30t Note that SUN UNIX supports TMS320C3x software tools on the 68000 family-based SUN-3 seriesworkstations and on the SUN-4 series machines that use the SPARC processor, but not on theSUN-386i series of workstations.:t: SPOX is currently packaged with XDS1000 Development Environment.8-15
TMS320C3x Part Order InformationTable 8-2.TMS320C3x Support Tool Part Numbers (Concluded)Tool Description Operating System . Part NumberSoftware (Concluded)Macro Assembler/Linker VAX VMS TMDS3243250-08PC-DOS/MS-DOS; OS/2 TMDS3243850-02SUNUNIXtTMDS3243550-08MAC-MPWTMDS3243560-01Operating System (SPOX) PC-DOS/MS-DOS :j: Offered by SpectronInc. (805) 967-0503Simulator VAX VMS TMDS3243261·08PC-DOS/MS-DOSTMDS3243851-02SUN UNIXtTMDS3243551-09HardwareXDS500 Emulator PC/MS-DOS TMDS3260131XDS1000 Development Environment PC/MS-DOS TMDS3261 030t Note that SUN UNIX supports TMS320C3x software tools on the 68000 family-based SUN-3 seriesworkstations and on the SUN-4 series machines that use the SPARC processor, but not onthe SUN-386i series of workstations.:j: SPOX is currently packaged with XDS1000 Development Environment.8.4.1 Device and Development Support Tool Prefix DesignatorsPrefixes to Texas Instruments' part numbers designate phases in the product'sdevelopment stage.for both devices and support tools, as shown in the followingdefinitions: .Device Development Evolutionary Flow:TMXTMPTMSExperimental device that is not necessarily representative of the finaldevice's electrical specifications.Final silicon die that conforms to the device's electrical specificationsbut has not completed quality and reliability verification.Fully qualified production device.Support Tool Development Evolutionary Flow:TMDX Development su pport product that has not yet completed Texas Instruments'internal qualification testing for development systems.TMDS Fully qualified development support product.TMX and TMP devices and TMDX development support tools are shipped withthe following disclaimer:"Developmental product is intended for internal evaluation purposes."8-16Development Support/Part Order Information
TMS320C3x Part Order InformationNote:Prototype DevicesTexas Instruments recommends that prototype devices (TMX orTMP) not beused in production systems because their expected end-use failure rate isundefined but predicted to be greater than standard qualified production devices.TMS devices and TMDS development support tools have been fully characterized,and their quality and reliability have been fully demonstrated. Texas Instruments'standard warranty applies to TMS devices and TMDS developmentsupport tools.TMDX development support products are intended for internal evaluation purposesonly. They are covered by Texas Instruments' Warranty and UpdatePolicy for Microprocessor Development Systems products; however, theyshould be used by customers only with the understanding that they are developmentalin nature.B-17
TMS320C3x Part Order Information8.4.2 Device SuffixesFigure 8-5. TMS320 Device NomenclatureThe suffix indicates the package type (e.g., N, FN, or G8) and temperaturerange (e.g., L).Figure 8-5 presents a legend for reading the complete device name for anyTMS320 family member.Prefix ____--'1TMX::: Experimental DeviceTMP = Prototype DeviceTMS = Qualified DeviceSMJ = MIL-STD-883CTMS 320 C 30 GB Ll Temperature RangeH = 0 to 50°CL 0 to 70°CS -55 to 100°CM = -55 to 125°CA = -40 to 85°CDevice Family------'320 = TMS320 FamilyTechnology---------'C = CMOSE = CMOS EPROMNo Letter = NMOSDevice -------------'1 st-generation DSP:10141516172nd-generation DSP:2025263rd-generation DSP:30314th-generation DSP:405th-generation DSP:5051'---- Package TypeN = Plastic DIPJD = Ceramic DIP Side-BrazedFN = Plastic Leaded CCGB = Ceramic PGAFJ = Ceramic Leaded CCFD ::: Leadless Ceramic CCFZ = Ceramic Leaded CCGE = Ceramic PGA, Glass SealHU = Ceramic quad f1atpackHT ::: Ceramic quad flatpack(gull wing)PQ ::: Plastic quad flatpack8-18Development Support/Part Order Information
.. ' ~----------------------------------------------------------------.. IQuality and Reliability
________________ Q_U_8_lit_y_8_n_d_R_e_Ii_8_bi_li_ty ___---'
Chapter CQuality and Reliability~;:;:::~~~~::~;:~~::~::~::::~~;:~~::~~m~::::~::::::~~~;:~~~;:~~~~::~~~::~~~::~~~~~~:;::~~::~~~~~~~~~~~~~~::~~::~::~~~~::~~;:~~::~~:~~~~~~~~::~~::~~~::::~::::~::~;:::~::~~~~:~~~~:~~~~~:;;~::~:;~~~::~~m::~~::~;:~~~~::~:: ::::::::~::::::::::::::::::::::::::::~:i~~::::~~::~;:~~~~~~:.:~~~~~~~~~~~~~::~::~::~::::~~~~~::~::::~~::~::::m::::~::~:::i~::~::~~::;:::~~~::~~~~~m~::~~~::~~::~::~ ~::::~~~~::~~~:i~:i~;:::~:;::~~~:;~::~~:::::~~~::~~~~: :~::::~~~::::The quality and reliability of Texas Instruments microprocessor andmicrocontroller products, which include TMS320 digital signal processors, relieson feedback froma Our customers,a Our total manufacturing operation from front-end wafer fabrication to finalshipping inspection, anda , Product quality and reliability monitoring.Our customer's perception of quality is the governing criterion for judging performance.This concept is the basis for Texas Instruments Corporate QualityPolicy, which is as follows:"For every product or service we offer, we shall define the requirements thatsolve the customer's problems, and we shall conform to those requirementswithout exception."Texas Instruments has developed a leadership reliability qualification system,based on years of experience with leading-edge memory technology and onyears of research into customer requirements. In orderto achieve constant improvement,programs that support that system respond to customer input andinternal information.C-1
Reliability Stress TestsC.1 Reliability Stress TestsAccelerated stress tests are performed on new semiconductor products andprocess changes in order to qualify them and to ensure excellence in productreliability. These test environments are typical:QQQQHigh-temperature operating lifeStorage lifeTemperature cyclingBiased humiditya AutoclaveQQElectrostatic dischargePackage integritya Electromigrationa Channel-hot electrons (performed on geometries less than 2.0 11m).Typical events or changes that require internal requalification of a product includea New die design, shrink, or layoutQWafer process (baseline/control systems, flow, mask, chemicals, gases,dopants, passivation, or metal systems)a Packaging assembly (baseline control systems or critical assembly equipment)QQPiece parts (such as lead frame, mold compound, mount material, bondwire, or lead finish)Manufacturing siteTI reliability control systems extend beyond qualification. Total reliability controlsand management include product reliability monitoring as well as finalproduct release controls. MaS memories, utilizing high-density active elements,serve as the leading indicator in wafer-process integrity at TI MaS fabricationsites, enhancing all MaS logic device yields and reliability. TI placesmore than several thousand MaS devices per month on reliability tests to ensureand sustain built-in product excellence.Table C-1 lists the microprocessor and microcontroller reliability tests, the durationof the test, and sample size. Definitions and descriptions of those testsprecede the table.C-2Quality and Reliability
Reliability Stress TestsAOQ (Average Outgoing Quality)FIT (Failure In Time)Operating UfetestHigh-Temperature StorageBiased HumidityAutoclave (Pressure Cooker)Temperature CycleElectrostatic DischargeThermal ShockPIND(Particle Impact NoiseDetection)Amount of defective product in a population, usuallyexpressed in terms of parts per million (PPM).Estimated field failure rate in number of failures perbillion power-on device hours; 1000 FITS equal 0.1percent failure per 1000 device hours.Device dynamically exercised at a high ambienttemperature (usually 125°C) to simulate fieldusage that would expose the device to a much lowerambient temperature (such as 55°C). Using aderived high temperature, a 55°C ambient failurerate can be calculated.Device exposed to 150°C unbiased condition.Bond integrity is stressed in this environment.Moisture and bias used to accelerate corrosiontypefailures in plastic packages. Conditions include85°C ambient temperature with 85 percent relativehumidity (RH). Typical bias voltage is +5 V and isgrounded on alternating pins.Plastic-packaged devices exposed to moisture at121°C using a pressure of one atmosphere abovenormal pressure. The pressure forces moisturepermeation of the package and accelerates corrosionmechanisms (if present) on the device. Externalpackage contaminants can also be activatedand caused to generate inter-pin current leakagepaths.Device exposed to severe temperature extremes inan alternating fashion (-65°C for 15 minutes and150°C for 15 minutes per cycle) for at least 1000cycles. Package strength, bond quality, and consistencyof assembly process are tested in this environment.Device exposed to electrostatic discharge pulses.Calibration is according to MIL STD 883C, method3015.6. Devices are stressed to determine failurethreshold of the design.Test similarto the temperature cycle test, but involvinga liquid-to-liquid transfer, per MIL-STD-883C,Method 1011.A nondestructive test to detect loose particlesinside a device cavity.Mechanical Sequence:Fine and gross leakMechanical shockPIND (optional)Per MIL-STD-883C, Method 1014Per MIL-STD-883C, Method 2002,1500 g, 0.5 ms, Condition BPer MIL-STD-883C, Method 2020 'C-3
Reliability Stress Tests'~~"".~ ••••• ~.~; •••• ~ ••• ~ ••••• :.:;:;:.: •• ~.:.:.:.:.:·:·:·:::::··;:::.:.:.:.:.·.·.·.·.·.·8:.:.·;::::.:;:;:.:;:.·.·8·.:.:.:.~:;:.:.·;:;:.:'·;~:;·.:.·.:.·;·.~·.:.:;·8·.·...·;..·.:.·.·...•... :;·.·.:;·;~~.. y;:;:;~~·;!> :;.;.....;........'......,:•••••••••••••:....,..:...................:.~•••;•••••••;....., •• o; .....................;.................... 0; ...........................................;.................................................................................... o; .........;................................................ ~ .............. ~ .... ~~~ .. ~ .. o;~ .......;o;:oVibration, variable frequencyConstant accelerationFine and gross leakElectrical testThermal Sequence:Fine and gross leakSolder heat (optional)Temperature cycle(10 cycles minimumThermal shock(10 cycles minimum)Moisture resistanceFine and gross leakElectrical testThermal/Mechanical Sequence:Fine and gross leakTemperature cycle(10 cycles minimum)Constant accelerationFine and gross leakElectrical testElectrostatic dischargeSolderabilitySolder heatSalt atmosphereLead pullLead integrityElectromigrationResistance to solventsPer MIL-STD-883C, Method 2007,20 g, Condition APer MIL-STD-883C, Method 2001,20 kg, Condition 0, Y1 Plane minPer MIL-STD-883C, Method 1014To data sheet limitsPer MIL-STD-883C, Method 1014Per MIL-STD-750C, Method 1014Per MIL-STD-883C, Method 1010,- 65 to + 150 ec, Condition CPer MIL-STD-883C, Method 1011,- 55to + 125 ec, Condition 8Per MIL-STD-883C, Method 1004Per MIL-STD-883C, Method 1014To data sheet limitsPer MIL-STD-883C, Method 1014Per MIL-STD-883C, Method 1010,- 65 to + 150 ec, Condition CPer MIL-STD-883C, Method 2001,30 kg, Y1 PlanePer MIL-STD-883C, Method 1014To data sheet limitsPer MIL-STD-883C, Method 3015Per MIL-STD-883C, Method 2033Per MIL-STD-750C, Method 2031,10 secPer MIL-STD~883C, Method 1009,Condition A, 24 hrs minPer MIL-STD-883C, Method 2004,Condition APer MIL-STD-883C, Method 2004,Condition B 1Accelerated stress testing of conductorpatterns to ensure acceptable lifetime ofpower-on operationPer MIL-STD-883C, Method 2015C-4Quality and Reliability
Reliability Stress Tests:x:::s:."!O::-;:;:.;:;:;:;:;::s...:::;.... :;:;:;::>:;x:s:;::>:;::::x::-::x:~::::,;:::;:;..-;:O:;:.. ~:::::OSY.::;:O:::::::::::;:;::::~zm;s.:;:;:;,;:i:;:::::a:;:::>:i:;:.::;~:;.. ..:::;):.:,::>.,... ~;::::::::::x.;::XO:;:;:;:w::::~:::::::.::::>~:::;:.::::;:::::::::;:::::;:;::::x.:::::s:;::::::sm;S$S:~s:;:~::O;' ...::s:::::;::Y.::~:::::::;:;:;>::::::"y';*;*::;::"'::·;-;::';~"s:;::m)S%::Y.>::Y.;::>Y-.:i:>'~::Y.i:OSS:;~:::::'Q::,:>%m::Y.>~:'"X:WYh:M>:::;Ss.
Reliability Stress TestsTable C-2. TMS320C3x TransistorsTable C-2 lists the TMS320C3x devices, the approximate number of transistors,and the equivalent gates. The numbers have been determined from designv~rification runs.Device # Transistors # GatesCMOS: TMS320C30 600K-700K 200KCMOS: TMS320C31 SOOK-600K 100KNote:Texas Instruments reserves the right to make changes in MOS Semiconductortest limits, procedures, or processing without notice. Unless prior arrangementsfor notification have been made, TI advises all customers to reverifycurrent test and manufacturing conditions prior to relying on publisheddata.C-6Quality and Reliability
~ _____ C_a_l_c_ul_a_ti_o_n_O_f_T_M_S_3_2_0_C_3_0_P_o_w_e_r_D_is_s_ip_a_t_io_n _______________' __ 11III
.Calculation of TMS320C30 Power Dissipation~----------------------------------~
Appendix DCalculation of TMS320C30 Power Dissipation:;:;:;:::::::;:::;:::,::;:::::::;:;:;:::;:::;:::;:::;:;:;:;:;:;=;:;:;":;=;:;:::::::;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:i:;:::::::;:;:;;;:::;:;:;:;:;:::::::::::::;:;:;:::::;:;:;:;:;:;:;:;:;::;::;:::::;::::: .... ;:::;:;:;:;:;:;:;:::::::}f:;::::;:·:::::::::;:::::;··"··········· ... :.:.:::::::.:::;::::;::::::::;::::::::::~::::::::: .. :.:.:.;.;.;.;.:.:.;.;.;.;.;.;;;:;;:::;::;::::; ............. , ',' ........................... :::;:::::::::::::::::;;::;:;::;;:;:;:;::::::::::~::::::::::::::::::;:::::::;::::::;:::::;:::::::::;:::;:::::::;:;:;"'::;:;:;:;:;:;:::.::;:;:;:;:.;.;.;;:.:.:.;:!.:.;.;The TMS320C30 is a state-of-the-art, high-performance, 32-bit floating-pointDSP microprocessor fabricated in CMOS technology. This device is the firstmember of the third generation of TMS320 family single-chip DSP microprocessors.Since 1982 when the first-generation TMS3201 0 was introduced, theTMS320 family has established itself as the industry standard for digital signalprocessing. The TMS320C30's innovative architecture and specialized instructionset provide high speed and increased flexibility for DSP applications.This combination makes it possible to execute upto 40 MFLOPS (million floatingpoint operations per second).As device sophistication and levels of integration increase with evolving semiconductortechnologies, actual levels of power dissipation vary widely and dependheavily on the particular application in which the device is used and thenature of the program being executed. In addition, due to the inherent characteristicsof CMOS technology, power requirements vary according to clockrates and data values being processed.This application report presents the information necessary to determineTMS320C30 power supply current requirements under different operatingconditions. With this information, you can determine the power dissipation forthe device, which, in turn, you can use to calculate thermal management requirements.The major topics discussed in this application report are as follows:QQFundamental Power Dissipation Characteristics• Components of Power Supply Current Requirements• Dependencies• Test Setup DescriptionCurrent Requirement of Internal Circuitry• Quiescent• Internal Operations• Internal Bus OperationsQ Current Requirement of Output Driver Circuitry0-1
Introduction• Primary Bus• Expansion Bus• Data Dependency• Capacitive Load DependenceQCalculation of Total Supply Current• Combining Supply Current Due to <strong>Al</strong>l ComponentsISSupply Voltage, Operating Frequency, and Temperature Dependencies• Design Equation• Peak Versus Average Current• Thermal Management ConsiderationsQExample Supply Current CalculationsD-2Calculation of TMS320C30 Power Dissipation
Fundamental Power Dissipation CharacteristicsD.1 Fundamental Power Dissipation CharacteristicsTypically, an IC's (integrated circuit) power specification is expressed as afunction of operating frequency, supply voltage, operating temperature, andoutput load. As devices become more complex, the specification must also bebased on device functionality. CMOS devices inherently draw current only duringswitching through the linear region. Therefore, the power supply current isrelated to the rate of switching. Furthermore, since the output drivers of theTMS320C30 are specified to drive DC loads, the power supply current resultingfrom external writes depends not only on switching rate but also on the valueof data written.D.1.1Components of Power Supply Current RequirementsThere are four basic components of the power supply current:Q QuiescentQQQInternal OperationsInternal Bus OperationsExternal Bus Operations0.1.2 DependenciesThe power supply current consumption depends on many factors. Four aresystem related:QQQQOperating frequencySupply voltageOperating temperatureOutput loadand several others are related to TMS320C30 operation:QQDuty cycle of operationsNumber of buses usedQ Wait statesQQCache usageData valueThe total power supply current for the device is described in an equation applyingthe four basic power supply current components and the dependencies describedabove. This equation is as follows:0-3
Fundamental PowerCharacteristicsI = (Iq + liOPS + libUS + I xbus) x FV x TwhereIqliopslibusIxbusFVTis the quiescent current component,is the current component due to internal operations,is the current component due to internal bus usage including data valueand cycle time dependencies,is the current component due to external bus usage including datavalue, wait state, cycle time, and capacitive load dependencies,is a scale factor for frequency and supply voltage, andis a scale factor for operating temperature.Application of this equation and determination of all the dependencies are de-'scribed in detail in this application report.While this document explains, in detail, howtodeterminethe powersupplycurrentrequirement for the TMS320C30, if a less detailed analysis is sufficient,the minimum, typical, and maximum values can be used to determine a roughestimate of the power supply current requirements. The minimum power supplycurrent requirement is 110 mAo The typical and average current consumptionis 250 mA as described in the TMS320C30 data sheet and will be associatedwith most algorithms running on the device unless excessive data outputis being performed.:-rh~.l-J~iirrt~I11C~rr~l1t·reql1ireme~t··is 600 mA·and·occ~r~~l1lyU.i2
Fundamental Power Dis~sioa~tion CharacteristicsFigure D-1. Current Measurement Test SetupCY7C186-25PCSRAMTektronixCurrent Probe(P6042)2.15 V VDD2.15 VR = 825 QTMS320C3032 D-----+---'2O'=4~A-r---I Primary ExpansionR = 825 Q32 D13 ACr rC0.1.3 Determining <strong>Al</strong>gorithm PartitioningEach part of an algorithm behaves differently, depending on its internal and externalbus usage. To analyze the power supply current requirement, you mustpartition an algorithm into segments with distinct concentrations of internal orexternal bus usage. The analysis that follows is applied to each distinct programsegment to determine the power supply current requirement for that section.The average power supply current requirement can then be calculatedfrom the requirements of each segment of the algorithm.0.1.4 Test Setup Description<strong>Al</strong>l TMS320C30 supply current measurements were performed on the test setupshown in Figure 0-1. The test setup consists of a TMS320C30, 8K of zerowait-state Cypress Semiconductor SRAMs (CY7C186-25PC), and RC loadson all data and address lines. A Tektronix Current Probe (P6042) measures thepower supply current in all Voo lines of the device. The supply voltage on theoutput load is 2.15 V. Unless otherwise specified, all measurements are madeat a supply voltage of 5.0 V, an input clock frequency of 33 MHz, a capacitiveload of 80 pF, and an operating temperature of 25°C.0-5
Current0.2 Current Requirement of Internal CircuitryThe power supply current requirement for internal circuitry consists of threecomponents: quiescent, internal operations, and internal bus operations.Quiescent and internal operations are constants, but the internal bus operationscomponent varies with the rate of internal bus usage and the data valuesbeing transferred.D.2.1QuiescentQuiescent refers to the baseline supply current drawn by the TMS320C30 duringminimal internal activity, such as executing the IDLE instruction or branchingto self. It includes the current required to fetch an instruction from on- oroff-chip memory. The quiescent requirement for the TMS320C30 is 110 rnA.Examples of quiescent current include:a Maintaining timers and serial portsa Executing the IDLE instructionQTMS320C30 in HOLD mode pending external bus accessQ TMS320C30 in resetQBranching to selfD.2.2 Internal OperationsInternal operations are those that require more current than quiescent activitybut do not include external bus usage or significant internal bus usage. Internaloperations include register-to-register multiplication, ALU operations, andbranches. They add a constant 55 rnA above the quiescent so that the totalcontribution of quiescent and internal operations is 165 rnA. Note, however,that internal and/or external bus operations executed via an RPTS instructiondo not contribute an internal operations power supply current component andhence do not add 55 rnA to quiescent current. During an instruction in RPTS,activity other than the instruction being repeated is suspended; therefore, powersupply current is related only to the operation performed by the instructionbeing executed. The next contributing factor to the power supply current requirementis internal bus operations.0-6Calculation of TMS320C30 Power Dissipation
Current Requirement of Internal0.2.3 Internal Bus OperationsThe internal bus operations include all operations that utilize the internal busesextensively, such as accessing internal RAM every cycle. No distinction ismade between internal reads (such as instruction or operand fetches from internalROM or internal RAM banks) and internal writes (such as operand storesto internal RAM banks), because internally they are equal. Significant use ofinternal buses adds a term to the power supply current requirement that is datadependent. Recall that switching requires more current. Hence, movingchanging data at high rates requires higher power supply current.Pipeline conflicts, use of cache, fetches from external wait-state memory, andwrites to external wait-state memory all effect the internal and external buscycles of an algorithm executing on the TMS320C30. Therefore, the internalbus usage of the algorithm must be determined in order to accurately calculatepower supply current requirements. The TMS320C30 software simulator andXOS emulator both provide benchmarking and timing capabilities that allowbus usage to be determined.The current resulting from internal bus usage varies roughly exponentially withtransfer rates. Figure 0-2 shows internal bus current requirements for transferringalternating data (AAAAAAAAh to 55555555h) at several transfer rates(expressed as the transfer cycle time). A transfer rate less than one impliesmultiple accesses per single H1 cycle (that is, using OMA, etc.). Transfer cycletimes greater than one refer to single-cycle transfers with one or more cyclesbetween them. The minimum transfer cycle time is one third, which correspondsto three accesses in a single H1 cycle.The data set AAAAAAAAh to 55555555h exhibits the maximum current forthese types of operations. Less current is required for transferring other datapatterns, and current values may be derated accordingly as described later inthis subsection.As the transfer rate decreases (that is, transfer cycle time increases) the incrementallooapproaches 0 mAo Transfer rates corresponding to more than 7 H1cycles do not add any current and are considered insignificant. This figure representsthe incremental 100 due to internal bus operations and is added toquiescent and internal operations current values.For example, the maximum transfer rate corresponds to three accesses everycycle or one-third H1 transfer cycle time. At this rate, 85 mA is added to thequiescent (110 mA) and internal operation (55 mA) current values for a totalof 250 mAo0-7
Current #-Jo/"Y"i,"orTIontFigure D-2. Internal Bus Current Versus Transfer Rate
Current Requirement of InternalFigure 0-3. Internal Bus Current Versus Data Complexity Derating CurvecC"t:I1.21Q)0.8.!:!!mE10.0z 0.60.4Internal Bus Data DependencyIr 'Os-Fs I I I 'AS-5S~<strong>Al</strong>ternating Data.,~'--- ,OS-Oj,Same Data- /FS-FsJo 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1Relative Data Complexity0-9
0.3 Current Requirement of Output Driver CircuitryThe output driver circuits on the TMS320C30 are required to drive significantlyhigher DC and capacitive loads than internal device logic. Therefore, they aredesigned to drive larger currents than internal devices. Because of this, outputdrivers impose higher supply current requirements than other sections of circuitryon the device.Accordingly, the highest values of supply current are exhibited when externalwrites are being performed at high speed. During reads, or when the externalbuses are not being used, the TMS320C30 is not driving the data bus; this eliminatesthe most significant component of output buffer current. Furthermore,in typical cases, only a few address lines are changing, or the whole addressbus is static. Under these conditions, an insignificant amount of supply currentis consumed. Therefore, when no external writes are being performed or whenwrites are performed infrequently, current due to output buffer circuitry can beignored.When external writes are being performed, the current required to supply the. output buffers depends on several different considerations. As with internalbus operations, current required for output drivers depends on the data beingtransferred and the rate at which transfers are being made. Additionally, outputdriver current requirements depend on the number of wait states implemented,because wait states affect rates at which bus signals switch. Finally, currentvalues are also dependent upon external bus DC and capacitive loading.External operations involve writes external to the device ·and constitute the majorpower supply current component. The power supply current for the externalbuses is made up of three components and is summarized in the followingequation:Ibase + Iprim + lexpwhereIbase = 60-mA baseline current component,prim is the primary bus current component,lexp is the expansion bus current component.The remainder of this section describes in detail the calculation of external buscurrent components.0-10Calculation of TMS320C30 Power Dissipation
Current Requirement of Output Driver Circuitry0.3.1 Primary BusThe current due to primary bus writes varies roughly exponentially with bothwait states and write cycle time. <strong>Al</strong>so, current components due to output drivercircuitry are represented as offsets from the baseline value. Since the baselinevalue is related to internal current components, negative values for current offsetare obtained under some circumstances. Note, however, that actual negativecurrent does not occur.As mentioned in the previous section, to obtain accurate current values, timingof write cycles on the buses must first be established. This is accomplished byanalyzing program activity, including any pipeline conflicts that may exist, todetermine the rate and timings at which write cycles to the external buses occur.Information from the TMS320C30 emulator or simulator as well as theTMS320C3x User's Guide is used to make these determinations. Note that effectsfrom the use of cache must also be accounted for in these analyses, becauseuse of cache can effect whether or not instructions are fetched from externalmemory.When evaluating external write activity in a given pr9gram segment, a considerationthat must be made is whether or not a particular level of external writeactivity constitutes significant activity. If writes are being performed at a slowenough rate, they do not significantly impact supply current requirements;therefore, current due to external writes can be ignored. This is the case, however,only if writes are being performed at very slow rates on both the primaryand the expansion buses. If writes are being performed at high speed on onlyone of the two external buses, the approach described in this section shouldstill be used for calculation of current requirements.Note that although negative incremental current values are obtained undersome circumstances, the total contribution for external buses, including baselinecurrent, must always be positive. This is because, when external buses areused minimally, total current requirements always approach the current contributiondue to internal components, which is solely a function of internal activity.This places a lower limit on current contributions resulting from the primary andexpansion buses, because the total current due to external buses is the sumof the 60-mA baseline value and the primary and expansion bus components.This effect is discussed in further detail in the rest of this subsection.When bus-write cycle timing has been established, Figure 0-4 can be usedto determine the contribution to supply current due to this bus activity.Figure Q-4 shows values of current contribution from the primary bus for variousnumbers of wait states and H1 cycles between writes. These characteristicsare exhibited when writes of alternating 55555555h and AAAAAAAAh arebeing performed at a capacitive load of 80 pF per output signal line. The conditionsexhibit the highest current values on the device. The values presentedin the figure represent incremental or additional current contributed by the primarybus output driver circuitry under the given conditions. Current values ob-0-11
Current Requirement of Output DriverFigure D-5. Primary Bus Current Versus Transfer Rate at Zero Wait States
CurrentDriver CircuitryFigure 0-4 and Figure 0-5 showthatthecontribution of writes for external busactivities becomes insignificant if writes are being performed with more than18 cycles between each write. Under these conditions, the incremental valueof -30-mA current contribution due to the primary bus should be used. Note,however, that a value of -30 mA should be used only if the expansion bus isbeing used extensively, because the total contribution for external buses includingbaseline current must always be positive. If the expansion bus is notbeing used and the primary bus is being used minimally, the current contributiondue to the primary bus must always be greater than or equal to 20 mAo Thisensures that the correct total current value is obtained when summing externalbus components. Once a current value has been obtained from Figure 0-4 orFigure 0-5, this value may be scaled by a data dependency factor if necessary,as described at the end of this section. This scaled value is then summedalong with several other current terms to determine the total supply current.Calculation of total supply current is described in detail in the next section.0.3.2 Expansion BusCurrents due to the primary and expansion buses are similar in characteristicsbut differ slightly because of several factors, including the fact that the expansionbus has 11 fewer address outputs than the primary bus (13 ratherthan 24).This difference is exhibited in a slightly lower overall current contribution fromthe expansion bus than from the primary bus.Accordingly, determining expansion bus current follows the same basic premisesas determining the the primary bus current. Figure 0-6 and Figure 0-7show the same current relationships for the expansion bus as Figure 0-4 andFigure 0-5 show for the primary bus. <strong>Al</strong>so, since the total external buses' currentcontribution must be positive, if the primary bus is not being used and theexpansion bus is being used minimally, then the minimum current contributiondue to the expansion bus is -30 mAo Finally, as with the primary bus, currentvalues obtained from these figures may require scaling by a data dependencyfactor as described in the next subsection.0-14Calculation of TMS320C30 Power Dissipation
Current Requirement of Output Driver CircuitryFigure D-9. Expansion Bus Current Versus Data Complexity Derating CurveExpansion Bus Data Dependency [80 pF]1r---r---~--~--~--~--'---cC"CCI,).!:::!mEI-oZ0.55 L...-__ "--__..L..-__..I-..__...I...-__...L-__...J......__...J......__...I.-__--I-__--'o 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1Data Complexity0.3.4 Capacitive Load DependenceOnce cycle timing and data dependencies have been accounted for, capacitiveloading effects should be included in a similar mannerto that of data dependency.Figure 0-10 shows the scale factor to be applied to the current values obtainedabove as a function of actual load capacitance if the load capacitancepresented to the buses is less than 80 pF.In the previous example, if the load capacitance is 20 pF instead of 80 pF, ascale factor of 0.84 is used, yielding:Primary:Expansion:0.84 x 68 mA = 57.12 mA0.84 x 34 mA = 28.56 mAThe slope of the load capacitance line in Figure 0-10 is 0.26% normalized 100per pF. While this slope may be used to interpolate scale factors for loads greaterthan 80 pF, the TMS320C30 is specified to drive output loads less than 80pF, and interface timings cannot be guaranteed at higher loads. With data dependencyand capacitive load scale factors applied to the current values forprimary and expansion buses, the total supply current required for the devicefor a particu.lar application can be calculated, as described in the next section.0-17
Current Requirement of Output Driver Circuitry::::~::;:;:;:.:;:;:::;:;:;:;.;:::;:;:;:::;:::;:;:;:;:;:;:::::.:::;:::;:::
Calculation of TotalCurrent0.4 Calculation of Total Supply CurrentThe previous sections have discussed currents contributed by several differentsources on the TMS320C30. Because determinations of actual current valuesare unique and independent for each source, each current source was discussedseparately. In an actual application, however, the sum of the independentcontributions from each current determines the total current requirementfor the device. This total current value is exhibited as the total current suppliedto the device through all of the Voo inputs and returned through the Vss connections.Note that numerous Voo and VSS pins on the device are routed to a varietyof internal connections, not all of which are common. Externally, however, allof these pins should be connected in parallel to 5 V and ground planes, respectively,with as low impedance as possible.As mentioned previously, because different program segments inherently performdifferent operations that are often quite distinct from each other, it is typicallyappropriate to consider current for each of the different segments independently.Once this is done, then peak current requirements are readily obtained.Further, average current calculations can also be made that can beused to determine heating effects of power dissipation. These effects, in turn,can be used to determine thermal management considerations.0.4.1 Combining Supply Current Due to <strong>Al</strong>l ComponentsTo determine the total supply current requirements for any given program activity,calculate each of the appropriate components and combine them in the followingsequence:1) Start with 11 O-mA quiescent current requirement.2) Add 55 mA for internal operations unless the device is dormant, such aswhen executing IDLE, NOPs, or branches-to-self, or performing internaland/or external bus operations using an RPTS instruction (see InternalOperations section). Internal or external bus operations executed viaRPTS do not contribute an internal operations power supply current componentand hence do not add 55 mA to quiescent current. Therefore, currentcomponents in the next two steps may still be required even thoughthe 55 mA is omitted.3) If significant internal bus operations are being performed (see Internal BusOperations section), add the calculated current value.4) If external writes are being performed at high speed (see Current RequirementsDue to Output Driver Circuitry section), add 60 mA and then add thevalues 'calculated for primary and expansion bus current components. Ifonly one external bus is being used, the appropriate incremental currentD-19
Calculation of TotalCurrentfor the unused bus should still be included because the current offsets includecomponents required for operating both buses. Note, however, that,as discussed previously, the total current contribution for external buses,including baseline, must always be positive.The current value resulting from summing these components is the total devicecurrent requirement for a given program activity. '0.4.2 Supply Voltage, Operating Frequency, and Temperature Dependencies.Besides current dependencies that are specific to each of the components ofsupply current discussed earlier, supply voltage level, operating temperatureand operating frequency also affect current requirements. However, theseconsiderations affect the total supply current, not just specific components(that is, internal or external bus operations).,Note that supply voltages, operatingtemperature, and operating frequency must be maintained within requireddevice specifications.In the same manner as data dependencies discussed in other sections, considerationsfor these dependencies are applied as a scale factor. This factor isapplied, once the total current for a particular program segment has been determined.Figure D-11 shows the relative scale factors to be applied to the supplycurrent values as a function of both Voo and operating frequency.Power supply current consumption does not vary significantly with operatingtemperature. However, ifdesired, ascalefactorof2 % normalized 100 per 50°Cchange in operating temperature may be used to derate current within the specifiedrange noted in the TMS320C30 data sheet. This temperature dependenceis shown graphically in Figure D-12. Note that a temperature scale factorof 1.0 corresponds to current values at 25°C, which is the temperature atwhich all other references in the document are made.0-20Calculation of TMS320C30 Power Dissipation
Calculation of TotalCurrentFigure D-11. Current Versus Frequency and Supply Voltage100 Versus f(CLKIN) and Supply Voltage1.2 r----.,----r---.;.--r-----r-----;------r--,Voo = 5.5 V1.1 I----I----t----t---_I_---t----::I~_t Voo = 5.25 V1 Voo = 5.0 V1----I----t----t---_I_--::ii1',c...-~~~=---t~9 Voo = 4.75 VC 0.9cVee = 4.5 V"C(I,).~(ijEJ..oZ0.81----I----t----t-~~~~~~~~~~-t0.7~--+---~-~~~~~~~~~-~-~0.6~--+--~~~~~~~~---+--~-~0.5~--~~~~~~~---+---+--~-~0.4~~~~~~-t----t----I----t--~--t0.3~~~+---4---~-V-o-o-ln+c-re-m-e-nt-s~in-O-.2-5-V~-~0.2 L-__ .l..-__....I..-__....J,....__--'-__--..L.__----L_--'o 5 10 15 20 25 30f(CLKIN) (MHz)Figure D-12. Current Versus Operating Temperature Change1.031.02c 1.01"C(I,).!::! 1(ijEJ..0z0.990.98Operating Temperature Effects"-" "''" .. ~~'-'" "'- "" '"0.97-80 -60 -40 -20 o 20 40 6080Change in Operating Temperature (OC)0-21
Calculation of TotalCurrent0.4.3 Design EquationThe procedure for determining th~ power supply current requirement can besummarized in the following equation:I = (Iq + 'iOPS + 'ibus + 'xbus)x FV' x TwhereIq'iops= 110 mA,= 55 mA,libus = 01 x f1 (see Table 0-1),Ixbuswith= Ibase + prim + 'exp,Ibase = 60 mA,prim = 02 x C2 x f2 (see Table 0-1),'exp = 03 x C3 x f3 (see Table 0-1).FVis the scale factor for frequency and supply voltage, andTis the scale factor for operating temperature.Table 0-1 describes the symbols used in the power supply current equation.Furthermore, the table displays the figure number from which the value can beobtained.D-22Calculation of TMS320C30 Power Dissipation
Calculation of Total Supply Current~::.::.~;:.::.~~:.;:.::.~~"!-~~:,;:.;:=:::-~::;:~~:.'):::::::-::-:::;::::-:::-,:~::::.:~~:~ ..,:::~:::!:-:.,::::!::.~~~-:.::~:::::~,:::;:.::::.,:::::~:.::.~:::::::::.,:;:.,:~:.,::~... ~::::-,::!::::::.,::}~~:,;:.:::~:::=:::::=:::::::::::;::::::.~::::.,:::::::::~,:::;:::;:;:::;:::;,;::::::::::::,;:::-,:;:::::::::;:.:::::.::::::::;';:.:.::;:.~;:-,:::.:::.:'::'~:;:;>;:;:').).':;:;:;::';:::;:=:::;*.:'~·::;::::v.;·:.... ·:·::=~:;·:::.. ~;o~:;·::.::::·.:::: ..:.s:;·:..:.::.::,:s,;:;:=:,::,::.:,::::,:,:::,::s::::·;:::;:::::;:.:::::::':"!>~:;:.:::.', .. '.":":'. '.. ... >:' ' ..'.. .',~/':-:.••,'.'.. :.>:lnt~rl1;;tl8~~()per~ti()l1sGurrenL : '.'.' ': ., .....:., :..:•.,'." ,.'.,.,D1 Internal Bus Oata Scale Factor Figure 0-3'1 Internal Bus Current Requirement Figure 0-2"',', ..•• :. :·'·'· ••.• ~#erl1aJBus()p~r~tiorl~.Gurre.nt .• :!base External Bus Base Current 60 rnAprimlexpPrimary Bus Operations CurrentD2 Primary Bus Oata Scale Factor Figure 0-8C2 Primary Bus Cap Load Scale Factor Figure 0-10Primary Bus Current Requirement Figure 0-4 or 0-5Expansion Bus Operations CurrentExpansion Bus Oata Scale Factor Figure 0-9Expansion Bus Cap Load Scale Factor Figure 0-10Expansion Bus Current Requirement Figure 0-6 or 0-7,..,... ········>\preq!SuppIY\loltage.Scal:! c:. ••.• »)•••..••....••.•..•..• F;::;~,;;;.b-,..,.".,.,.,.,.,.,"""'.'••···T
Calculation of TotalCurrent0.4.5 Thermal Management ConsiderationsHeating characteristics of the TMS320C30 are dependent upon powerdissipation,which is, in turn, dependent upon power supply current. When makingthermal management calculations, several considerations must be made thatrelate to the manner in which power supply current contributes to power dissipationand to the TMS320C30 package thermal characteristics' time constant.De'pending on sources and destinations of current on the device, some currentcontributions to 100 do not constitute a component of power dissipation at 5volts. Accordingly, if the total current flowing into Voo is used to calculate powerdissipation at 5 volts, erroneously large values for power dissipation will beobtained. Power dissipation is defined as:P = I x V(where P is power, I is current, and V is voltage). If device outputs are drivingany DC load to a logic high level, only a minor contribution is made to powerdissipation because CMOS outputs typically drive to a level within a few tenthsof a volt of the power supply rails. If this is the case, subtract these current componentsout of the total supply current value; then calculate their contributionto power dissipation separately, and add it to the total power dissipation (seeFigure 0-13). If this is not done, these currents resulting from driving a logichigh level into a DC load will cause unrealistically high power dissipation values.The error occurs because the currents resulting from driving a logic highlevel into a DC load will appear as a portion of the current used to calculate. power dissipation due to Voo at 5 volts.Figure 0-13. Load Currents100TMS320C30:lOUTOevice Output Oriven HighISSVOD100TMS320C30 : I 'lOUTDevice Output Driven LowISS0-24 Calculation of TMS320C30 Power Dissipation
Calculation of TotalCurrentFurthermore, external loads draw supply only current when outputs are beingdriven high, because when outputs are in the logic zero state, the device issinking current, which is supplied from an external source. Therefore, the powerdissipation due to this current component will not have a contributionthrough I DO but will contribute to power dissipation with a magnitude of:P = VOLX IOLwhere VOL is the low level output voltage and IOL is the current being sunk bythe output as shown in Figure 0-13. The power dissipation component due tooutputs being driven low should be calculated and added to the total power dissipation.When outputs with DC loads are being switched, the power dissipation componentsfrom outputs being driven high and outputs being driven low are averagedand added to the total device power dissipation. Calculation of powercomponents due to DC loading of the outputs should be made separately foreach program segment before average power is calculated.Note that any unused inputs that are left disconnected may float to a voltagelevel that will cause input buffer circuits to remain in the linear region and thereforecontribute a significant component to power supply current. Accordingly,any unused inputs should be made inactive by being either grounded or pulledhigh if absolute minimum power dissipation is desired. If several unused inputsmust be pulled high, they may be pulled high together through one resistor tominimize component count and board space.When you use power dissipation values to determine thermal managementconsiderations, you should use the average power unless the time duration ofindividual program segments is long. The thermal characteristics of theTMS320C30 in the 181-pin PGA package are exponential in nature with a timeconstant t = 4.5 minutes. Therefore, when subjected to a change in power, thetemperature of the device package will reach approximately 63% of the totaltemperature change due to this power after 4.5 minutes. Accordingly, if thetime duration of program segments exhibiting high power dissipation valuesis short (on the order of a few seconds), average power, calculated in the samemanner as average current as described in the previous subsection, can beused.Otherwise, maximum device temperature should be calculated on the basis ofthe actual time duration of the program segments involved. For example, if aparticular program segment Ip.sts for 7 minutes, then using the exponentialfunction, it can be calculated that a device will reach approximately 80% of thetemperature due to the total power dissipation during the program segment.Note that the average power should be determined by calculating the powerfor each program segment (including considerations described above) andperforming a time average of these values, rather than simply multiplying theaverage current as determined in the previous subsection, by VOO.0-25
Calculation of TotalCurrentSpecific device temperature calculations are made using the TMS320C30thermal impedance characteristics included in the TMS320C30 data sheet inChapter 13 of the TMS320C3x User's Guide.D-26Calculation of TMS320C30 Power Dissipation
Current Calculationsor,I = 110 + (55 rnA)(0.8) + 60 rnA - 80 rnA + (170 rnA)(0.85)= 278.5 rnA0.5.3 AverageThe average current is derived from the two portions of the algorithm. The processingportion took 95% of the time and required about 21 0 mA, and the datadump portion took the other 5% and required about 280 mAo The average iscalculated as:lavg = (0.95)(21 rnA) + (0.05)(280 rnA) = 213.5 rnAFrom the thermal characteristics specified in the TMS320C3x User's Guide,it can be shown that this current level corresponds to a case temperature of43°C. This temperature meets the maximum device specification of 85°C andhence requires no forced air cooling.0.5.4 Experimental ResultsA photograph of the power supply current for the FFT is shown in the photographin Appendix A. During the FFT processing, the current measured variedbetween 180 and 220 mAo The peak of the current during external writes was270 mA, and the average current requirement, as measured on a digital multimeterwas 200 mAo The calculations yielded results that were extremely closeto the actual measured power supply current.0-28Calculation of TMS320C30 Power Dissipation
0.6 SummaryThe power supply current requirement for the TMS320C30 cannot be expressedsimply in terms of operating frequency, supply voltage, and outputload capacitance. A more complete specification, one based on device functionality,must be used to determine a more accurate power supply current requirement.This application note presents the necessary information you willrequire to determine power supply specifications. The specification is basedon a knowledge of the algorithm and its operation on the TMS320C30 in termsof internal and external bus usage. As devices become more complex, theapplication of the approach presented in this document becomes vital.The power supply current requirement for the TMS320C30 depends on devicefunctionality and system parameters.'The components of current related to devicefunctionality are those due to quiescent current, internal operations, internalbus operations, and external bus operations. The dependencies related tosystem parameters are those due to operating frequency, supply voltage, outputload capacitance, and operating temperature. The typical power supplycurrent requirement is 250 mA, and the minimum, or quiescent, is 110 mAoTflern~ximumcurrent requirement is 600mAandoccur~riril~pij::)derYVORSrCASE conditions: writing' alternating data(AAAAAAAAh to 55555555h) out of both external busessilllLJIta.l1eously, e"erycycle, with 80 pF loads and running at 331\i1HzJ> '.'0-29
Photo of 100 for FFT0.7 Photo of 100 for FFT300rnA500 ~s/Div.0-30 Calculation of TMS320C30 Power Dissipation
FFT Assembly Co.de_'''':G)~~.,., ......(::t.''''O$S$''')$$iI$'''''''~''''',1$~''''',,*'''''':~.....$;$""':;.$::9..,.,. ~_.""'"''''~_.:;C;'''''''~''''''''''''.;.'io:'''''.''_'5i:'''_;·· .....·~·$:lI .... ·;·.__.I._~·":...~:Xi_·~S.: ..... :::_·)._··.~·_···I""·n",,·:~·"':f,&_·.;~:,,_::._.'":>_')0(', .'~~"""':a:=,._ .. ___ ~ __. ':',»~~~~~~~~:"0.8FFT Assembly Code.GLOBL.GLOBL.GLOBL.GLOBLSINTAB:. WORDRAMO:. WORDOUTBUF:. WORD.TEXTFFTNMSINESINE809800h800hsetupFFT:LOPSINTABprocessing portion:quiescent, internal andbus operationsLOILSHN,IRO-l,IROLENGTH-TWO BUTTERFLIESLOILOISUBI@RAMO,AROIRO,RC1,RCRPTB BLKIAODF *+ARO,*ARO++,ROSUBF *ARO,*-ARO,RlBLKI STF RO,*-AROII STF Rl,*ARO++FIRST PASS OF THE DO-20 LOOP(STAGE K=2 IN DO-IO LOOP)LOILOILOILSHSUBI@RAMO,ARO2,IRON,RC-2,RC1,RCRPTB BLK2AODF *+ARO(IRO),*ARO++(IRO),ROSUBF *ARO,*-ARO(IRO),RlNEGF *+ARO,ROII STF RO, *-ARO (IRO)BLK2 STF Rl,*ARO++(IRO)II STF RO,*+AROMAIN LOOPLDI(FFT STAGES)N,IRO0-31
A.~ .. ~p./nh.lv CodeLOOPLSHLDILDILDILSHLSHLSH-2,IRO3,R51, R42,R3-l,IRO1,R41,R3INNER LOOPINLOP:IIIILDILDIADDILDILDIADDILDIADDILDISUBIADDILDFADDFSUBFSTFNEGFNEGFSTFSTFINNERMOSTLDILSHLDISUBI(DO-20 LOOP IN THE PROGRAM)LOOP@RAMO,AR5IRO,ARO@SINTAB,AROR4,IRIAR5,ARI1,ARlARl,AR3R3,AR3AR3,AR22,AR2R3,AR2,AR4*AR5++(IRl) ,RO*+AR5(IRl) ,RO,RlRO,*++ARS(IRl),RORl, *-ARS (IRl)RO*++ARS(IRl),RlRO, *ARSRl, *ARSN, IRI-2,IRIR4,RC2,RCIIIIIIIIBLK3RPTBMPYFMPYFMPYFADDFMPYFSUBFSUBFADDFSTFADDFSTFSUBFSTFSTFSUBIBLK3*AR3,*+ARO(IRl),RO*AR4,*ARO,Rl*AR4,*+ARO(IRl),RlRO,Rl,R2*AR3,*ARO++(IRO),RORO,Rl,RO*AR2,RO,Rl*AR2,RO,RlRl,*AR3++*ARl,R2,RlRl,*AR4- -R2,*ARl,RlRl,*ARl++Rl,*AR2- -@RAMO,ARSD-32Calculation of TMS320C30 Power Dissipation
CodeADDICMPIBLTDADDINOPNOPR4,AR5N,AR5INLOP@RAMO,AR5ADDI 1,R5CMPI M,R5BLE LOOPDUMP LDI @RAMO,ARO data dump portionLDI @OUTBUF,ARl quiescent, internal busLDF *ARO++,RO ops and primary bus opsRPTS N-2LDF *ARO++,ROI I STF RO,*ARl++STF RO,*AR1++LDIRAMO,ARlLDI @RAMO,ARO swap RAM banksXOR 400h,AROSTI ARO,*ARlB.ENDFFT0-33
0-34 Calculation of TMS320C30 Power Dissipation
L...-___ S_M_J3_2_0_C_3_0_D_i_9_it_a_1 S_i_9_n_a_1 P_r_o_c_e_sS_O_r_D_a_t_a_S_h_e_e_t ________, __
....... _____ S_M_J_32_0_C_3_0_D_i_9_it_8_1 S_i_9_n_8_1 P_r_o_c_e_s_sO_r_D_8_t_8_S_h_e_e_t ___ --'
Chapter E. SMJ320C30 Digital Signal ProcessorData SheetThis appendix contains the standalone data sheet for the SMJ320C30 DigitalSignal Processor.E-1
E-2 SMJ320C30 Digital Signal Processor Data Sheet
• PerformanceSMJ320C30-28 (70-ns Single CycleInstruction Execution Time)28.6 MFLOPS (MillionFloating-Point Operations perSecond)14.3 MIPS (Million Instructions perSecond)••SMJ320C30-25 (80-ns Single CycleInstruction Execution Time)- 25 MFLOPS- 12.5 MIPSClass 8 High-Reliability ProcessingOne 4K x 32-81t Single-Cycle Dual-AccessOn-Chip ROM 810ck• Two 1 K x 32-8it Single-Cycle Dual-AccessOn-Chip RAM 810cks• 64-Word x 32-81t Instruction Cache• 32-81t Instruction and Data Words, 24-81tAddresses••••••••••••40/32-8It Floating Point/Integer Multiplierand ALU32-Bit 8arrel ShifterEight Extended-Precision Registers(Accumulators)Two Address Generators With EightAuxiliary Registers and Two AuxiliaryRegister Arithmetic UnitsOn-Chip Direct Memory Access (DMA)Controller for Concurrent I/O and CPUOperationInteger, Floating Point, and LogicalOperationsTwo- and Three-Operand InstructionsParallel ALU and Multiplier Executions In aSingle Cycle810ck Repeat CapabilityZero-Overhead Loops with Single-CycleBranchesConditional Calls and ReturnsInterlocked Instructions forMultiprocessing Support• Two External Interface PortsEPIC is a trademark of Texas Instruments Incorporated.••••••PRODUCTION DATA documents contain Informationcurrent .. 01 publication dati. Products conform tospecifications p.r thl t.rms of Tun fnstrum.ntsstandard warranty. Production processing dOli notTEXAS l!1nec ... arily Includ.ttSling 01 all parameters.INSTRUMENTS49ABCDEFGH'JKLMNPR
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991descriptionThe SMJ320C30's internal bus and special digital processing (DSP) instruction set have the speed and flexibilityto execute up to 28.6 MFLOPS (million floating-point operations per second). The SMJ320C30 optimizes speedby implementing functions in hardware that other processors implement through software or microcode. Thishardware-intensive approach provides the design engineer with power previously unavailable on a single chip.The SMJ320C30 can perform parallel multiply and ALU operations on integer or floating-point data in a singlecycle. The processor also possesses a general-purpose register file, program cache, dedicated auxiliary registerarithmetic units (ARAU), internal dual-access memories, one DMA channel supporting concurrent I/O, and ashort machine-cycle time. High performance and ease of use are achieved through greater parallelism, greateraccuracy, and general-purpose features.General-purpose applications are greatly enhanced by the large address space, multiprocessor interface,internally and externally generated wait states, two external interface ports, two timers, two serial ports, andmultiple interrupt structure. The SMJ320C30 supports a wide variety of system applications from host processorto dedicated coprocessor.High-level language is more easily implemented through a register-based architecture, large address space,powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.E-4TEXAS ~INSTRUMENTSPOST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991pin functional description.GB package pin function assignmentsPIN FUNCTION PIN FUNCTION PINF15 AO C4 DO P3G12 A1 05 01 R2G13 A2 A2 02 N4G14 A3 A3 03 M5G15 A4 84 04 R1H15 A5 C5 05 R3H14 A6 06 06 M3J15 A7 A4 Of PlJ14 A8 85 08 L4J13 A9 C6 09 N2K15 <strong>Al</strong>0 AS 010 NlJ12 <strong>Al</strong>l 86 011 P2K14 A12 07 012 ,L15 A13 A6 013 F14K13 A14 C7 014 E15L14 A15 87 015 F13M15 A16 A7 016 E14K12 A17 A8 017 F12L13 A18 88 018 ClM14 A19 A9 019 M6N15 A20 89 020 83M13 A21 C9 021 <strong>Al</strong>L12 A22 <strong>Al</strong>0 022N14 A23 09 023 C2E5 LOCATOR 810 024 81Gl lACK <strong>Al</strong>l 025 P4H2 INTO Cl0 026 N5Hl INTl 811 027Jl INT2 A12 028 G2J2 INT3 010 029 G3015 MC/MP Cl1 030 03E3 MSTRB 812 031 E4El ROY H4Fl RESET F3 HOLO 08G4 RfijJ E2 HOLDA M8F2 STR8 02 XROY H12F4 IOSTR8 01 XR1W N8FUNCTION PINFSROA13FSXOA14CLKRO 011CLKXOC12ORO 813OXOA15FSRl 815FSXlC14CLKRlE12CLKXl 013ORlC15OXl 014E13EMUOJ3EMUlJ4EMU2KlEMU3K2EMU4L1EMU5K3EMU6L2HlK4H3MlL3XlM2X2/CLKIN 012TCLKO HllTCLKl 04E8XFOL8XFlM12V88PH5VSU8SM4VOOB2VOOP14VOOC8VOOH3VssH13FUNCTION PIN FUNCTIONXAO R4 XOOXA1 P5 X01XA2 N6 X02XA3 R5 X03XA4 P6 X04XA5 M7 X05XA6 R6 X06XA7 N7 X07XA8 P7 X08XA9 R7 X09XA10 P8 X010X<strong>Al</strong>l R8 XOllXA12 R9 X012RSVO P9 X013RSVl N9 X014RSV2 Rl0 X015RSV3 M9 X016RSV4 Pl0 X017RSV5 Rll X018RSV6 Nl0 X019RSV7 P,ll X020RSV8 R12 X021RSV9 Ml0 X022RSV10 Nll X023AOVOO P12 X024AOVOO R13 X025OOVOO R14 X026OOVOO Ml1 X027IOOVOO N12 X028IOOVOO P13 X029MOVOO R15 X030POVOO P15 X031CVSS C3 OVSSCVss C13 OVSSVss N3 OVssVss N13 OVSSVSS 814 IVSSNOTES: 1. AOVOO, OOVOO, IOOVOO, MOVOO, and POVOO pins are on a common plane internal to the device.2. VOO pins are on a common plane internal to the device.3. VSS, CVSS, and IVSS pins are on a common plane internal to the device.4. OVSS pins are on a common plane internal to the device.TEXAS -1!1INSTRUMENTSPOST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 E-5
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991HU/HT package pin function assignmentsPIN FUNCTION PIN' FUNCTION PIN FUNCTION PIN FUNCTION1 POVOO 41 X023 81 A1 121 0192 POVOO 42 X024 82 AO 122 0183 ORO 43 X025 83 EMUO 123 VOO4 FSRO 44 X026 84 EMU1 124 VOO5 CLKRO 45 X027 85 EMU2 125 VSS6 CLKXO 46 X028 86 EMU3 126 VSS7 FSXO 47 X02'9 87 EMU4 127 0178 OXO 48 X030 88 MC/MP 128 0169 TCLKO 49 IOOVOO 89 XA12 129 01510 TCLK1 50 OVSS 90 XA11 130 01411 EMU6 51 CVSS 91 XA10 131 01312 XOO 52 CVSS 92 XA9 132 01213 X01 53 X031 93 XA8 133 01114 X02 54 A23 94 XA7 134 01015 IODVOO 55 A22 95 XA6 135 0916 IOOVOO 56 A21 96 IVSS 136 0817 X03 57 A20 97 IVSS 137 0718 X04 58 A19 98 OVss 138 D619 X05 59 A18 99 VSUBS 139 0520 X06 60 A17 100 ADVoD 140 D421 X07 61 A16 101 ADVOD ·141 0322 X08 62 A15 102 XA5 142 0223 X09 63 A14 103 XA4 143 0124 X010 64 AOVOO 104 XA3 144 DO25 VOO 65 A13 105 XA2 145 H126 VOO 66 A12 106 XA1 146 H327 Vss 67 A11 107 XAO 147 oOVOO28 Vss 68 A10 108 031 148 OVSS29 X011 69 A9 109 030 149 CVss30 X012 70 A8 110 029 150 CVSS31 X013 71 A7 111 028 151 X2/CLKIN32 XD14 72 A6 112 027 152 X133 X015 73 VOO 113 026 153 VSUBS34 X016 74 VOO 114 oOVOO 154 V88P35 X017 75 Vss 115 025 155 EMUS36 X018 76 VSS 116 024 156 XRi5Y,37 X019 77 A5 117 D23 157 MSTRB38 X020 78 A4 118 022 158 IOSTRB39 X021 79 A3 119 021 159 XRrW40 X022 80 A2 120 020 160 HOLDAPIN FUNCTION161 HOLD162 MOVoO163 MOVOO164 ROY165 STRB166 Rm167 RESET168 XF1169 XFO170 lACK171 INTO172 VOO173 VOO174 VSS175 VSS176 INT1177 INT2178 INT3179 RSVO180 RSV1181 RSV2182 RSV3183 RSV4184 RSV5185 RSV6186 RSV7187 RSV8188 RSV9189 RSV10190 OR1191 FSR1192 CLKR1193 CLKX1194 FSX1195 OX1196 oVSSNOTES: 1. AOVOO, OOVOO, IOOVOD, MOVOO, and POVOO pins are on a common plane internal to the device.2. VOO pins are on a common plane internal to the device.3. VSS, CVSS, and IVSS pins are on a common plane internal to the device.4. OVSS pins are on a common plane internal to the device.E-GTEXAS "!1INSlRUMENTSPOST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991signal descriptions.This section gives signal descriptions for the SMJ320C30 device in the microprocessor mode. The followingtables list each signal, the number of pins, function, and operating mode(s}, i.e., input, output, or high-impedancestate as indicated by I, 0, or Z. <strong>Al</strong>l pins labelled NC are not to be connected by the user. A line over a signal name(e.g., RESET) indicates that the signal is active low (true at a logic 0 level). The signals are grouped accordingto function.signal descriptionsPINI/o/ZtNAME NOs.031-00 32 I/O/ZA23-AO 24 O/ZRm 1 O/ZSTRB 1 O/ZROY 1 IHOLD 1 IHOLDA 1 0X031-XOO 32 !lO/ZXAI2-XAO 13 O/ZXRm 1 O/ZMSTRB 1 atOSTRB 1 0XROY 1 IRESET 1 IINT3-INTO 4 IlACK 1 0MC/MP 1 IXF1, XFO 2 I/O32-bit data port of the primary bus interface.DESCRIPTIONPRIMARY BUS INTERFACE24-bit address port of the primary bus interface.Read/write signal for primary bus interface. This pin is high when a read is performed and lowwhen a write is performed over the parallel interface.External access strobe for the primary bus interface.Ready signal. This pin indicates that the external device is prepared for a primary bus interfacetransaction to complete. As long as ROY is a logic high, the data and address buses ofthe primary bus interface remain valid.Hold signal for primary bus interface. When HOLD is a logic low, any ongoing transaction iscompleted. The A23-AO, 031-00, STRB, and Rm signals are placed in a high-impedancestate, and all transactions over the primary bus interface are held until HOLD becomes a logichigh.Hold acknowledge signal for primary bus interface. This signal is generated in response to alogic low on HOLD. It Signals that A23-AO, 031-00, STRB, and Rm are placed in a high-impedancestate and that all transactions over the bus will be held. HOLDA will be high in responseto a logic high of HOLD.EXPANSION BUS INTERFACE32-bit data port of the expansion bus interface.13-bit address port of the expansion bus interface.Read/write signal for expansion bus interface. When a read is performed, this pin is held high;when a write is performed, this pin is low.External memory access strobe for the expansion bus interface.External I/O access strobe for the expansion bus interface.Ready signal. This pin indicates that the external device is prepared for an expansion businterface transaction to complete. As long as XROY is high, the data and address buses ofthe expansion bus interface remain valid.CONTROL SIGNALSReset. When this pin is a logic low, the device is placed in the reset condition. When RESETbecomes a logic high, execution begins from the location specified by the reset vector.External interrupts.Interrupt acknowledge signal. lACK is set to 1 by the lACK instruction. This can be used to indicatethe beginning or end of an interrupt service routine.Microcomputer/microprocessor mode pin.External flag pins. They are used as general-purpose I/O pins or to support interlocked processorinstructions.t Input, output, high-impedance state.TEXAS -I!}INSlRUMENlSPOST OFFICE BOX 1443 • HOUSTON. TEXAS 77001 E-7
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991signal descriptions (continued)NAMEPINNOs.I/O/ZtCLKXO 1 I/ODXO 1 OIlFSXO 1 I/OCLKRO 1 I/OORO 1 IFSRO 1 ICLKXl 1 I/ODXl 1 OIlFSXl 1 I/OCLKRI 1 I/ODRl 1 IFSR1 1 ITCLKO 1 I/OTCLKl 1 I/OVOO 4/8 I10DVOO 2/3 IAOVDD 2/3 IPOVOO 1/2 IOOVDO 2/2 IMDVOD 1/2 IVSS 4/8 IOVSS 4/4 ICVSS 2/4 IIVSS 1/2 IVBBP 1/1 NCVSUBS 1/2 IXI 1 aX2/CLKIN 1 IHI 1 aH3 1 at Input, output, high-impedance state.NOTE 5: GB/HU power pins.DESCRIPTIONSERIAL PORT 0 SIGNALSSerial port 0 transmit clock. This pin serves as the serial shift clock for the serial port 0 transmitter.Data transmit output. Serial port 0 transmits serial data on this pin.Frame synchronization pulse for transmit. The FSXO pulse initiates the transmit data processover pin DXO.Serial port 0 receive clock. This pin serves as the serial shift clock for the serial port 0 receiver.Data receive. Serial port 0 receives serial data via the ORO pin.Frame synchronization pulse for receive. The FSRO pulse initiates the receive data process overORO.SERIAL PORT 1 SIGNALSSerial port 1 transmit clock. This pin serves as the serial shift clock for the serial port 1 transmitter.Data transmit output. Serial port 1 transmits serial data on this pin.Frame synchronization pulse for transmit. The FSXl pulse initiates the transmit data processover pin DX1.Serial port 1 receive clock. This pin serves as the serial shift clock for the serial port 1 receiver.Data receive. Serial port 1 receives serial data via the DRl pin.Frame synchronization pulse for receive. The FSRl pulse initiates the receive data processover OR1.TIMER 0 SIGNALSTimer clock. As an input, TCLKO is used by timer 0 to count external pulses. As an output pin,TCLKO outputs pulses generated by timer O.TIMER 1 SIGNALSTimer clock. As an input, TCLKl is used by timer 1 to count external pulses. As an output pin,TCLKl outputs pulses generated by timer 1.+5 V supply pin.+5 V supply pin.+5 V supply pin.+5 V supply pin.+5 V supply pin.+5 V supply pin.Ground pin.Ground pin.Ground pin.Ground pin.VBB pump oscillator output.Substrate pin. Tie to ground.SUPPLY AND OSCILLATOR SIGNALS (see Note 5)Output pin from the internal oscillator for the crystal. If a crystal is not used, this pin should beleft unconnected.Input pin to the internal oscillator from the crystal or a clock.External HI clock. This clock has a period equal to twice ClKIN.Externai"H3 clock. This clock has a period equal to twice ClKIN.E-8TEXAS l!IINSlRUMENTSPOST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991signal descriptions (concluded)PINI/O/ZtNAME NOs.EMUO-EMU2 3 IEMU3 1 0EMU4 1 IEMU5. EMU6 2 NCRSVO·RSV10 11 It Input. output. high-impedance state.Reserved. Use pullups to +5 volts.Reserved.Reserved. Use pullups to +5 volts.Reserved.Reserved. Use pull ups to +5 volts.DESCRIPTIONRESERVEDCAUTIONFollow the connections specified for the reserved pins. <strong>Al</strong>l pullup resistors must be 20 kQ. <strong>Al</strong>l +5 volt supply pinsmust be connected to a common supply plane, and all ground pins must be connected to a common ground plane.ELECTRICAL SPECIFICATIONSabsolute maximum ratings over specified temperature range (unless otherwise noted) :J:Supply voltage range, Vee .......................................................... - 0.3 V to 7 VInput voltage range ...... , ............ , ... , ........................................ - 0.3 V to 7 VOutput voltage range ............................ , .............. ,................... - 0.3 V to 7 VContinuous power dissipation (see Note 11) ....... ,........................................ 3.15 WMinimum free air operating temperature .......................... , ........ , ............. , .. - 55°CMaximum operating case temperature , ...... " ......................... ,................... 125°CStorage temperature range ................... , .............. ,................... - 65°C to 150°C:j: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only;functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" sectionof this specification is not implied. Exposure to absolute-maximum·rated conditions for extended periods may affect device reliability.NOTES: 6. <strong>Al</strong>l voltage values are with respect to VSS.7. Actual operating power will be less. This value was obtained under specially produced worst·caso tost conditions, which nro notsustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to bothprimary and extension buses at the maximum rate possible. See normal (ICc) current specification in the "electrical characteristics"table and also read Calculation of TMS320C30 Power DiSSipation Application Report.TEXAS ~INSTRUMEN1SPOST OFFICE BOX 1443 • HOUSTON. TEXAS 77001 E-9
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991recommended operating conditions (see Note 8)VDDVSSSupply voltagesSupply voltages (CVSS, etc.)ISMJ320C30-28I SMJ320C30-25MIN NOM MAX UNIT4.75 5 5.25V4.5 5 5.50 VVIHHigh-level input voltage2.1 VDD + 0.3§ VVTHClKIN high-level input voltage for ClKIN3 VDD+0.3§ VVILLow-level input voltage- 0.3§ 0.8 VIOHHigh-level output current-300 ~lAIOLLow-level output current2 mATCOperating case temperature125 °CTAOperating free-air temperature-55 °c§ These values derived from characterization but not tested.NOTE 8: <strong>Al</strong>l input and output voltages are TTL compatible.electrical characteristics over specified temperature rangeVOHVOLVOLXIZIIPARAMETERHigh-level output voltage (VOO = Min, IOH = Max)Low-level output voltage ( VDD = Min, IOL = Max)low-level output voltage (VDD = Min, IOL = Max), (XA 12-XAO)Three-state current ( VDD = Max)Input current ( VI = VSS to VDD)MIN NOM MAX UNIT2.4 3 V0.3 0.6 VO.6t V± 20 IlA±10 ~l<strong>Al</strong>iP Input current (Inputs with internal pullups) (see Note 12)-400 20 IlAIICInput current ( X2/CLKIN), (VI = VSS to VCC)± 50 ~lAICC Supply current (VDO = Max, fx = Max) (see Note 13)200 600 mACICoCxInput capacitanceOutput capacitanceX2/CLKIN capacitance15* pF20* pF------25* pFt Derived from characterization and not tested.:\: Derived by design but not tested.NOTES: 9. <strong>Al</strong>l nominal values are at VDD = 5 V, T A = 25°C.10. fx is the input clock frequency.11. <strong>Al</strong>l input and output voltage levels are TTL compatible.12. Pins with internal pullup devices: INTO-INT3, MC/MP, RSVO-RSV10.13. Actual operating current will be less than this maximum value. This value was obtained under speCially producedworst·case test conditions, which are not sustained during normal device operation. These conditions consist ofcontinuous parallel writes of a checkerboard pattern to both primary and expansion buses at the maximum ratepossible. See Calculation of TMS320C30 Power Dissipation Application Report. .E·10TEXAS l!}INS1RUMENTSPOST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ320C30DIGITAL SIGNAL PROCESSORTester PinElectronicsPARAMETER MEASUREMENT INFORMATION-,IIIVLoadII Output>-_.--+0 UnderI TestCT IIII_JSGUS014 - FEBRUARY 1991Where:IOL = 2 rnA (all outputs)IOH = 300 IlA (all outputs)VLoad = 2.15 VCT = 80 pF typical load circuit capacitance.Figure 1. Test Load Circuitsignal transition levelsTTL-level outputs are driven to a minimum logic-high level of 2.4 volts and to a maximum logic-low level of 0.6volts. Output transition times are specified as follows.For a high-to-Iow transition on a TTL-compatible output signal, the level at which the output is said to be no longerhigh is 2 volts, and the level at which the output is said to be low is 1 volt. For a low-to-high transition, the levelat which the output is said to be no longer low is 1 volt, and the level at which the output is said to be high is 2volts.2.4V2VFigure 2. TTL-Level Outputs1 VO.6VTransition times for TTL-compatible inputs are specified as follows. For a high-to-Iow transition on an inputsignal, the level at which the input is said to be no longer high is 2.1 volts, and the level at which the input is saidto be low is 0.8 volt. For a low-to-high transition on an input signal, the level at which the input is said to be nolonger low is 0.8 volt, and the level at which the input is said to be high is 2.1 volts.====;!----. -----------~---- ------------------ ---Figure 3. TTL-Level Inputs90%10%0.8VTEXAS -IllINSTRUMENTSPOST OFFICE BOX 1443 • HOUSTON. TEXAS 77001E-11
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991timing parameters for elKIN, H1, and H3 (see Note 11)NO.PARAMETERSMJ320C30·28SMJ320C30·2SMIN MAX MIN MAX1 tf(CI) ClKIN fall time 5t st2 tw(Cll) ClKIN low pulse duration tc(CI) = min (see Note 15) 12.5 143 tw(CIH) ClKIN high pulse duration tc(CI) = min (see Note 15) 12.5 144 tr(CI) ClKIN rise time 5t 5t5 tc(CI) CLKIN cycle time 35 406 tf(H) H1/H3 fall time 3 47 tw(Hl) H1/H31ow pulse duration (see Note 14) P-6 P-68 tw(HH) H 1 /H3 high pulse duration (see Note 14) P-7 P-79 tr(H) H1/H3 rise time 4 49.1 td(HL·HH) Delay from H1 (H3) low to H3(H1) high ot 5 ot 510 tclH) H1/H3 cycle time 70 606 80 606t Derived by design but not tested.NOTES~ 11. <strong>Al</strong>l input and output voltages are TIL compatible.14. P = tc(CI)15. Rise and fall times, assuming a 35-65% duty cycle, are incorporated within this specification. See X2/CLKIN timing below.X2/CLKIN timingUNITnsnsnsnsnsnsnsnsnsnsnsX2/CLKIN1--.1I*-411~s----"'·l.f.--3 ~ :I I III 1~2~(1.5V)H1/H3 timingH1--.I I1~1I14- 9~I10r.- 6III~7~I---.l ~ 9.1H3~ /~B~\1114114~II1I I 1 1~ ~9 --'1 ~67 ~ 1110.,E·12TEXAS ~INSffiUMENlSPOST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991memory read/write cycle timing (MSTRB = 0)NO.PARAMETER11 td(H1 L-(M)SL) H1 low to (M)STRB low12 td(H1 L-(M)SH) H1 low to (M)STRB high13.1 td(H1H-RWL) H1 high to RNJ low13.2 td(H1 H-XRWL) H1 high to (X)RNJ low14.1 td(H1L-A) H1 low to A valid14.2 tdlH1L-XA) H 1 low to (X)A valid15.1 tsu(D)R D valid before H1 low (read)15.2 tsujXD)R (X)D setup before H1 low (read)16 th((X)D)R (X)D hold time after H1 low (read)17.1 tsu--'-RD'r'J RDY setup before H1 high17.2 tsu(XRDY) XRDY setup before H1 high18 th((X)RDY) XRDY hold time after H1 high19 td(H1 H-(X)RWH) H1 high to (X)RNJ high (write)20 tv((X)D)W (X)D valid after H1 low (write)21 th((X)D)W (X)D hold time after H1 high (write)22.1 td(H1H-A) H1 high to A valid on back-to-back write cycles (write)22.2 td(H1H-XA) H1 high to XA valid on back-to-back write cycles (write)26 td(A-XRDY) (X)RDY delay from A validSMJ320C30-28 SMJ320C30-25MIN MAX MIN MAXUNITot 10 of 10 ns0* 10 0* 10 nsot 10 0* 10 ns0* 17 0* 1a nsot 16 0* 1a ns0* 12 0* 14 ns19 19 ns20 20 nsot ot ns10 10 ns10 12 ns0 0 ns12 12 ns20 20 ns0 0 ns22 22 ns32 32 nsat at nst These values derived from characterization but not tested.* These values derived by design but not tested.TEXAS ..INSlRUMENTSPOST OFFICE BOX 1443 • HOUSTON, TEXAS 77001E-13
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991memory read cycle timing (MSTRB ::: 0)H3H11 I1 1 I~ ~ 11 -.j ~ 1~~I 1 II/_~-----MSTRB~:_11 I I(X)RiW: : : 1\1 1 I 1 ----1~ 14- 14.1/14.2 I ~;.- 13I 1 ~(X) A X )(__-J 15.1/15.2 ~ '------26 ~:t- 1-.1 ~ 161(X)D I 1 0 )------17.1/17.2 ~ ~___"""\ tl *-18\l yr-------memory write cycle timing (MSTRB = 0)H3H1 1 11 1 1 I I111 -.I ~ ~ ~ 12MSTRB : I :\l: ; :1 I 1 1 II ~ ~ 13 1 1(X)R/w: 'x:: :~ I'f- 14.1/~4.2 I 1(X)A =X =\'-_---J/ :-.I 14- 191!~ ~: X'ttt-22.1/22.2x'-___ _20::;l ~ 1(X)D --__ --
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991memory read cycle timing (IOSTRB = 0)NO.PARAMETER27 td(H1 H-IOSL) H1 high to IOSTRB low28 td(H1 H-IOSH) H1 high to IOSTRB high29 td(H1 L-XRWH) H1 low to XRN/ high30 td(H1L-XA) H1 low to XA valid31 tsu(XD)R XD setup before H1 high32 th{XD)R XD hold time after H1 high33 tsuiXRDY) XRDY setup before H1 high34 th(XRDY) XRDY hold time after H1 hight These values derived from characterization but not tested.1: These values derived by design but not tested.SMJ320C30·28MINMAX01: 1101: 1001: 1001: 1115at10aSMJ320C30·25MINMAXUNIT01: 11 ns01: 10 ns01: 12 ns01: 13 ns15 nsatns12 nsansH3HlII127 --.!I IIIXRm=/--.I 14- 29IOSTRB--.! tct- 30XA==>(XDXRDY~~II28~I~ II1/ IIII--1 1..- 35IIIII31 --.!I~ ~ 3233 ~Qt~ >CI --.! ~ 34\l YTEXAS -1.!1INSTRUMENTSPOST OFFICE BOX 1443 • HOUSTON, TEXAS 77001E·15
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991memory write cycle timing (IOSTRB = 0)SMJ320C30-28NO.PARAMETERMIN MAX35 Id(H1L-XRWL) H1 low 10 (X)RIVV low ot 1536 Iv(XD)W XD valid after H 1 high 3037 Ih(XmW XD hold lime after H1 low 0SMJ320C30-25UNITMIN MAXot 15 ns30 ns0 nst These values derived by design bul nollesled.H3H1IIII. I27~ ~ 28 --.I ~--~------hl \: I: I~---:~------IOSTRB : \ ,II I ~I ------+--1 ~ ~ 29-.1 ~ 35 I I I I~II I:LXRiW ~ I I I-IIE-16TEXAS'l!1INSlRUMEN1SPOST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ320C30DIG'ITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991timing for XFO and XF1 when executing LOFI or LOllNO.PARAMETERSMJ320C30·28MIN MAXSMJ320C30·25MIN MAXUNIT383940td(H3H·XFOL)tsu{XF1)th(XF11H3 high to XFO lowXF1 valid before H1 lowXF1 hold time after H1 low1501515015nsnsnsH3FetchLDFI or LOllDecode Read ExecuteH1MSTRB(X)RIWXFO PinXF1 PinIIIIIIIIIIIII(X) AII(X) 0 I IIIIII(X)RDYIII38 -.! I'f-I39 -JlI r4-I I4! ~ 40\l V-I:\ /IIIIIX x=-----be\lTEXAS -I!}INSTRUMENTSPOST OFFICE BOX 1443 • HOUSTON, TEXAS 77001E·17
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991timing for XFO when executing a STFI or STIISMJ320C30·28 SMJ320C30·25NO.PARAMETERMIN MAX MIN MAX41 td(H3H·XFOH) H3 high to XFO high 20 20UNITnsH3FetchI STFI or STII Decode I Read Execute IH1IIII\ r-(X)R/W i\ ;-(X) A~i >C(X) 0XFO Pintiming for XFO and XF1 when executing a SIGIIIII -
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991timing for loading XF register when configured as an output pinNO.PARAMETERSMJ320C30·28 SMJ320C30·25MIN MAX MIN MAXUNIT45 tvIH3H-XF)H3 high 10 XF valid20 20nsH3Fetch LoadInstruction Decode ReadExecuteH1OUTXF BitXF Pin~lO
S'MJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991change of XF from input to output modeNO.PARAMETERSMJ320C30-28MIN MAXSMJ320C30-25MIN MAXUNIT49 td(H3H-XFIO}H3 high to XF switching frominput to output2020nsExecution ofLoad of IOFH3H1iOXF BitXF Pin------------------------------------~
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991reset timingNO.PARAMETERSMJ320C30·28 SMJ320C30·25MIN MAX MIN MAXUNIT50 tsu(RESEn Setup for RESET before CLKIN low10 10 ns51 td(CLKINH-H 1 H) CLKIN high to H1 high5 18 5 18 ns52 td(CLKINH-H1 L) CLKIN high to H1 low5 18 5 18 ns53 tsu(RESETH-H 1 L)Setup for RESET high before H1 low and after10 H 1 clock cycles1St 1St ns54 td(CLKINH-H3L) ClKIN high to H3 low5 18 5 18 ns55 td(CLKINH-H3H) ClKIN high to H3 high5 18 S 18 ns56 tdis(H1 H-XO) H1 high to (X)O three state20t 20t ns57 tdis(H3H-XA) H3 high to (X)A three state12t 12t nsS8 td(H3H-CONTROLHl H3 high to control signals high10t 10t ns59 td(H1 H-IACKH) H 1 high to lACK high12t 12t ns60 tdis(RESETL-ASYNCH)RESET low to asynchronously reset signalsthree state2St 2St nst These values derived from characterization but not tested.RESET(see Notes 20, 21)H1H3(X) 0(see Note 16)(X) A(see Note 17)Control Signals(see Note 18)~~I ----r.-~------------~!~,- I ~14- 53II54 ~ 14- I I I I,...:...-----"\1 ~\ :iF>O!Hl CI;kCYCleS F- .:II --.I h 56I:~::::::~:::i}~1 ~~--~--~\~--------------------~II -~ tf-57 ~55~ t4- I 1~========~)~----+-~~---------~::;l r4- 58J~ ______________ ~7 I~ ______________________~7~~59IIINOTES: 16. (X)O includes 031-00 and X031·XOO.17. X(A) includes A23-AO, XA 12-XAO, and R/W.18. Control signals include STRB, MSTRB, and IOSTRB.19. Asynchronously reset signals include XF1, XFO, CLKXO, OXO, FSXO, CLKRO, ORO, FSRO, CLKX1, OX1, FSX1, CLKR1, OR1, FSR1,TCLKO, and TCLK1.20. RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exactsequence shown will occur; otherwise, an additional delay of one clock cycle may occur.21. Note that the R/W and XR/W outputs are placed in a high impedance state during reset and can be provided with a resistive pull-up,nominally 20 kQ, if undesirable spurious writes could be caused when these outputs go low.TEXAS ~INSTRUMENlSPOST OFFICE BOX 1443 • HOUSTON. TEXAS 77001 E·21
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991INT3-INTO response timingSMJ320C30·28SMJ320C30·25NO. PARAMETER UNITMIN NOM MAX MIN NOM MAX61 tsu(lNn INT3-INTO setup before H1 low 15 15 ns62tw(INT)(see Note 22)Interrupt pulse width to guarantee oneinterrupt seenP 1.5P < 2Pt P 1.5P < 2Pt nst These values derived from characterization but not tested. P = One H1 period.NOTES: 22. Interrupt pulse width must be at least 1 P wide to guarantee it will be seen. It must be less than 2 P wide to guarantee it will be respondedto only once. The recommended pulse width is 1.5 P.23. INT is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met. the exact sequenceshown will occur; otherwise. an additional delay of one clock cycle may occur.H3H1INTJ·INTO Pin '\l.INTJ·INTO FlagI-.,..- 61I~62--':Reset orInterruptVector ReadFetch FirstInstruction ofI Service Routine IIFirstInstructionAddressIIIIIADDR ____________________________ ~Data----------__________________________ ~~~------------~_____E·22TEXAS -I!IINSlRUMENTSPOST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991lACK timingNO.63 td(H1 H-IACKL) H1 high to lACK low64 td(H1 H-IACKH)PARAMETERH1 high to lACK high during first cycle of lACK instructiondata readSMJ320C30-28 SMJ320C30-25UNITMIN MAX MIN MAX12 12 ns12 12 nsNOTE 24: The lACK output is active for the entire duration of the bus cycle and is therefore extended if the bus cycle utilizes wait states.Fetch lACKInstructionlACKData ReadH3H1ADDR63,.-I ~64__ ---..;l\{"----JI__ ---Jx'-----Jx~ __DATA--------------------------~~-------TEXAS ~INSlRUMENTSPOST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 E-23
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991serial port timingNO.PARAMETER65 td(H1-SCK) H1 high to internal CLKXJR66 tc(SCK) CLKXJR cycle time67tw(SCK)CLKX/R high/lowpulse width68 tr(SCK). CLKXJR rise time69 tf(SCK) CLKXJR fall time70 td(OX) CLKX to OX validDR setup before71 tsu(OR) CLKX lowDR hold from72 th(OR) CLKR lowCLKX to internal73 td(FSX) FSX high/lowCLKXJR extCLKXJR intCLKXJR extCLKXJR intCLKX extCLKX intCLKR extCLKR intCLKR extCLKR intCLKX extCLKX intFSR setup before CLKR ext74 tsu(FSR) CLKR low CLKR int75 th(FS) FSXJR input holdExternal FSX setup76 tsu(FSX) before CLKXCLKX to first OX bit,77 td(CH-OX)V FSX precedesCLKX high78 td(FSX-OX)V79 tdOXZCLKXJR extCLKXJR intCLKX extCLKX intCLKX extCLKX intFSX to first OX bit, CLKX precedesFSXCLKX high to OX high Z followinglast data bitt These values derived from characterization but not tested.t These values derived by design but not tested.SMJ320C30-2SMINMAX17tc(H)x2.5tc(H)x2 2 tC(H)x232ttc(H)+15 t[tc(SCK)/21-15 [tc(SCK)/2J+5stst3520102510ot3217101010ot-[tc(H)-SJ [tc(CLK)/21-10 t-[tc(H)-21J tc(CLKX)/2 t36213620tSMJ320C30·25UNITMINMAX17 nstc(H)x2.5nstc(H)x2 2 tC(H)X232ttc(H)+15 tns[tc(SCK)/2J-15 [tc(SCK)/2J+5st nsst ns35ns2010ns2510nsot32ns1710ns1010nsot-[tc(H)-8} [tc(CLK)/21-10 t ns-[tc(H)-21J tc(CLKX)/2t36ns2136 ns20t nsTEXAS l!1INSlRUMENlSE-24 POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991serial port timing, fixed data rate modeH165~-------66------~1 ~I I ~67~1,--__ ~I I I IICLKXJR ---../I \l Ii ~ 67 ~0 ~r-I!I I I 1 I I -.I :.- 69 II I I 1 68 --.l ~ 1! I . I ~ I -.! 14- 79I I 70~ I ~ ~ 72 I\'-_-oJ1OX I I I ( IIDt 0 X Bit 1 :: Bit N 2>------. I I I --., ~ 71OR_~FSRlli: ~__ I~~...J ~74 I ~~ ;+-- 73 1 I --.l! I IFSX(INT) I! ~ 104- 75--""1...1 1IIFSX(EXT) --'" I 1II ~~ 14- 76~ 73~~------------------~;~\~--------------NOTES: 25. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = O.26. These timings are valid for all serial port modes, including handshake, except where otherwise indicated.serial port timing, variable data rate modeCLKXJR ----A \ Ii \ I ~~~ ~73 I 1 1FSX(INT) __ --+-': ! ~ ~ 78 : 1\ :FSX(EXT) 111////// JI I 70 -.l ~ Ii 1~ 77 --., 1 ~ ~ 79OX ------« Bit 0 X Bit 1 X Bit 2 :: Bit N )>------=.J ~75~ ~7~ I 1 INOTES: 27. Timings are valid for all serial port modes, including handshake, except where otherwise indicated.25. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = O.28. Timings not expressly specified for variable data rate mode are the same as those for fixed data rate mode.TEXAS l.!1INSlRUMENTSPOST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 E-25
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991HOLD/HOLDA timingNO.PARAMETER80 tsu(HOLD) HOLD valid before H1 low81 tv(HOLDA) HOLDA valid af1er H 1 low82 tw(HOLD) HOLD low width83 tw(HOLDA) HOLDA low width84 td(H1 L·SH)H H1 low to STRB high for a HOLD85 tdis(H1 L-S) H1 low to STRB high impedance state86 ten (H1L-S) H1 low to STRB active87 tdis(H1 L-RW) H 1 low to RNI high impedance state88 ten (H1 L-RW) H1 low to RNI active89 tdis(H 1 L-A) H1 low to address high impedance state90 ten (H1 L-A) H1 low to address valid91 tdislH 1 H-D) H1 high to data impedance stateSMJ320C30·28SMJ320C30·25MIN MAX MIN MAXt These values derived from characterization but not tested.l These values derived by design but not tested.NOTE 29: HOLD is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exactsequence shown will occur; otherwise. an additional delay of one clock cycle may occur.UNIT1S 1S ns0* 10 0* 10 ns2 2H1cyclestcH-St tcH-st ns0* lOt ot lOt ns0* lOt 0* lOt nsot lOt ot lOt ns0* lOt ot lOt ns0* lOt 0* lOt ns0* 1St ot 1St ns0* 1St ot 1St nsOt 1St 0* 1St nsH3H1I~~.- 80HOLD~HOLDASTRBRfilA0I84 -~Write Data82 III :+!~~II -.I ~ 81I ~ 83I I~~ ~ t4- 857 I 'I~:~ i4- 91~.- 87)~ *-89)80I--.l ~~81-.I ~ 86I II-.II ~ 88I I(-.I r4- 90
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991peripheral pin general-purpose I/O timingSMJ320C30-2B SMJ320C30-25NO. PARAMETER UNITMIN MAX MIN MAX92 tsu (GPIOH1l) Gel'!eral-purpose input setup time before H1 low 15 15 ns93 th(GPIOH1 l) General-purpose input hold time after H1 low 0 0 ns94 td(GPIOH1 H) General-purpose output delay after H1 low 15 15 nsNOTE 30: Peripheral pins include ClKXO/1, ClKRO/1, DXO/1, DRO/1, FSXO/1, FSRO/1, and TClKO/1. The modes of these pins are defined bythe contents of internal control registers associated with each peripheral.H3~H1~1perlphe;~~ __93 ~ 14-. I...;;9.;;;.2_--.! ..... >tS\~....l~__ 9_4 _____________timer pin timingNO.PARAMETERSMJ320C30·2BSMJ320C30·25MIN MAX MIN MAX78 tsu(TCLKH1 Ll TCLK setup before H 1 low 15 1579 th(TClKH1 L) TCLK hold after H1 low 0 080 tdITClKHl H} TCLK valid after H1 high 15 15NOTE 31: Period and polarity of valid logic level are specified by contents of internal control registers.H3H1perIPhe;~~x::::: ___\..J~~~~ rt- 96 97 --.l ~ -.: 14-~ r+-. 95 I I I - 97'.:~X~ __ .--J}--;~~::::::::::::UNITnsnsnsTEXAS ~INSlRUMENTSPOST OFFICE BOX 1443 • HOUSTON. TEXAS 77001E-27
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991change of peripheral pin from general purpose output to input modeSMJ320C30·28NO.PARAMETERMIN MAX98 th(H3H) Hold after H 1 high 1St99 tsu (GPIOH1L) Peripheral pin setup before H 1 low 1S100 thiGPIOH1U Peripheral pin hold after H1 low 0t These values derived from characterization but not tested.SMJ320C30·25MIN MAX1St1S0UNITnsnsnsExecute StoreOf PerlphalControlRegIsterBuffers Gofrom Output toInputSynchronIzer DelayValue on PInSeen InPerIpheralControl RegIsterH3H1III10 ___-....1 9~ t4-Control I I ~I - 100. ~ ro-BItI--.I !4- 98 I IPerIpheral -------m~:7\7'I:7\7'I'V\7''V\7'o::7'V'''V'V''V'V~'''V'\:rvo:::ro'\'T';F'-~:7\7'I'V\7'o::7'V'o::7'V'''V'V~~'''V'\:rvo:::ro'\7\7''":7\7'I~o::7'V'''V'V''VT~'f\7Pln ____ O_u_tP_u_t ____ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Data BitE·28TEXAS .J!1INSTRUMENTSPOST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991change of peripheral pin from general-purpose input to output modeNO.PARAMETERSMJ320C30-28MIN MAXSMJ320C30-25MIN MAXUNIT101 td(GPIOH 1 H)HI high to peripherial pin switching from input to output1515nsExecution of Store ofPeripheral ControlRegisterH3H110 ControlBitperIPhe;~III--.!------......... --------------------t\1..-- 1011......____TEXAS ~INSlRUMENlSPOST OFFICE BOX 1443 • HOUSTON. TEXAS 77001 E-29
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991SMJ320C30 part order informationDEVICETECHNOLOGYPOWERSUPPLYOPERATING PACKAGE PROCESSINGFREQUENCY TYPE LEVELSMJ320C30GBM251.0-f!m CMOS5V:t 10%25 MHz Ceramic 181-pin PGA Class BSM320C30GBM25SMJ320C30GBM281.0-,lm CMOS1.0-flm CMOS5V:t 10%5V:t5%25 MHz Ceramic 181-pin PGA SId28 Ml:'z Ceramic 181-pin PGA Class BSM320C30GBM28SMJ320C30HUM25SM320C30HUM251.0-flm CMOS1.0-,lm CMOS1.0-f!m CMOS5V:t5%5V:t 10%5V:t 10%28 MHz Ceramic 181-pin PGA Std25 MHz Ceramic 196-pin gullwing leaded carrier Class B25 MHz Ceramic 196-pin gullwing leaded carrier SIdSMJ320C30HUM281.0-~lm CMOS5V:t5%28 MHz Ceramic 196-pin gullwing leaded carrier Class BSM320C30HUM281.0-!lm CMOS5V:t5%28 MHz Ceramic 196-pin gullwing leaded carrier StdSMJ320C30HTM251.0-f!m CMOS5V:t 10%25 MHz Ceramic 196-pin quad flat pack Class BSM320C30HTM25SMJ320C30HTM28SM320C30HTM281.0-!lm CMOS1.0-,lm CMOS1.0-!lm CMOS5V:t 10%5V:t5%5V:t5%25 MHz Ceramic 196-pin quad flatpack SId28 MHz Ceramic 196-pin quad flatpack Class B28 MHz Ceramic 196-pin quad flatpack Stddevice nomenclaturePrefixSMJ = Class BSM = STDSMJ320C 30 GB M 28L Speed Range25 25 MHz28 = 28 MHzDevice Family320 = SMJ320 family'----- Temperature RangeM = - 55°C to 125°CL O°Cta 70°CTechnologyC = CMOSE =- CMOS EPROMNo lerter = NMOS'-------- Package TypeGBpin grid array (PGA)HT = 196 pin quad flalpack - flat leadHU = 196 pin quad flatpack - gull wingDeviceTEXAS -I!IINSTRUMENTSE-30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991HT 196·lead ceramic quad flatpack"'"~~486 , (1 915)..Typ47,8 (1.880)34,7 (1.365) T33,9 (1.335) yp..6,35 (0.250) Min Typ -. f4-~ 30,5 (1.200) Ref. Typ ~~ 15,2 (0.600)TypPin 1 Indlcato r-~K"\...lovoollovsslII[]1I-- - ---1-----[[] I1[!] I0,25 (0.010) -.li.-0,15 (0.006)Jlovssllovool[]]r--'\uL 0,64 (0.025) TypctctDetail "A"0,20 (0.008)0,10 (0.004)0,36 (0.014)0,05 (0.002)~ 0,25 (0.010) Max1I==-=t'i=2,67 (0.105) MaxThermal Resistance CharacteristicsParametero C/WR8JC 1.0R8JA 28.5Detail "A"3,30 (0.130) MaxALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHESTEXAS -I!}INSTRUMENTSPOST OFFICE BOX 1443 • HOUSTON. TEXAS 77001 E-31
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991HU 196-lead ceramic leaded chip carrier (gul/wing)2,55 (0.100) TypPin 1 IndicatorII-----+-----II0,25 (0.010) -JI.-0,15 (0.006)1,02 (0.040)0,50 (0.020)J L 0,64 (0.025) Typ££Detail "A"0,25 (0.010) Max0,64 (0.025) Min0,76 (0.030)---''--_-'['- 0,51 (0.020)Thermal Resistance CharacteristicsParametero CfWR0JCR0JA1.028.53,30 (0.130) MaxDetail "A"ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHESE-32T~ -I!}INSTRUMENlSPOST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ320C30DIGITAL SIGNAL PROCESSORSGUS014 - FEBRUARY 1991GB 181-pin ceramic pin grid arrayTop ViewVDDDVD~~ vss DVS.,/"\.' Thermal Resistance CharacteristicsPin <strong>Al</strong> _____ -uCorner Indicator I--. '~-------,Air FlowParameter °CN! LFPM4,70 (0.185)40,4 (1.590)37,6 (1.480)"SJ DVSSL>DVDDVS~VDD~14---- 40,4 (1.590) ___ ~~37,6 (1.480)R8JCf-----R8JAR8JAR8JAR8JAR8JAR8JA3,55 (0.140) ~ Side View- 1,40 (0.055)r- ~~ ~ ~ I ~ H ~ ~ ~ ~' ~ ~ ~;t,f 1,14(0.045)J0,506 (0.020) --II.-~ ~ 1,27 (0.050) Nom3,56 (0.140) 0,406 (0.016) Diameter305 (0.120) (180 Places) (4 Places), T~3.8-----21.613.39.78.37.47.1N/Ar----020040060080010002,54 (0.100) Typ Bottom ViewR @ • @@@@@@@@@@@@ @rP @ @@@@@@@@@@@@@ @N @ @@@@@@@@@@@@@ @M @@@@@@@@@@@@@@@L @@@@ @ @@@@K @@@@ @@@@35,6 (1.400) J @@@@ @@@@Ref H @@@@@ @@@@@G @ @@@ Extra Pin @@@@F @@@@ r @@@@E @@@@@ @ @@@@D @@@@@@@@@@@@@@@C @@@@@@@@@@@@@@@B • @@@@@@@@@@@@@ •A @ @@@@@@@@@@@@@ @1 2 3 4 5 6 7 8'9 10 11121314 15Index Corner2,54 (0.100) TypALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHESTEXAS "!IINSTRUMENTSPOST OFFICE BOX 1443 • HOUSTON. TEXAS 77001E-33
E-34 SMJ320C30 Digital Signal Processor Data Sheet
Quick Reference Guide
_Quick Reference GuideL....-I ___________-----J
Chapter FQuick ReferenceThis appendix is a collection of the most-referenced material in this user'sguide.Figure F-1Figure F-2Figure F-3Figure F-4Figure F-5Figure F-6Figure F-7Figure F-8Figure F-9Figure F-10Figure F-11Figure F-12Figure F-13Figure F-14Figure F-15Figure F-16Figure F-17Figure F-18Figure F-19Figure F-20Figure F-21Figure F-22Figure F-23Figure F-24Figure F-25Figure F-26Figure F-27Figure F-28Table F-1Table F-2Table F-3Table F-4Table F-5Table F-6Table F-7TMS320C3x Block Diagram ............................... F-4TMS320C3x Block Diagram ............................... F-5Extended-Precision Register Floating-Point Format. . . . . . . . . .. F-7Extended-Precision Register Integer Format. . . . . . . . . . . . . . . .. F-7Data-Page Pointer (DP) Register Format. . . . . . . . . . . . . . . . . . .. F-7Index Register (IRx) Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. F-7Block-Size (BK) Register Format . . . . . . . . . . . . . . . . . . . . . . . . . .. F-7Status Register.......................................... F-8CPU/DMA Interrupt Enable Register (IE) .................... F-9CPU Interrupt Flag (IF) Register Format. . . . . . . . . . . . . . . . . . . .. F-10IOF Register Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. F-11TMS320C30 Memory Map ................................ F-12TMS320C31 Memory Map ................................ F-; 3Reset, Interrupt, and Trap Vector Locations. . . . . . . . . . . . . . . . .. F-14Reset, Interrupt, and Trap Vector Format . . . . . . . . . . . . . . . . . . .. F-15Peripheral-Bus Memory-Map Registers ..................... F-16Memory-Mapped Locations for a DMA Channel .............. F-17DMA Global-Control Register Format. . . . . . . . . . . . . . . . . . . . . .. F-18Memory-Mapped Timer Locations ...... . . . . . . . . . . . . . . . . . . .. F-20Timer Global-Control Register ............................. F-21Memory-Mapped Serial-Port Locations ..................... F-23Serial-Port Global-Control Register Format . . . . . . . . . . . . . . . . .. F-24FSXlDX/CLKX Port Control Register Format. . . . . . . . . . . . . . . .. F-27FSR/DR/CLKR Port Control Register Format ................ F-28ReceiveiTransmit Timer Control Register Format. . . . . . . . . . . .. F-29Memory-Mapped External Interface Control Registers ........ F-31Primary-Bus Control Register Format .. . . . . . . . . . . . . . . . . . . . .. F-32Expansion-Bus Control Register Format .................... F-33Feature Set Comparison .................................. F-2TMS320C31 Reserved Memory Locations .................. F-3CPU Register/Assembler Syntax and Function. . . . . . . . . . . . . .. F-6BNKCMP and Bank Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. F-34Indirect Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. F-35Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. F-37Parallel Instruction Set Summary. . . . . . . . . . . . . . . . . . . . . . . . . .. F-42F-1
TMS320C30 and TMS320C31 DifferencesF.1 TMS320C30 and TMS320C31 DifferencesTable F-1. Feature Set ComparisonThis section addresses the major memory access differences between theTMS320C31 and the TMS320C30 devices. Observance of these considerationsis critical for achieving design goal success. Table F-1 shows these dif·ferences.DeviceFeature TMS320C31 TMS320C30Data/program bus Primary bus: one bus composed Two buses:of a 32-bit data and a 24-bit ad- 1} Primary bus: a 32-bit data and adress bus24-bit address2) Expansion bus: a 32-bit data and a13-bit addressSerial I/O ports 1 serial port (SPO) 2 serial ports (SPO, SP1)User program/data ROM Not available 4K words/16K bytesProgram boot loader User selectable Not availableF.1.1Data/Program Bus DifferencesThe TMS320C31 uses only the primary bus and reserves the memory spacethat was previously used for expansion bus operations.F.1.2Serial Port DifferencesSerial port 1 references in Section 8.2 of the TMS320C3x User's Guide are notapplicable to the TMS320C31. The memory locations identified for the associatedcontrol registers and buffers are reserved.F.1.3Reserved Memory LocationsTable F-2 identifies TMS320C31 reserved memory locations in addition tothose shown in Table 3-8.F-2Quick Reference
TMS320C30 and TMS320C31 DifferencesTable F-2. TMS320C31 Reserved Memory LocationsDeviceFeature TMS320C31 TMS320C30OxOOOOOO-OxOOOFFF Reservedt Microcomputer program/data ROM modetOx800000-0x801FFF Reserved Expansion bus MSTRB spaceOx804000-0x80SFFF Reserved Expansion bus IOSTRB spaceOx808050 Reserved SP1 global-control registerOx8080S2-0x8080S6 Reserved SP1 local-control registersOx808058 Reserved SP1 data-transmit bufferOx8080SC Reserved SP1 receive-transmit bufferOx808060 Reserved Expansion bus control registertApplies to the MCBL and Me modes only.F.1.4Effects on the IF and IE Interrupt RegistersThe bits associated with serial port 1 in the IE (interrupt enable) register andthe IF (interrupt flag) register for the TMS320C30 are not applicable to theTMS320C31. Write only logic 0 data to IE register bits 6, 7, 22, and 23 and toIF register bits 6 and 7. Writing logic 1 s to these bits produces unpredictableresults.F.1.SUser Program/Data ROMThe user program/data ROM that is available for the TMS320C30 device doesnot exist for the TMS320C31 . Rather, the memo ry locations that were allocatedto support user program/data ROM operations have been reserved on theTMS320C31 to support microcomputer/boot loader accessing. See Chap~er 3 for more information on tJsing the microcomputer/boot loader function.F.1.6Development ConsiderationsFor users who are developing application code using a TMS320C3x simulator,XDS, or ASM/LNK, TI recommends that you modify the .efm and .emdfiles byremoving these memory spaces from the tool's configured memory. This ensuresthat your developed application performs as expected when theTMS320C31 device is used.F-3
TMS320C3x ArchitectureF.2 TMS320C3x ArchitectureFigure F-1. TMS320C3x Block DiagramFigure F-1 and Figure F-2 showthe TMS320C3x's register-based CPU architecturewith internal and external buses, peripherals, DMA, and memory organization.ROYHOLDHOLDASTRBRIW031-0A23-0RESETINT3-0 ----.lACKXF1-0 ~MCBUMP ~EX1 4----1 CX2/CLKIN ----. 8VOO ----.Vss ----.SHZ ----.ProgramCache(64 x 32)Integer/Floating-PointMultiplierRAM Block 0(1K x 32)CPUInteger/Floating-PointALU8 Extended-PrecisionRegistersAddress AddressGenerator 0 Generator 18 Auxiliary Registers12 Control RegistersRAM Block 1(1K x 32): ROMBlockO .(4Kx32)Address GeneratorsControl RegistersAvailable onTMS320C30,TMS320C30-27 andTMS320C30-40F-4Quick Reference
TMS320C3x ArchitectureFigure F-2. TMS320C3x Block DiagramCACHE(64 X 32)RAMBlock 0(1KX32)RAMBlock 1(1KX32)-l-~RESET-'~INT3-0-'lACK 4-MC/MP-.XF(1.0)+tVOO(3-0)-'IOOVOO(1.0)-.AOVOO(1.0)-.POVoo-'OOVOO(1 .0) __MOVoo __" 32 t24CoNTRollERVSS(3-0) --.OVSS(3-O)~CVSS(1.0)-+IVSS-+VBBP4-SUBS-+X14-X2/ClKIN-+H14-H34-EMU6-0'-'RSV10-O~i--/MUX,32 24 24 32 2432-BitMultiplier BarrelShifterL-~---J.r-IA~L~U--i~40 t40 ~====;-:lf}:::~ ... .f::::I---\-""":"'1-1 Extended I ~40 Precision32 Registers ~H(R7-RO) ~-----:~ARAUO BK ARAU124~':t?':t?3232~4Au~iliary II 4Registers(ARO-AR7)f+-\-
F.3 CPU Register FileThe TMS320C30 provides 28 registers in a multiport register file that is tightlycoupled to the CPU. The PC is not included in the 28 registers. <strong>Al</strong>l of these registerscan be operated upon by the multiplier and ALU and can be used as general-purpose32-bit registers.F.3.1Register AddressingThe TMS320C30 provides 28 registers in a multiport register file that is tightlycoupled to the CPU. The PC is not included in the 28 registers. <strong>Al</strong>l of these registerscan be operated upon by the multiplier and ALU and can be used as general-purpose32-bit registers.Table F-3. CPU Register/Assembler Syntax and FunctionCPU Register Assembler AssignedAddress Syntax FunctionOOh RO Extended-precision register01h R1 Extended-precision register02h R2 Extended-precision register03h R3 Extended-precision register04h R4 Extended-precision registerOSh RS Extended-precision register06h R6 Extended-precision register07h R7 Extended-precision register08h ARO Auxiliary register09h AR1 Auxiliary registerOAh AR2 Auxiliary registerOBh AR3 Auxiliary registerOCh AR4 Auxiliary registerODh AR5 Auxiliary registerOEh AR6 Auxiliary registerOFH AR7 Auxiliary register10h DP Data-page pointer11 h IRO Index register 012h IR1 Index register 113h BK Block-size register14h SP Active stack pointer1Sh ST Status register16h IE CPU/DMA interrupt enable17h IF CPU interrupt flags18h 10F I/O flags19h RS Repeat start address1Ah RE Repeat end address1Bh RC Repeat counterF-6 Quick Reference
CPU Register FileFigure F-3. Extended-Precision Register Floating-Point Formate I s I fractionFigure F-4. Extended-Precision Register Integer Format39 32 31 30 0(ij I.. ~-------- mantissa -------~J39 32 31 oI unchanged I signed or unsigned integerThe eight 32-bit auxiliary registers (ARD-AR7) can be modified by the twoAuxiliary Register Arithmetic Units (ARAUs). The primary function of the auxiliaryregisters is the generation of 24-bit addresses, especially for use in indirectaddressing.Figure F-S. Data-Page Pointer (DP) Register Format31x ... x8 7 opageFigure F-6. Index Register (IRx) Format3124 23oindexFigure F-7. Block-Size (BK) Register Format31First 1 at Location NN +1 +N0 ... 0 11(N LSBs of BK)oF-7
CPU ~ClrllctClr FileFigure F-B. Status Register31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx15 14 13 12 11 10 9 8 7 6 5 4 3 2 0xx xx I GIE I CC I CE CF xx I RM I OVM I LUF I LV UF I N I z I V I CRIW RIW RIW RIW RIW RlW R/W RIW R/W RIW RIW RIW RIWNOTE:xx = reserved bit.R = read. W = write.Status Register Bits SummaryBit Name Reset Value Functionot C 0 Carry flag.1t V 0 Overflow flag.2t Z 0 Zero flag.3t N 0 Negative flag.4t UF 0 Floating-point underflow flag.5t LV 0 Latched overflow flag.6t LUF 0 Latched floating-paint underflow flag.7 OVM 0 Overflow mode flag. This flag affects only the integer operations. If OVM= 0, the overflow mode is turned off; integer results that overflow aretreated in no special way. If OVM = 1,a) integer results overflowing in the positive direction are set to themost positive 32-bit twos-complement number (7FFFFFFFh)b) integer results overflowing in the negative direction are set to themost negative 32-bit twos-complement number (80000000h).Note that the function of V and LV is independent of the setting of OVM.8 RM 0 Repeat mode flag. If RM = 1 , the PC is being modified in either therepeat-block or repeat-single mode.9 Reserved 0 Read as O.10 CF 0 Cache freeze. When CF = 1, the cache is frozen. If the cache is enabled(CE = 1), fetches from the cache are allowed, but no modification of thestate of the cache is performed. This function can be used to save frequentlyused code resident in the cache. At reset, 0 is written to this bit.Cache clearing (CC=1) is allowed when CF=O.11 CE 0 Cache enable. CE = 1 enables the cache, allowing the cache to be usedaccording to the least recently used (LRU) cache algorithm. CE = 0 disablesthe cache; no update or modification of the cache can be performed.No fetches are made from the cache. This function is useful forsystem debug. At system reset, 0 is written to this bit. Cache clearing(CC = 1) is allowed when CE=O.12 CC 0 Cache clear. CC = 1 invalidates all entries in the cache. This bit is alwayscleared after it is written to and thus always read as O. At reset, 0 is writtento this bit.13 GIE 0 Global interrupt enable. If GIE = 1, the CPU responds to an enabled interrupt.If GIE = 0, the CPU does not respond to an enabled interrupt.15-14 Reserved 0 Read as O.31-16 Reserved 0-0 Value undefined.t The seven condition flags (ST bits 6 -0) are defined in Section 10.2 on page 10-9.F-8 Quick Reference
CPUFileFigure F-9. CPUIDMA Interrupt Enable Register (IE)31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16RJW RJW RJW RJW RJW RJW RJW ANI ANI RNI ANINOTE: xx = reserved bit. read as o.R = read. W = write.RJW ANI RJW RJW RNI RNI RNI RJW RNI RNIIE Register Bits SummaryBit Name Reset Value Functiona EINTO a Enable external interrupt a (CPU)1 . EINT1 a Enable external interrupt 1 (CPU)2 EINT2 a Enable external interrupt 2 (CPU)3 EINT3 a Enable external interrupt 3 (CPU)4 EXINTO a Enable serial-port 0 transmit interrupt (CPU)5 ERINTO a Enable serial-port 0 receive interrupt (CPU)6 EXINT1 0 Enable serial-port 1 transmit interrupt (CPU)7 ERINT1 a Enable serial-port 1 receive interrupt(CPU)8 ETINTO a Enable timer a interrupt (CPU)9 ETINT1 a Enable timer 1 interrupt (CPU)10 EOINT a Enable OMA controller interrupt (CPU)15-11 Reserved a Value undefined16 EINTO a Enable external interrupt a (OMA)17 EINT1 a Enable external interrupt 1 (OMA)18 EINT2 a Enable external interrupt 2 (OMA)19 EINT3 0 Enable external interrupt 3 (OMA)20 EXINTO a Enable serial-port 0 transmit interrupt (OMA)21 ERINTO a Enable serial-port a receive interrupt (OMA)22 EXINT1 a Enable serial-port 1 transmit interrupt (OMA)23 ERINT1 a Enable serial-port 1 receive interrupt (OMA)24 ETINTO a Enable timer 0 interrupt (OMA)25 ETINT1 a Enable timer 1 interrupt (OMA)26 EOINT a Enable OMA controller interrupt (OMA)31-27 Reserved 0-0 Value undefinedF-9
CPU f-{or"f/ct.::lr FileFigure F-1 O. CPU Interrupt Flag Register (IF) .31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16xx xx xx xx xx xx xx xx xx xxNOTE: xx = reserved bit, read as o.R = read, W = write.IF Register Bits SummaryBit Name Reset Value Function0 INTO 0 External interrupt 0 flag1 INT1 0 External interrupt 1 flag2 INT2 0 External interrupt 2 flag3 .INT3 0 External interrupt 3 flag4 XINTO 0 Serial-port 0 transmit interrupt flag5 RINTO 0 Serial-port 0 receive interrupt flag6 XINT1t 0 Serial-port 1 transmit interrupt flag7 RINT1t 0 Serial-port 1 receive interrupt flag8 TINTO 0 Timer 0 interrupt flag9 TINT1 0 Timer 1 interrupt flag10 DINT 0 DMA channel interrupt flag31-11 Reserved 0-0 Value undefinedt Reserved on TMS320C31.F-10 Quick Reference
CPU R~tlic::t.Qr FileFigure F-11. liD Flag Register (IOF)31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16lulululululululul xx xx xx I xx I xx. xx xx I xx I15 14 13 12 11 10 9 8 7 6 5 4 3 2 0NOTE: xx = reserved bit. read as O.R = read, W = write.R RJW RJW R RNJ RJWIOF Register Bits SummaryBit Name Reset Value Function0 Reserved 0 Read as O.1 I/OXFO 0 If YOXFO = 0, XFO is configured as a general-purpose input pin.If I/OXFO = 1, XFO is configured as a general-purpose output pin.2 OUTXFO 0 Data output on XFO.3 INXFO 0 Data input on XFO. A write has no effect.4 Reserved 0 Read as O.5 I/OXF1 0 If YOXF1 = 0, XF1 is configured as a general-purpose input pin.If I/OXF1 = 1, XF1 is configured as a general-purpose output pin.6 OUTXF1 0 Data output on XF1.7 INXF1 0 Data input on XF1. A write has no effect.31-8 Reserved 0-0 Read as O.F-11
Memory MapsF.4 Memory MapsFigure F-12. TMS320C30 Memory MapsThe TMS320C3x memory map is divided into the following sections: programinterrupt address, internal ROM, RAM,· the peripheral bus, and memorymappedperipheral registers.OhOBFhOCOh7FFFFFh800000h801FFFh802000h803FFFh804000h805FFFh80S000h807FFFh808000hInterrupt Locationsand Reserved (192)External STRB ActiveExternalSTRB Active~nsionBusMSTRB Active (8K)Reserved(8K)~sionBusIOSTRB Active (8K)Reserved(8K)OhOBFhOCOhOFFFh1000h7FFFFFh800000h801FFFh802000h803FFFh804000h805FFFh80S000h807FFFh808000hInterrupt Locationsand Reserved (192)~---------ROM(Internal)ExternalSTRB Active~nsionBusMSTRB Active (8K)Reserved(8K)~sionBusIOSTRB Active (8K)Reserved(8K)Peripheral BusMemory-MappedRegisters(Internal) (SK)Peripheral BusMemory-MappedRegisters(Internal) (SK)8097FFh809800h809BFFh809COOh809FFFh80AOOOhOFFFFFFhRAM Block 0(1 K) (Internal)RAM Block 1(1 K) (Internal)ExternalSTRB Active8097FFh809800h809BFFh809COOh809FFFh80AOOOhOFFFFFFhRAM Block 0(1 K) (Internal)RAM Block 1(1 K) (Internal)ExternalSTRB Active(a) Microprocessor Mode(b) Microcomputer ModeF-12Quick Reference
Figure F-13. TMS320C31 Memory MapsOhOBFhOCOhInterrupt Locationsand Reserved (192)(External STRB Active)OhReserved for BootLoader Operations(See Section 3.4)ExternalSTRB ActiveFFFh1000h400000h"= Boot 1{JIff Boot 2 mIlExternalSTRBActive7FFFFFh800000h807FFFh808000h8097FFh809800h809BFFh809COOh809FFFh80AOOOhFFFFFFhReserved(32K Words)Peripheral BusMemory-MappedRegisters(6K Internal)RAM Block 0(1 K Internal)RAM Block 1(1 K Internal)ExternalSTRB Active7FFFFFh800000h807FFFh808000h8097FFh809800h809BFFh809COOh809FCOh80A9F1h809FFFh80AOOOhFFFOOOhFFFFFFhReserved(32K Words)Peripheral BusMemory-MappedRegisters(6K Internal)RAM Block 0(1 K Internal)RAM Block 1(1 K-64 Internal)User Program Interruptand Trap Branches(64 Internal)iF? Boot 3 'iIIExternalSTRBActive(a) Microprocessor Mode(b) Microcomputer/Boot Loader ModeF-13
Memory Maps~;O::-':S::~;:;-':~::::~;:~-':;-'::;:;-'::"';:;:~"I.;'.::::::"'.::::"';:";:::::"'f.;,;q.::::::%::'I.::::::::::::;::~.:::::::O:'.:::"'Y.-:,(.:::::~.:::'(-,:::'o:(~.:'-:::,O::::::::::::::::::::: ....::'(.::::q,-.(
Figure F-15. Reset, Interrupt, and Trap Vector Format31 24 23 aaddressReset and Interrupt Vector LocationsReset or Vector Priority FunctionInterrupt LocationRESET Oh a External reset signal input on the RESETpin.INTO 1h 1 External interrupt input on the INTO pin.INT1 2h 2 External interrupt input on the INT1 pin.INT2 3h 3 External interrupt input on the INT2 pin.INT3 4h 4 External interrupt input on the INT3 pin.XINTO 5h 5 Internal interrupt generated when serial porta transmit buffer is empty.RINTO 6h 6 Internal interrupt generated when serial porta receive buffer is full.XINT1t 7h 7 Internal interrupt generated when serial port1 transmit buffer is empty.RINT1t 8h 8 Internal interrupt generated when serial port1 receive buffer is full.TINTO 9h 9 Internal interrupt generated by timer O.TINT1 OAh 10 Internal interrupt generated by timer 1.DINT aSh 11 Internal interrupt generated by DMA controllerO.tReserved on TMS320C31.F-15
F.4.2Peripheral BusFigure F-16. Peripheral-Bus Memory-Map Registers808000h80800Fh808010h80801Fh808020h80802Fh808030h80803Fh808040h80804Fh808050h80805Fh808060h80806Fh808070h8097FFhDMA Controller Registers(16)Reserved(16)Timer 0 Registers(16)Timer 1 Registers(16)Serial-Port 0 Registers(16)Serial-Port 1 Registerst(16)Primary and Expansion PortRegisters (16)ReservedtReserved on TMS320C31F-16 Quick Reference
F.4.2.1DMA RegistersFigure F-17. Memory-Mapped Locations for a DMA ChannelRegisterDMA Global Control (See Table 8-7)ReservedReservedReservedDMA Source Address (subsection 8.3.2)ReservedDMA Destination Address (subsection 8.3.2)ReservedDMA Transfer Counter (subsection 8.3.3)ReservedReservedReservedReservedReservedReservedReservedPeripheralAddress808000h808001h808002h808003h808004h808005h808006h808007h808008h808009h80800Ah80800Bh80800Ch80800Dh80800Eh80800FhF-17
Memory Maps~;~~~;!:'::!;:;:;:::;:~;~":;~'~:::;:::>":':;::::!:~::;:::::::".:~-::':;::::::S::::,:::::c:;-,>,:-:::::::,:;:;:::o:::~::~::::::::::;:::;:~~:s:::::".(.::::~-:~:;::~.::,::::::::::::~;x;:::~;::::::*::::::" .. ~,::::~:::-::::.::::~:~:;~:;:;:::::::~.:~:-:::::::::::;'~::::::"o':""£~:::::;:::::%::~Y.'::'):;,::::o-:::%~::?";oX-.. ':"::~%,t;:::y'~~::~:':~~';~':Y/o:::::;:;-;::·;*.X-;"';7.>::::::::::::~;·;'S·:·.:::~;~·~~:%~~::~~ ·~:::;:::;::::~::"/.-::-:;:;:::;~·:::":·~-';:::::::""~:*;';?;~/o7;~~:""'''';7.'-:--'':::::~..;Figure F-18. DMA Global-Control Register Format31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16I xx I xx I xx I xx I xx xx xx I xx xx xx xx xx xx xx xx xx15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0xx xx xx xx I TCINTI TC SYNC I DECDSTI INCDST I DECSRC I INCSRC I STAT STARTRIW RIW RIW RIW RIW RIW RIW RIW R R RIW RIWNOTE: xx = Reserved bit, read as O.R = read, W = write.DMA Global-Control Register Bits SummaryBit Name Reset Value Function1-0 START 0-0 These bits control the state in which the DMA starts and stops. TheDMA may be stopped without any loss of data.3-2 STAT 0-0 These bits indicate the status of the DMA and change every cycle.4 INCSRC 0 If INCSRC = 1 , the source address is incremented after every read.5 DECSRC 0 If DECSRC = 1, the source address is decremented after everyread. If INCSRC = DECSRC, the source address is not modified aftera read.6 INCDST 0 If INCDST = 1, the destination address is incremented after everywrite.7 DECDST 0 If DECDST = 1, the destination address is decremented after everywrite. If INCDST = DECDST, the destination address is not modifiedafter a write.9-8 SYNC 0-0 The SYNC bits determine the timing synchronization between theevents initiating the source and the destination transfers. The interpretationof the SYNC bits is shown on next page.10 TC 0 The TC bit affects the operation of the transfer counter. If TC = 0,transfers are not terminated when the transfer counter becomeszero. If TC = 1, transfers are terminated when the transf~r counterbecomes zero.11 TCINT 0 If TCINT = 1, the DMA interrupt is set when the transfer countermakes a transition to zero.lfTCINT = 0, the DMA interrupt is not setwhen the transfer counter makes a transition to zero.31-12 Reserved 0-0 Read as zero.F-18 Quick Reference
DMA Global-Control Register Bits Summary (Concluded)STARTSTART Bits and Operation of the DMA (Bits 0-1)Function00 DMA read or write cycles in progress will be completed; any data read will be ignored.Any pending read or write will be canceled. The DMA is reset so that whenit starts, a new transaction begins; i.e., a read is performed. (Reset value)01 If a read or write has begun, it is completed before it stops: for example, in themiddle or at the end of a DMA transfer. If a read or write has not begun, no reador write is started.1 0 If a DMA transfer has begun, the entire transfer is completed (including both readand write operations) before stopping. If a transfer has not begun, none is started.1 1 DMA starts from reset or restarts from the previous state.STATSTAT Bits and Status of the DMA (Bits 2-3)Function00 DMA is being held between DMA transfer (between a write and read). This is thevalue at reset. (Reset value)01 DMA is being held in the middle of a DMA transfer, i.e., between a read and a write.1 0 Reserved.1 1 DMA busy; i.e., DMA is performing a read or write.SYNCSYNC Bits and Synchronization of the DMA (Bits 8-9)Function00 No synchronization. Enabled interrupts are ignored. (Reset value)01 Source synchronization. A read is performed when an enabled interrupt occurs.1 0 Destination synchronization. A write is performed when an enabled interrupt occurs.1 1 Source and destination synchronization. A read is performed when an enabled interruptoccurs. A write is then performed when the next enabled interrupt occurs.F-19
F.4.2.2Peripheral TimersFigure F-19. Memory-Mapped Timer LocationsRegisterPeripheral AddressTimer 0 Timer 1Timer Global Control (See Table 8-1) 808020h 808030hReserved 808021h 808031hReserved 808022h 808032hReserved 808023h 808033hTimer Counter (See subsection 8.1.2) 808024h 808034hReserved 808025h 808035hReserved 808026h 808036hReserved 808027h 808037hTimer Period (See subsection 8.1.2) 808028h 808038hReserved 808029h 808039hReserved 80802Ah 80803AhReserved 80802Bh 80803BhReserved 80802Ch 80803ChReserved 80802Dh 80803DhReserved 80802Eh 80803EhReserved 80802Fh 80803FhF-20 Quick Reference
Figure F-20. Timer Global-Control Register31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16I xx I xx I xx I xx I xx xx xx xx xx xx I xx I xx I xx xx xx xx15 14 13 12 ·11 10 9 8 7 6 5 4 3 2 1 0I xx I xx I xx I xx I TSTAT I INV I CLKSRC I C/P HLD GO I xx I xx I DATIN DATOUT T/o FUNCR/W R/W R/W R/W R/W RIW R R/W R/W RIWNOTE:xx = reserved bit, read as O.R = read, W = write.Timer Global-Control Register Bits SummaryBits Name Reset Value Function0 FUNC 0 FUNC controls the function ofTCLK.lf FUNC = 0, TCLK is configuredas a general-purpose digital I/O port. If FUNC = 1, TCLK is configuredas a timer pin (see Figure 8-7 for a description of the relationshipbetween FUNC and CLKSRC).1 T/o 0 If FUNC = 0 and CLKSRC =: 0, TCLK is configured as a general-purposeI/O pin. In this fase, if 110 = 0, TCLK is configured as a generalpurposeinput pin. If I/O = 1 , TCLK is configured as a general-purposeoutput pin.2 DATOUT 0 DATOUT drives TCLK when the TMS320C3x is in I/O port mode.DATOUT can also be used as an input to the timer.3 DATIN x Data input on TCLK or DATOUT. A write has no effect.5-4 Reserved 0-0 Read as O.6 GO a The GO bit resets and starts the timer counter. When GO = 1 and thetimer is not held, the counter is zeroed and begins incrementing on thenext rising edge of the timer input clock. The GO bit is cleared on thesame riSing edge. GO = a has no effect on the timer.7 HLD a Counter hold signal. When this bit is zero, the counter is disabled andheld in its current state. If the timer is driving TCLK, the state of TCLKis also held. The internal divide-by-two counter is also held so that thecounter can continue where it left off when HLD is set to 1. The timerregisters can be read and modified while the timer is being held.RESET has priority over HLD. Table 8-2 shows the effect of writingto GO and HLD.8 C/P 0 Clock/Pulse mode control. When C/P = 1, clock mode is chosen, andthe signaling of the status fLag and external output will have a 50percent duty cycle. When C/P = 0, the status flag and external outputwill be active for one H1 cycle during each timer period (seeFigure 8-4).9 CLKSRC a Specifies the source of the timer clock. When CLKSRC = 1, an internalclock with frequency equal to one-half the H 1 frequency is used to incrementthe counter. The INV bit has no effect on the internal clocksource. When CLKSRC = 0, an external signal from the TCLK pin canbe used to increment the counter. The external clock is synchronizedinternally, thus allowing external asynchronous clock sources that donot exceed the specified maximum allowable external clock frequency.This will be less than f(H1 )/2. (See Figure 8-7 for a description ofthe relationship between FUNC and CLKSRC).F-21
Timer Global-Control Register Bits Summary (Continued)Bits101131-12Name Reset Vallie FunctionINV 0 Inverter control bit. If an external clock source is used and INV = 1, theexternal clock is inverted as it goes into the counter. If the output of thepulse generator is routed to TCLK and INV= 1, the output is invertedbefore it goes to TCLK (see Figure 8-1). If INV = 0, no inversion isperformed on the input or output of the timer. The INV bit has no effect,regardless of its value, when TCLK is used in 110 port mode.TSTAT 0 This bit indicates the status of the timer. It tracks the output of theuninverted TCLK pin. This flag sets a CPU interrupt on a transition fromo to 1 . A write has no effect.Reserved 0-0 Read as O.The result of a write using specified values of the GO and HLD bits in the globalcontrol register is shown below.Result of a Write of Specified Values of GO and HLDGO HLD Result0 0 <strong>Al</strong>l timer operations are held. No reset is performed. (Reset value)0 1 Timer proceeds from state before write.1 0 <strong>Al</strong>l timer operations are held, including zeroing of the counter. The GO bitis not cleared until the timer is taken out of hold.1 1 Timer resets and starts.F-22Quick Reference
F.4.3Serial PortFigure F-21. Memory-Mapped Serial-Port LocationsRegisterPeripheral AddressSerialSerialPort 0Port 1tSerial-Port Global Control 808040h 808050hReserved 808041h 808051hFSX/DX/CLKX Port Control 808042h 808052hFSR/DR/CLKR Port Control 808043h 808053hR/X Timer Control 808044h 808054hR/X Timer Counter 808045h 808055hR/X Timer Period 808046h 808056hReserved 808047h 808057hData Transmit 808048h 808058hReserved 808049h 808059hReserved 80804Ah 80805AhReserved 80804Bh 80805BhData Receive 80804Ch 80805ChReserved 80804Dh 80805DhReserved 80804Eh 80805EhReserved 80804Fh 80805Fht Reserved locations on the TMS320C31F-23
Figure F-22. Serial-Port Global-Control Register Format31 30 29 28 27 26 24 23 22 21 20 19 18 17 16XLENR/W RIW RIW RIW RIW RIW RIW R/W RIW R/W R/W RIWR/W RNI RIW R/W RIW R/W RIW R/W RIW R/W RIW R R R/W R RNOTE: xx = Reserved bit, read as O.R = read, W = write.Serial-Port Global-Control Register Bits SummaryBit Name Reset Value Function0 RRDY 0 If RRDY = 1 , the receive buffer has new data and is ready to be read. A three H1 IH3cycle delay occurs from the reading of ORR to RRDY = 1. The rising edge of this signalsets RINT. If RRDY= 0 at reset, the receive buffer does not have new data since thelast read. RRDY = 0 at reset and after the receive buffer is read.1 XRDY 1 If XRDY = 1 , the transmit buffer has written the last bit of data to the shifter and is readyfor a new word. A three H1 IH3 cycle delay occurs from the loading of the transmit shifteruntil XROY is set to 1. The riSing edge of this signal sets XINT. If XROY = O,thetransmit buffer has not written the last bit of data to the transmit shifter and is not readyfor a new word. XRDY = 1 at reset.2 FSXOUT 0 This bit configures the FSX pin as an input (FSXOUT = 0) or an outpuXFSXOUT = 1).3 XSREMPTY 0 If XSREMPTY = 0, the transmit shift register is empty. If XSREMPTY = 1 , the transmitshift register is not empty. Reset or XRESET causes this bit to = O.4 RSRFULL 0 If RSRFULL = 1, an overrun of the receiver has occurred. In continuous mode,RSRFULL is set to 1 when both RSR and ORR are full. In noncontinuous mode,RSRFULL is set to 1 when RSR and ORR are full and a new FSR is received. A readcauses this bit to be set to O. This bit can be set to 0 only by a system reset, a serialport receive reset (RRESET =1), or a read. When the receiver tries to set RSRFULLto a 1 at the same time that the global register is read, the receiver will dominate andRSRFULL is set to 1. If RSRFULL = 0, no overrun of the receiver has occurred.5 HS 0 If HS = 1 , the handshake mode is enabled. If HS = 0, the handshake mode is disabled.6 XCLKSRCE 0 If XCLKSRCE = 1 , the internal transmit clock is used. If XCLKSRCE = 0, the externaltransmit clock is used.7 RCLKSRCE 0 If RCLKSRCE = 1, the internal receive clock is used. If RCLKSRCE = 0, the externalreceive clock is used.8 XVAREN 0 This bit specifies fixed (XVAREN = 0) or variable (XVAREN = 1) data rate signalingwhen transmitting. With a fixed data rate, FSX is active for at least one XCLK cycleand then goes inactive before transmission begins. With variable data rate, FSX isactive while all bits are being transmitted. When you use an external FSX and variabl edata rate signaling, the OX pin is driven by the transmitter when FSX is held activeor when a word is being shifted out.9 RVAREN 0 This bit specifies fixed (RVAREN = 0) or variable (RVAREN = 1) data rate signalingwhen receiving. With a fixed data rate, FSR is active for at least one RCLK cycle andthen goes inactive before the reception begins. With variable data rate, FSR is activewhile all bits are being received.F-24 Quick Reference
Serial-Port Global-Control Register Bits Summary (Continued)Bit Name Reset Value Function10 XFSM°Transmitframe sync mode. Configures the portfor continuous mode operation(XFSM= 1) or standard mode (XFSM = 0). In continuous mode, only the first word of a blockgenerates a sync pulse, and the rest are simply transmitted continuously to the endof the block. In standard mode, each word has an associated sync pulse.11 RFSM 0 Receive frame sync mode. Configures the port for continuous mode (RFSM =1) orstandard mode (RFSM = 0) operation. In continuous mode, only the first word of ablock generates a sync pulse, and the rest are simply received continuously withoutexpectation of another sync pulse. In standard mode, each word received has anassociated sync pulse.12 CLKXP 0 CLKX polarity. If CLKXP = 0, CLKX is active high. If CLKXP = 1, CLKX is active low.13 CLKRP 0 CLKR polarity. If CLKRP = 0, CLKR is active high. If CLKRP =1 , CLKR is active low.14 DXP 0 DX polarity. If DXP = 0, DX is active high. If DXP = 1, DX is active low.15 DRP°DR polarity. If DRP = 0, DR is aCtive high. If DRP = 1, DR is active low.16 FSXP 0 FSX polarity. If FSXP = 0, FSX is active high. If FSXP = 1, FSX is active low.17 FSRP 0 FSR polarity. If FSRP = 0, FSR is active high. If FSRP = 1, FSR is active low.19-18 XLEN 00 These two bits define the word length of serial data transmitted. <strong>Al</strong>l data is assumedto be right-justified in the transmit buffer when fewer than 32 bits are specified.o 0 --- 8 bits 1 0--- 24 bitso 1 --- 16 bits 1 1 --- 32 bits21-20 RLEN 00 These two bits define the word length of serial data received. <strong>Al</strong>l data is right-justifiedin the receive buffer.o 0 --- 8 bits 1 0--- 24 bitso 1 --- 16 bits 1 1 --- 32 bits22 XTINT 0 Transmit timer interrupt enable. If XTINT = 0, the transmit timer interrupt is disabled.If XTINT = 1 , the transmit timer interrupt is enabled.23 XINT°Transmit interrupt enable. If XINT = 0, the transmit interrupt is disabled. If XINT = 1,the transmit interrupt is enabled. Note that the CPU transmit interrupt flag XINT is thelogical OR of the enabled transmit timer interrupt and the enabled transmit interrupt.24 RTINT 0 Receive timer interrupt enable. If RTINT = 0, the receive timer interrupt is disabled.If RTINT = 1 , the receive timer interrupt is enabled.25 RINT26 XRESET°°Receive interrupt enable. If RINT = 0, the receive interrupt is disabled. If RINT = 1 , thereceive interrupt is enabled. Note that the CPU receive interrupt flag RINT is the ORof the enabled receive timer interrupt and the enabled receive interrupt.Transmit reset. If XRESET = 0, the transmit side of the serial port is reset. To take thetransmit side of the serial port out of reset, set XRESETto 1. However, do not set XRE-SET to 1 until at least three cycles after XRESET goes inactive. This applies only tosystem reset. Setting XRESET to 0 does not change the contents of any of the serialportcontrol registers. It places the transmitter in a state corresponding to the beginningof a frame of data. Resetting the transmitter generates a transmit interrupt. Resetthis bit during the time the mode of the transmitter is set. XFSM can be toggled withoutresetting the global-control register.F-25
Serial-Port Global-Control Register Bits Summary (Concluded)Bit Name Reset Value Function27 RRESETReceive reset. If RRESET = 0, the receive side of the serial port is reset. To take the° receive side of the serial port out of reset, set RRESET to 1. Setting RRESET to °does not change the contents of any of the serial-port control registers. It places thereceiver in a state corresponding to the beginning of a frame of data. Reset this bitat the same time the mode of the receiver is set. RFSM can be toggled without resettingthe global-control register.31-28 Reserved 0-0 Read as O.F-26 Quick Reference
F.4.4FSX/OX/CLKX Port Control RegisterFigure F-23. FSXlDXlCLKX Port Control Register31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx15 14 13 12 11 10 9 8 7 6 5 4 3 2 0NOTE: xx = reserved bit, read as O.R = read, W = write.R RIW RIW RIW R R/W RIW R/W R R/W RIW R/WFSX/OX/CLKX Port Control Register Bits SummaryBit Name Reset Value Function0 CLKXFUNC 0 CLKXFUNC controls the function of CLKX. 'It CLKXFUNC = 0, CLKX is configuredas a general-purpose digital I/O port. If CLKXFUNC = 1, CLKX is aserial port pin.1 CLKXI/O a if CLKX 110 = 0, CLKX is configured as a general-purpose input pin. If CLKXI/O = 1, CLKX is configured as a general-purpose output pin.2 CLKXDATOUT a Data output on CLKX.3 CLKXDATIN x Data input on CLKX. A write has no effect.4 DXFUNC 0 DXFUNC controls the function of OX. If DXFUNC = 0, OX is configured asa general-purpose digital I/O port. If DXFUNC = 1, OX is a serial port pin.S OX I/O 0 If OX 110 = 0, OX is configured as a general-purpose input pin.If OX I/O = 1, OX is configured as a general-purpose output pin.6 DXDATOUT 0 Data output on DX.7 DXDATIN x Data input on DX. A write has no effect.8 FSXFUNC 0 FSXFUNC controls the function of FSX. If FSXFUNC = 0, FSX is configuredas a general-purpose digital I/O port. If FSXFUNC = 1, FSX is a serial portpin.g FSX 110 0 If FSX Tlo = 0, FSX is configured as a general-purpose input pin.If FSX 110 = 1, FSX is configured as a general-purpose output pin.10 FSXDATOUT 0 Data output on FSX.11 FSXDATIN x Data input on FSX. A write has no effect.31- 12 Reserved 0-0 Read as O.F-27
F.4.SFSR/DR/CLKR Port Control RegisterFigure F-24. FSRIDRICLKR Port Control Register31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx15 14 13 12 11 10 8 7 6 5 4 3 2 0NOTE: xx = reserved bit, read as O.R = read, W = write.R RIW RNI RIW R RfW RNI R/W R RNI RNI RNIFSR/OR/CLKR Port Control Register Bits SummaryBit Name Reset Value Function0 CLKRFUNC 0 CLKRFUNC controls the function of CLKR. If CLKRFUNC = 0, CLKR isconfigured as a general-purpose digital 1/0 port. If CLKRFUNC = 1,CLKR is a serial port pin.1 CLKR1/0 0 If CLKR!/O = 0, CLKR is configured as a general-purpose input pin.If CLKRI/O = 1, CLKR is configured as a general-purpose output pin.2 CLKRDATOUT 0 Data output on CLKR.3 CLKRDATIN x Data input on CLKR. A write has no effect.4 DRFUNC 0 DRFUNC controls the function of DR. If DRFUNC = 0, DR is configuredas a general-purpose digital 1/0 port. If DRFUNC = 1, DR is a serial portpin.'5 DR 1/0 0 If DRI/O = 0, DR is configured as a general-purpose input pin.If DRIIO = 1, DR is configured as a general-purpose output pin.6 DRDATOUT 0 Data output on DR.7 DRDATIN x Data input on DR. Awrite has no effect.8 FSRFUNC 0 FSRFUNC controls the function of FSR. If FSRFUNC = 0, FSR is configuredasa general-purpose digital 1/0 port. If FSRFUNC = 1, FSR is aserial port pin.g FSR 1/0 0 If FSR TIO = 0, FSR is configured as a general-purpose input pin. If FSR110 = 1,FSR is configured as a general-purpose output pin.10 FSRDATOUT 0 Data output on FSR.11 FSRDATIN x Data input on FSR. A write has no effect.31-12 Reserved 0-0 Read as O.F-28 Quick Reference
F.4.6Receive/Transmit Timer Control RegisterFigure F-25. ReceivelTransmit Timer Control Register31 30 29I xx I xx I28 27 26 25I xx xx xx xx24 23 22xx xx xx21 20 19 18 17 16xx xx xx xx xx xx15 14 13I xx I xx I xxNOTE:12 11 10 9I xx I RTSTAT xx I RCLKRCRRIWXX,= reserved bit, read as O.R = read, W = write.7 6RC/P RHLD RGORIW R RIWReceive/Transmit Timer Control RegisterBit Name Reset Value Function5 3 2 1 0XTSTAT xx I XCLKSRC I XC/P I XHLD XGOR/W R RIW RIW RIW0 XGO 0 The XGO bit resets and starts the transmit timer counter. When XGOis set to 1 and the timer is not held, the counter is z6iOed and beginsincrementing on the next rising edge of the timer input clock. The XGObit is cleared on the same rising edge. Writing 0 to XGO has no effecton the transmit timer.1 XHLD 0 Transmit counter hold signal. When this bit is set to 0, the counter is disabledand held in its current state. The internal divide-by-two counteris also held so that the counter will continue where it left off when XHLDis set to 1. The timer registers may be read and modified while the timeris being held. RESET has priority over XHLD.2 XC/P°XClockiPulse mode control. When XC/P = 1, theclockmodeis chosen.The signaling of the ~atus flag and external output has a 50-percentduty cycle. When XC/P = 0, the status flag and external output are activefor one CLKOUT cycle during each timer period.3 XCLKSRC 0 This bit specifies the source of the transmit timer clock. WhenXCLKSRC = 1, an internal clock with frequency equal to one-half theCLKOUTfrequency is used to increment the counter. When XCLKSRC= 0, an external signal from the CLKX pin can be used to increment thecounter. The external clock source is SYNChronized internally, thus allowingfor external aSYNChronous clock sources that do not exceedthe specified maximum allowable external clock frequency, i.e., lessthan f(H1 )/2.6.4 Reserved 0 Read as zero.5 XTSTAT 0 This bit indicates the status of the transmit timer. It tracks what wouldbe the output of the uninverted CLKX pin. This flag sets a CPU interrupton a transition from ° to 1 . A write has no effect.F-29
ReceivelTransmit Timer Control Register (Concluded)Bit Name Reset Value Function.6 RGO 0 The RGO bit resets and starts the receive timer counter. When RGOis set to 1 and the timer is not held, the counter is zeroed and beginsincrementing on the next rising edge of the timer input clock. The RGObit is cleared on the same rising edge. Writing 0 to RGO has no effecton the receive timer.7 RHLD 0 Receive counter hold signal. When this bit is set to 0, the counter is disabledand held in its current state. The internal divide-by-two counteris also held so that the counter will continue where it left off when RHLDis set to 1. The timer registers may be read and modified while the timeris being held. RESET has priority over RHLD.8 RC/P 0 RClockiPulse mode control. When RC/P = 1, the clock mode is chosen.The signaling of the slatus flag and external output has a 50-percentduty cycle. When RC/P = 0, the status flag and external output are activefor one CLKOUT cycle during each timer period.9 RCLKSRC 0 This bit specifies the source of the receive timer clock. When RCLKSRC= 1, an internal clock with frequency equal to one-half the CLKOUT frequencyis used to increment the counter. When RCLKSRC = 0, an externalsignal from the CLKR pin can be used to increment the counter.The external clock source is SYNChronized internally, thus allowing forexternal aSYNChronous clock sources that do not exceed the specifiedmaximum allowable external clock frequency, i.e., less than f(Hi )/2.6.10 Reserved 0 Read as zero.11 RTSTAT 0 This bit indicates the status of the receive timer. It tracks what would bethe output of the uninverted CLKR pin. This flag sets a CPU interrupton a transition from 0 to 1. A write has no effect.31-12 Reserved 0-0 Read as O.F-30 Quick Reference
F.4.7Primary-Bus and Expansion-Bus ControlFigure F-26. Memory-Mapped External Interface Control RegistersRegisterExpansion Bus Control (See sUbsection 7.1.2)tReservedReservedReservedPrimary Bus Control (See subsection 7.1.1)ReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedPeripheralAddress808060h808061h808062h808063h808064h808065h808066h808067h808068h808069h80806Ah80806Bh80806Ch80806Dh80806Eh80806FhtReserved on the TMS320C31F-31
F.4.8Primary-Bus Control RegisterFigure F-27. Primary-Bus Control Register12 11 10 9 8BNKCMPR/W RlW R/W R/W R/W R/W R/W R/W R/W R/W R/WNOTE: xx = reserved bit, read as O.R = read, W = write ..Primary-Bus Control Register Bits SummaryBit Name Reset FunctionValue0 HOLDST x Hold status bit. This bit signals whether the port is being held(HOLDST = 1) or is not being held (HOLDST = 0). This status bit isvalid whether the port has been held via hardware or software.1 NOHOLD 0 Port hold signal. NOHOLD allows or disallows the port to be held byan external HOLD signal. When NOHOLD = 1 , the TMS320C3x takesover the external bus and controls it, regardless of serviced or pendingrequests by external devices. No hold acknowledge (HOLDA) is assertedwhen a HOLD is received. However, it is asserted if an internalhold is generated (HIZ = 1). NOHOLD is set to 0 at reset.2 HIZ 0 Internal hold. When set (HIZ = 1), the port is put in hold mode. Thisis equivalent to the external HOLD signal. By forcing a high-impedancecondition, the TMS320C3x can relinquish the external memoryport through software. HOLDA goes low when the port is placed in thehigh-impedance state. HIZ is set to 0 at reset.4-3 SWW 11 Software wait mode. In conjunction with WTCNT, this 2-bit field definesthe mode of wait-state generation. It is set to 1 1 at reset.7-5 WTCNT 111 Software wait mode. This 3-bit field specifies the number of cycles touse when in software wait mode for the generation of internal waitstates. The range is zero (WTCNT = 0 0 0) to seven (WTCNT = 1 11)H1/H3 cycles. It is set to 1 1 1 at reset.12-8 BNKCMP 10000 Bank compare. This 5-bit field specifies the number of MSBs of theaddress to be used to define the bank size. It is set to 1 0000 at reset.31 -13 Reserved 0-0 Read as O.F-32 Quick Reference
F.4.9Expansion-Bus Control RegisterFigure F-28. Expansion-Bus Control Register31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16I xx I xx I xx I xx I xx I xx I xx I xx I xx I xx I xx I xx I xx I xx I xx I xx II xx I xx I xx I xx I xx I xx I xx I xx I WTCNT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0NOTE: xx = reserved bit, read as O.R = read, W = write.R/W R/W R/W R/lvV R/WSWW I xx I xx I xx IExpansion-Bus Control Register Bits SummaryBit2-04-37-531-8Name Reset FunctionValueReserved 000 Read as O.SWW 11 Software wait-state generation. In conjunction with the WTCNT,this 2-bit field defines the mode of wait-state generation. It is setto 1 1 at reset.WTCNT 111 Software wait mode. This 3-bit field specifies the number of cyclesto use when in software wait mode for the generation of internalwait states. The range is zero (WTCNT = 0 0 0) to seven( WTCNT = 1 1 1) H 1 /H3 clock cycles. It is set to 1 1 1 at reset.Reserved 0-0 Read as O.F-33
F.4.10 Programmable Bank SwitchingTable F-4. BNKCMP and Bank SizeBNKCMP MSBs Defining a Bank Bank Size (32-Bit Words)00000 None 224= 16M00001 23 223= 8M00010 23-22 222= 4M00011 23-21 221 = 2M00100 23-20 220= 1M00101 23-19 219= 512K00110 23-18 2 18 = 256K00111 23-17 217 = 128K01000 23-16 2 16 = 64K01001 23-15 2 15 = 32K01010 23-14 2 14 16K01011 23-13 2 13 = 8K01100 23-22 212= 4K01101 23-11 211 = 2K01110 23-12 2 1O =1K01111 23-910000 23-82 9 5122 8 = 25610000 -11111 Reserved UndefinedF-34 Quick Reference
Instruction SetF.5 Instruction SetF.S.1Instruction FormatsTable F-S. Indirect AddressingMod Field Syntax Operation DescriptionIndirect Addressing with Displacement00000 *+ARn(disp) addr = ARn + disp With predisplacement add00001 *- ARn(disp) addr = ARn - disp With predisplacement subtract00010 *++ARn(disp) addr = ARn + disp With predisplacement add and modifyARn = ARn + disp00011 *- - ARn(disp) addr = ARn - disp With predisplacement subtract and modifyARn = ARn - disp00100 * ARn++( disp) addr = ARn With postdisplacement add and modifyARn = ARn + disp00101 *ARn - - (disp) addr = ARn With postdisplacement subtract and modifyARn = ARn - disp00110 * ARn++(disp)% addr = ARn With postdisplacement add and circularARn = circ(ARn + disp) modify00111 * ARn - - (disp)% add = ARn With postdisplacement subtract andARn = circ(ARn - disp) circular modify01000 *+ARn(IRO) addr = ARn + IRO01001 *- ARn(IRO) addr = ARn -IRO01010 *++ARn(IRO) addr = ARn + IROARn = ARn + IRO01011 * - - ARn(IRO) addr = ARn -IROARn = ARn -IRO01100 *ARn++(IRO) addr = ARnARn = ARn + IRO01101 *ARn -- (IRO) addr= ARnARn = ARn - IROIndirect Addressing with Index Register IRO01110 *ARn++(IRO)% addr = ARnARn = circ(ARn + IRO)01111 * ARn - - (lRQ)% addr = ARnARn = circ(ARn) - IROLEGEND:addr memory addressARn auxiliary register ARQ - AR7IRn index register IRO or IR1disp displacement++ add and modifysubtract and modifycirc( ) address in circular addressing% where circular addressing is performedWith preindex (IRO) addWith preindex (IRO) subtractWith preindex (IRO) add and modifyWith preindex (IRO) subtract and modifyWith postindex (IRO) add and modifyWith postindex (IRO) subtract and modifyWith postindex (lRO) add and circularmodifyWith postindex (IRQ) subtract and circularmodifyF-35
Instruction SetTable F-S.Indirect Addressing (Concluded)Mod Field10000100011001010011101001010110110101111100011001LEGEND:addrARnIRndisp++circ( )BSyntax Operation DescriptionIndirect Addressing with Index Register IR1*+ ARn(IR1) addr = ARn + IR1 With preindex (IR1) add* - ARn(IR1) addr = ARn - IR1 With preindex (IR1) subtract* ++ ARn(IR1) addr ARn + IR1 With preindex (IR1) addARn = ARn + IR1and modify* --ARn(IR1) addr ARn - IR1 With preindex (IR1) subtractARn = ARn - IR1and modify* ARn ++ (IR1) addr = ARn With postindex (IR1) addARn = ARn + IR1and modify*ARn--(IR1) addr = ARn With postindex (IR1) subtractARn = ARn - IR1and modify* ARn ++ (IR1)% addr ARn With postindex (IR1) addARn = circ(ARn + IR1) and circular modify* ARn -- (IR1)% addr = ARn With postindex (IR1) subtractARn = circ(ARn -IR1) and circular modify*ARn*ARn ++ (IRO)BIndirect Addressing (Special Cases)addr = ARnIndirectaddr = ARnARn = B(ARn + IRO)memory addressauxiliary register ARO - AR7index register IRO or IR1displacementadd and modifysubtract and modifyaddress in circular addressingwhere circular addressing is performedwhere bit-reversed addressing is performedWith postindex (IRO) addand bit-reversed modifyF-36Quick Reference
Instruction SetF.S.2SummaryTable F-6. Instruction Set SummaryMnemonicABSFABSIADDCADDC3ADDFADDF3ADDIADDI3ANDAND3ANDNANDN3ASHASH3BcondBcondDDescriptionAbsolute value of a floating-point numberAbsolute value of an integerAdd integers with carryAdd integers with carry (3-operand)Add floating-point valuesAdd floating-point values (3-operand)Add integersAdd integers (3-operand)Bitwise logical-AN DBitwise logical-AND (3-operand)Bitwise logical-AND with complementBitwise logical-ANDN (3-operand)Arithmetic shiftArithmetic shift (3-operand)Branch conditionally (standard)Branch conditionally (delayed)Isrcl ----1 RnIsrcl ----1 DregOperationsrc + Dreg + C ----1 Dregsrc1 + src2 + C ----1 Dregsrc + Rn ----1 Rnsrc1 + src2 -7 Rnsrc + Dreg -7 Dregsrc1 + src2 + ----1 DregDreg AND src ----1 Dregsrc1 AND src2 ----1 DregDreg AND src ----1 Dregsrc1 AND src2 ----1 DregIf count 2: 0:(Shifted Dreg left by count) ----1 DregElse:(Shifted Dreg right by Icount!) ----1 DregIf count 2: 0:(Shifted src left by count) ----1 DregElse:(Shifted src right by Icount!) ----1 DregIf cond = true:If Csrc is a register, Csrc ----1 PCIf Csrc is a value, Csrc + PC ----1 PCElse, PC + 1 ----1 PCIf cond = true:If Csrc is a register, Csrc ----1 PCIf Csrc is a value, Csrc + PC + 3 ----1 PCElse, PC + 1 ----1 PCLEGEND:srcsrc1src2CsrcSregcountSPGIERMTOSgeneral addressing modesthree-operand addressing modesthree-operand addressing modesconditional-branch addressing modesregister address (any register)shift value (general addressing modes)stack pointerglobal interrupt enable registerrepeat mode bittop of stackDregRnDaddrARnaddrcondSTRERSPCCregister address (any register)register address (R7 - RO)destination memory addressauxiliary register n (AR7 - ARO)24-bit immediate address (label)condition code (see Chapter 11)status registerrepeat interrupt registerrepeat start registerprogram countercarry bitF-37
Instruction SetTable F-6.Instruction Set Summary (Continued)Mnemonic Description OperationBR Branch unconditionally (standard) Value -7 PCBRD Branch unconditionally (delayed) Value -7 PCCALL Call subroutine PC + 1 -7 TOSValue -7 PCCALLcond Call subroutine conditionally If cond = true:PC + 1 -7 TOSIf Csrc is a register, Csrc -7 PCIf Csrc is a value, Csrc + PC -7 PCElse, PC + 1 -7 PCCMPF Compare floating-point values Set flags on Rn - srcCMPF3Compare floating-point values(3-operand)Set flags on src1 - src2CMPI Compare integers Set flags on Dreg - srcCMPI3 Compare integers (3-operand) Set flags on src1 - src2\DBcond Decrement and branch conditionally ARn -1 -7 ARn(standard)If cond = true and ARn 2:: 0:If Csrc is a register, Csrc -7 PCIf Csrc is a value, Csrc+ PC + 1 -7 PCElse, PC + 1 -7 PCDBcondD Decrement and branch conditionally ARn -1 -7 ARn(delayed)If cond = true and ARn 2:: 0:If Csrc is a register, Csrc -7 PCIf Csrc is a value, Csrc + PC + 3 -7 PCElse, PC + 1 -7 PCFIX Convert floating-point value to integer Fix (src) -7 DregFLOAT Convert integer to floating-point value Float(src) -7 RnlACK Interrupt acknowledge Dummy read of srclACK toggled low, then highIDLE Idle until interrupt PC + 1 -7 PCIdle until next interruptLDE Load floating-point exponent src(exponent) -7 Rn(exponent)LDF Load floating-point value src -7 RnLDFcond Load floating-point value conditionally If cond = true, src -7 RnElse, Rn is not changedLDFI Load floating-point value, interlocked Signal interlocked operation src -7 RnLDI Load integer src -7 DregLDlcond Load integer conditionally If cond = true, src -7 DregElse, Dreg is not changedF-38 Quick Reference
Instruction SetTable F-6.Instruction Set Summary (Continued)MnemonicLDIILDMLSHLSH3MPYFMPYF3MPYIMPYI3NEGBNEGFNEGINOPNORMNOTOROR3POPPOPFPUSHDescriptionLoad integer, interlockedLoad floating-point mantissaLogical shiftLogical shift (3-operand)Multiply floating-point valuesMultiply floating-point value (3-operand)Multiply integersMultiply integers (3-operand)Negate integer with borrowNegate floating-point valueNegate integerNo operationNormalize floating-point valueBitwise logical-complementBitwise logical-ORBitwise logical-OR (3-operand)Pop integer from stackPop floating-point value from stackPush integer on stackOperationSignal interlocked operation src -7 Dregsrc (mantissa) -7 Rn (mantissa)If count ~ 0:(Dreg left-shifted by count) -7 DregElse:(Dreg right-shifted by Icount!) -7 DregIf count ~ 0:(src left-shifted by count) -7 DregElse:(src right-shifted by Icount!) -7 Dregsrc x Rn -7 Rnsrc1 X src2 ~ Rnsrc X Dreg ~ Dregsrc1 X src2 -7 DregO-src-C ~ DregO-src ~ Rn0- src ~ DregModify ARn if specifiedNormalize (src) ~ Rnsrc ~ DregDreg OR src -7 Dregsrc1 OR src2 ~ Dreg*SP--~ Dreg·SP---7 RnSreg ~ *++ SPLEGEND:srcsrc1src2CsrcSregcountSPGIERMTOSgeneral addressing modesthree-operand addressing modesthree-operand addressing modesconditional-branch addressing modesregister address (any register)shift value (general addressing modes)stack pointerglobal interrupt enable registerrepeat mode bittop of stackDregRnDaddrARnaddrcondSTRERSPCCregister address (any register)register address (R7 - RO)destination memory addressauxiliary register n (AR7 - ARO)24-bit immediate address (label)condition code (see Chapter 11)status registerrepeat interrupt registerrepeat start registerprogram countercarry bitF-39
Instruction SetTableF-6.Instruction Set Summary (Continued)Mnemonic Description OperationPUSHF Push floating-point value on stack Rn -7 *++ SPRETlcond Return from interrupt conditionalfy If cond = true or missing:*SP---7 PC1 -7 ST (GIE)Else, continueRETScond Return from subroutine conditionalfy If cond = true or missing:*SP---7 PCElse, continueRND Round floating-point value Round (src) -7 RnROL Rotate left Dreg rotated left 1 bit -7 DregROLC Rotate left through carry Dreg rotated left 1 bit through carry -7 DregROR Rotate right Dreg rotated right 1 bit -7 DregRORC Rotate right through carry Dreg rotated right 1 bit through carry -7DregRPTB Repeat block of instructions src -7 RE1 -7 ST (RM)Next PC -7 RSRPTS Repeat single instruction src -7 RC1 -7 ST (RM)Next PC -7 RSNext PC -7 RESIGI Signal, interlocked Signal interlocked operationWait for interlock acknowledgeClear interlockSTF Store floating-point value Rn -7 DaddrSTFI Store floating-point value,interlocked Rn -7 DaddrSignal end of interlocked operationSTI Store integer Sreg -7 DaddrSTI! Store integer, interlocked Sreg -7 DaddrSignal end of interlocked operationSUBB Subtract integers with borrow Dreg - src - C -7 DregSUBB3 Subtract integers with borrow (3-operand) src1 - src2 - C -7 DregSUBC' Subtract integers conditionalfy If Dreg - src ~ 0:[(Dreg - src) « 1] OR 1 -7 DregElse, Dreg « 1 -7 DregF-40 Quick Reference
Instruction SetTable F-6.Instruction Set Summary (Concluded)MnemonicSUBFSUBF3SUB ISUBI3SUBRBSUBRFSUBRISWITRAPcondTSTBTSTB3XORXOR3DescriptionSubtract floating-point valuesSubtract floating-point values (3-operand)Subtract integersSubtract integers (3-operand)Subtract reverse integer with borrowSubtract reverse floating-point valueSubtract reverse integerSoftware interruptTrap conditionallyTest bit fieldsTest bit fields (3-operand)Bitwise exclusive-ORBitwise exclusive-OR (3-operand)Rn - src -:7 Rnsrc1 - src2 -:7 RnDreg - src -:7 Dregsrc1 - src2 -:7 DregOperationsrc - Dreg - C -:7 Dregsrc - Rn -:7 Rnsrc - Dreg -:7 DregPerform emulator interrupt sequenceIf cond = true or missing:Next PC -:7 * ++ SPTrap vector N -:7 PC0-:7 ST (GIE)Else, continueDreg AND srcsrc1 AND src2Dreg XOR src -:7 Dregsrc1 XOR src2 -:7 DregLEGEND:srcsrc1src2CsrcSregcountSPGIERMTOSgeneral addressing modesthree-operand addressing modesthree-operand addressing modesconditional-branch addressing modesregister address (any register)shift value (general addressing modes)stack pointerglobal interrupt enable registerrepeat mode bittop of stackDregRnDaddrARnaddrcondSTRERSPCCregister address (any register)register address (R7 - RO)destination memory addressauxiliary register n (AR7 - ARO)24-bit immediate address (label)condition code (see Chapter 11)status registerrepeat interrupt registerrepeat start registerprogram countercarry bitF-41
Instruction SetTable F-7.Parallel Instruction Set SummaryMnemoniclDescription IOperationParallel Arithmetic With Store InstructionsABSF Absolute value of a floating-point Isrc21 ~ dst1II STFII src3 ~ dst2ABSI Absolute value of an integer Isrc21 ~ dst1IISTIII src3 ~ dst2ADDF3 Add floating-point src1 + src2 ~ dst1II STFII src3 ~ dst2ADDI3 Add integer src1 + src2 ~ dst1IISTIII src3 ~ dst2AND3 Bitwise logical-AND src1 AND src2 ~ dst1IISTIII src3 ~ dst2ASH3 Arithmetic shift If count ~ 0:II STIsrc2 « count ~ dst1II src3 ~ dst2Else:src2 » Icountl ~ dst1II src3 ~ dst2FIX Convert floating-point to integer Fix(src2) ~ dst1II STIII src3 ~ dst2FLOAT Convert integer to floating-point Float(src2) ~ dst1II STFII src3 ~ dst2LDF Load floating-point src2 ~ dst1II STFII src3 ~ dst2LDI Load integer src2 ~ dst1II STIII src3 ~ dst2LSH3 Logical shift If count ~ 0:II STIsrc2 « count ~ dst1II src3 ~ dst2Else:src2 » Icountl ~ dst1II src3 ~ dst2MPYF3 Multiply floating-point src1 x src2 ~ dst1II STFII src3 ~ dst2MPYI3 Multiply integer src1 x src2 ~ dst1IISTIII src3 ~ dst2NEGF Negate floating-point 0- src2 ~ dst1II STFII src3 ~ dst2F-42 Quick Reference
Instruction SetTable F-7.Parallel Instruction Set Summary (Concluded)Mnemonic Description OperationNEGIIISTINOTII STIOR3II STISTF.11 STFSTIIISTISUBF3II STFSUBI3II STIXOR3II STILDFII LDFLDIII LDIMPYF3II ADDF3MPYF3II SUBF3MPYI3II ADDI3MPy'13II SUBI3Negate integerComplementParallel Arithmetic With Store Instructions (Concluded)Bitwise logical-ORStore floating-pointStore integerSubtract floating-pointSubtract integerBitwise exclusive-ORLoad floating-pointLoad integerParallel Load Instructionsa - src2 --7 dst1II src3 --7 dst2src1 -7 dst1II src3 -7 dst2src1 OR src2 -7 dst1II src3 -7 dst2src1 -7 dst1II src3 -7 dst2src1 -7 dst1II src3 -7 dst2src1 - src2 -7 dst1II src3 -7 dst2src1 - src2 -7 dst1II src3 -7 dst2src1 XOR src2 -7 dst1II src3 -7 dst2src2 -7 dst1II src4 -7 dst2src2 -7 dst1II src4 -7 dst2Parallel Multiply And Add/Subtract InstructionsMultiply and add floating-pointMultiply and subtract floating-pointMultiply and add integerMultiply and subtract integerop1 x op2 -7 op3II op4 + op5 -7 op6op1 x op2 -7 op3II op4 - op5 -7 op6op1 x op2 -7 op3II op4 + op5 -7 op6op1 x op2 -7 op3II op4 - op5 -7 op6LEGEND:src1src3dst1op3register addr (R7 - RO)register addr (R7 - RO)register addr (R7 - RO)register addr (RO or R1)src2src4dst2op6indirect addr (disp = 0, 1, IRO, IR1)indirect addr (disp = 0, 1, IRa, IR1)indirect addr (disp = 0, 1, IRa, IR1)register addr (R2 or R3)op1 ,op2,op4,opS - Two of these operands must be specified using register addr, and two must be specifiedusing mdirect.F-43
F-44 Quick Reference
A-law compression, 11-51A-law expansion, 11-52adaptive filters, 11-61addition example, 11-35addressesA23-AO signalsadditional capacitance, 12-38timing requirements, 12-38XA 12-XAO signalsadditional capacitance, 12-38timing requirements, 12-38addressing modesconditional branch, 2-14, 5-23general, 5-19long-immediate, 2-14, 5-22parallel, 2-14, 5-21three operand, 2-14, 5-20addressing types, 5-2direct addressing, 5-4immediate, 5-17indirect addressing, 5-5-5-16PC relative, 5-18register, 5-3, F-6analysis subsystempod dimensions, 12-40use with debugging tools, 12-37applicationsgeneral listing, 1-7hardware, 12-1software, 11-1architecture, 2-1archiver, B-3arithmetic logic unit (ALU), 2-5arithmetic operations, 11-21assembler, B-3assembly language instructions, 10-1categories, 10-3-10-8interlocked operation, 10-6load and store, 10-3parallel operation, 10-6program control, 10-5three-operand, 10-5two-operand, 10-4coding hints, 11-88condition codes, flags, 10-9condition for execution, 10-9example instruction, 10-16opcodes, A-1register syntax, 10-15symbols used to defi ne, 1 0-12-1 0-15syntax options, 10-13-10-15auxiliary (ARO-AR7) registers, 3-4auxiliary register ALUs, 2-5IIbank switching, external bus, 7-29, 12-12bit manipulation, 11-21bit-reversed addressing, 5-29, 11-23block move, 11-23block repeat register (RS,RE), 3-11block size (BK) register, 3-5branches, 6-7delayed, 6-7,11-15bulletin board, B-13bus operationexternal, 2-23internal, 2-22busy-waiting example, 6-12C (HLL) routines, 11-88Index-1
IndexC compilerfeatures, 8-3hosts supported, 8-5optimization, 8-4cachehit, 3-20miss, 3-21cache memory, 2-9, 3-19See also memoryalgorithm, 3-20architecture, 3-19control bits, 3-22instruction cache, 3-19calls, 6-8capacitance of electrical probe, 12-38cautions, viiicentral processing unit, 2-3circular addressing, 5-24CLKR pins, 8-18, F-28CLKX pins, 8-17, F-27clock oscillator circuitry, 12-25clocksadditional capacitance, 12-38Hi, 12-38, 12-39H3, 12-38, 12-39timing requirements, 12-39companding, 11-48compressionA-law, 11-51/l-Iaw, 11-49condition codes, flags, 10-11conditional delayed branches, 6-7conditional-branch addressing modes, 2-14, 5-23context switching, 11-11conversionfloating point to integer, 4-22integer to floating point, 4-24counter example, 6-12counter register (timer), 8-2, 8-6CPU, 2-3CPU interrupt flag register (IF), interrupt flag (IF),3-9CPU registers, 2-6auxiliary (ARO-AR7), 2-7, 3-4block repeat (RS, RE), 3-11block size (BK), 2-7, 3-5CPU/OMA interrupt enable (IE), 3-8data page pointer, 2-7data page pointer (OP), 3-5extended precision (RO-R7), 2-6, 3-4I/O flags (IOF), 2-7, 3-10index (IR1, IRO), 2-7, 3-5interrupt enable (IE), 2-7, 3-8interrupt flag (IF), 2-7, 3-9list of, 3-3program counter (PC), 2-8, 2-22, 3-11repeat count (RC), 2-8, 6-2repeat count (RP), 3-11repeat end address (RE), 2-8,3-11,6-2repeat start address (RS), 2-8, 3-11, 6-2reserved bits, 3-11, 'status register (ST), 2-7, 3-5, 10-10system stack pointer (SP), 2-7, 3-5CPU1/2 buses, 2-22data031-00 signalsadditional capacitance, 12-38timing requirements, 12-38X031-XOO signalsadditional capacitance, 12-38timing requirements, 12-38data page pointer (OP) register, 3-5data receive register (serial port), 8-22data transmit register (serial port), 8-21delayed branches, 6-7,11-15advantages, 11-89incorrectly placed, 6-6, 6-7design considerations, 12-37-12-42electrical informationcapacitance of electrical probe, 12-38power supply loading of active probe, 12-38mechanical dimensions, 12-40timing information, Pages, 12-38dimensions (chip), 13-15direct addressing, 5-4disabled interrupts by branch,"6-7displacements, 5-5-5-16division, 11-24OMAarchitecture, 2-26buses, 2-22channel synchronization, 8-49-8-51Index-2
Indexcontroller, 8-38destination/source address register, 8-42general, 2-26global control register, 8-39interrupt enable register, 8-42memory transfer, 8-44-8-48synchronization of channels, 8-49-8-51transfer counter register, 8-42OMA global-control register format, F-18OMA interrupt enable register (IE), 3-2documentation, v, 8-13DR pins, 8-18, F-28OX pins, 8-17, F-27edge-triggered interrupts, 6-20electrical characteristics, 13-18electrical informationcapacitance of electrical probe, 12-38power supply loading of active probe, 12-38electrical specifications, 13-17EMUO-EMU6 signalsadditional capacitance, 12-38timing requirements, 12-39emulator, in system overvie'w, 12-37event counters, 8-2expansionA-law, 11-52Il-Iaw, 11-50expansion busSee also external busesaddresses, 12-38data, 12-38reads/writes, 12-39signal timing, 12-38extended precisionaddition example, 11-35floating-point format, 4-6multiplication example, 11-36subtract example, 11-35external buses (expansion, primary), 2-23, 7-1bank switching, 7-29,12-12expansion bus control register, 7-4expansion bus I/O cycles, 7-10-7-26expansion bus interface, 12-18external interrupts, 2-23interlocked instructions, 2-23primary bus control register, 7-3primary bus interface, 12-4ready generation, 12-8timingexpansion bus, 7-10-7-26primary bus, 7-5-7-9wait states, 7-27,12-4,12-8external devices, 12-3external interfaces, 12-2fast Fourier transforms, 11-66FFT,11-66filtersadaptive, 11-61FIR,11-53IIR,11-55lattice, 11-82LMS algorithm, 11-61FIR filters, 11-53floating pointaddition, 4-14conversion to integer, 4-22division, 11-24format conversion, 4-8formats, 4-4IEEE to TMS320, 11-38inverse, 11-27multiplication, 4-10normalization, 4-18normalized,4-14rounding value, 4-20short format, 4-4single-precision format, 4-6square root example, 11-30subtraction, 4-14TMS320 to IEEE, 11-38underflow, 4-15formatsconversion, 4-8floating point, 4-4signed integer, 4-2unsigned integer, 4-3FSR pins, 8-18, F-28FSX pins, 8-17, F-27"Index-3
general addressing modes, 2-14, 5-19global control register (serial port), 8-14global control register (timer), 8-3mglobal memory, 6-10, 6-13H1 signaladditional capacitance, 12-38timing require.ments, 12-39H3 signaladditional capacitance, 12-38timing requirements, 12-39hardware applications, 12-1hardware control, 6-1header (XDS1 000), 12-34HOLDA, signaladditional capacitance, 12-38timing requirements, 12-39hotline, 8-13D1/0 flags register (IOF), 3-10lACK, signaladditional capacitance, 12-38timing requirements, 12-39IIR filters, 11-55immediate addressing, 5-17index (IRO,IR1) register, 3-5indirect addressing, 5-5initialization (processsor), 11-3instruction cache, 3-19instruction register (IR), 2-22instruction set summaryalphabetical, 2-14function listing, 10-3instructions. See assembly languageINTO-,NT3, 3-17, F-14INTO-INT3, signalsadditional capacitance, 12-38timing requirements, 12-39integer division, 11-24integer formatsshort integer, 4-2signed,4-2single-:precision integer, 4-2unsigned, 4-3interfacesexpansion bus, 2-23, 12-18primary bus, 2-23, 12-4system control, 12-25types, 12-2interlocked operations, 6-10internal bus, 2-22interrupt enable register (IE), 3-8interrupt service routines, 11-10interrupts, 2-23, 6-20context switching, 11-11control bits, 6-20interrupt service routines, 11-10prioritization, 6-25prioritizing, 11-14processing, 6-27serial ports, 8-27vectors, 3-16, 6-25inverse, 11-27inverse lattice filter, 11-83..lattice filters, 11-82IOSTR8, signal, 7-2, 7-5additional capacitance, 12-38timing requirements, 12-40level-triggered interrupts, 6-20linker, 8-3literature, v, 8-13logical operations, 11-21long-immediate addressing modes, 2-14, 5-22looping, 11-16LRU cache update, 3-19matrix-vector multiplication, 11-64mechanical data, 13-15mechanical dimensions, 12-40memory, 2-9, 3-19accesses (pipeline), 9-21cache, 2-9, 3-19,11-89general organization, 2-9Index-4
Indexglobal, 6-10, 6-13memory maps, 2-11 , 3-12microcomputer mode, 3-12microprocessor mode, 3-12pipeline conflicts, 9-9, 9-19quick access, 11-89microcomputer mode, 2-11,3-12ll-Iaw compression, 11-49~-Iaw expansion, 11-50microprocessor mode, 2-11, 3-12MSTR8, signal, 7-2, 7-5additional capacitance, 12-38timing requirements, 12-40multiple processors, 6-10multiplication, 11-64multiplier, 2-5mnested block repeats, 6-6normalization, floating-point value, 4-14, 4-18object program converter, 8-3opcodes, A-1optimizer (C compiler), 8-4ordering information, 8-15overflow, 4-15,4-22overview; emulation system with analysis subsystem,12-37.parallel addressing modes, 2-14, 5-21part numbers, 8-15breakdown of numbers, 8-18prefix deSignators, 8-16period register (timer), 8-2, 8-6peripheral bus, 2-24, 8-1general architecture, 2-24map, 3-18peripherals on, 8-1DMA controller, 8-38serial port, 2-25, 8-12timers, 2-25, 8-2register diagram, 2-24pin assignments, 13-4, 13-5pin states at reset, 6-16pipeline, 9-1conflictsavoiding, 11-89branching, 9-4memory, 9-9memory (resolving), 9-19registers, 9-6memory accesses, 9-21structure, 9-2power, supply loading of active 'probe, 12-38primary busSee also external busesaddresses, 12-38data, 12-38reads/writes, 12-39signal timing, 12-38primary bus control register, 7-3probesactive probe power-supply loading, 12-38electrical probe capacitance, 12-38program buses, 2-22program counter (PC), 2-22,3-11program flow, 6-1quality, C-1mqueues (stack), 5-32R/W, signaladditional capacitance, 12-38timing requirements, 12-39RAM,2-9See also mem'oryready generation, 12-8receive/transmit timer counter register (serial port),8-21receive/transmit timer period register (serial port),8-21regional technology centers, 8-14register buses, 2-22registers, 2-6auxiliary (ARO-AR7), 2-7, 3-4block repeat (RS. RE), 3-11Index-5
Indexblock size (8K), 2-7, 3-5counter (timer), 8-6CPU/DMA interrupt enable (IE), 3-8, 8-42data page pointer, 2-7data page· pointer (DP), 3-5DMA destination and source address, 8-42DMA global control register, 8-39DMA transfer counter register, 8-42DM<strong>Al</strong>CPU interrupt enable (IE), 8-42extended precision (RO-R7), 2-6, 3-4global control (timer), 8-3I/O flag (IOF), 3-10I/O flags (IOF), 2-7index (IR1, IRO), 3-5interrupt enable (IE), 2-7,3-8interrupt flag (IF), 2-7, 3-9maximum use, 11-89period (timer), 8-6peripheral port, 8-1pipeline conflicts, 9-6program counter (PC), 2-8, 2-22, 3-11repeat count (RC), 2-8, 6-2repeat count (RP), 3-11repeat end address (RE), 2-8, 3-11,6-2repeat start address (RS), 2-8, 3-11, 6-2reserved bits, 3-11serial port global control, 8-14serial port registers, 8-12-8-37status register (ST), 2-7, 3:.5,10-10system stac;k pointer (SP), 2-7, 3-5registers, general, see also CPU registers, 2-5reliability, C-1stress testing, C-2repeat count register (RC), 3-11,6-2repeat en? address register (RE), 3-11,6-2repeat modeinitialization, 6-2RPTS initialization, 6-3repeat modes, 11-16repeat start address register (RS), 3-11, 6-2requirements, signal timing, Pages, 12-38reset, 3-16, 6-16initialization (processor), 11-3operations performed, 6-19pin states, 6-16vectors, 3-16, 6-25. RESET signaladditional capacitance, 12-38timing requirements, 12-39return from subroutine, 6-8RINTO,1, 3-17, F-14ROM,2-9See also memoryrounding of floating-point value, 4-20RTCs, 8-14scan path interface, 8-10segment start address (SSA) reg., 3-19semaphores, 6-13seminars, 8-14serial port, 8-12-8-37data receive register, 8-22data transmit register, 8-21global control register, 8-14interrupt sources, 8-27port control register (FSR/DR/CLKR), 8-18, F-28port control register (FSX/DXlCLKX), 8-17, F-27receive/transmit timer control register, 8-19, F-29receive/transmit timer counter register, 8-21receive/transmit timer period register, 8-21timing, 8-24, 8-28-8-37serial port global control register, 8-14short floating-point format, 4-4signal descriptions, 13-9-13-14signal transition levels, 13-19signals, timing information, Pages, 12-38simulator, 8-5software applications, 11-1software control, 6-1software development, 8-2archiver, 8-3assembler, 8-3emulator (XDS500 & 1000), 8-8linker, 8-3macro assembler, 8-3object format converter, 8-3scan path interface, 8-1 °simulator, 8-5SPOX, 8-6square root example, 11-30stack, 5-30, 5-32, 11-9queues, 5-32stack pointer (SP) register, 3-5status register (ST), 3-5, 10-10Index-6
STRB, signal, 7-2, 7-5additional capacitance, 12-38timing requirements, 12-40style (manual), viisubroutines, 11-7-11-20computed GOTO, 11-20context switching, 11-11runtime select, 11-18subtract example, 11-35symbols (used in manual), viisynchronize 2 processors example, 6-15system overview, 12-37Dtarget cable, 12-37target system, design considerations, 12-37-12-42electrical information, 12-38mechanical dimensions, 12-40timing information, Pages, 12-38target system connection, 12-34TClKO, TClK1 , signalsadditional capacitance, 12-38timing requirements, 12-39test load circuit, 13-18third party support, B-12three-operand addressing modes, 2-14, 5-20timer global control register, 8-3timers, 2-25, 8-2-8-11counter, 8-2counter register, 8-6operation nodes, 8-7period register, 8-2, 8-6timing parameters, 13-20-13-51timing/counting, TMS320C30 signal timing,Pages, 12-38TINTO,1, 3-17, F-14trap, 3-16, 6-8vectors, 3-16TTL levels, 13-19underflow, 4-14vectors (reset, interrupts), 6-25vectors (reset, trap, interrupt), 3-16wait states, 7-27external bus, 12-4, 12-8zero, 12-4workshops, B-14XDS1000, 12-34, 8-8XDS500,8-8XFO, XF1, signalsaddition;:il capacitance, 12-38timing requirements, 12-39XFO,XF1, 2-23XINTO,1, 3-17, F-14XRIW signaladditional capacitance, 12-38timing requirements, 12-39zero wait states, 12-4Index-7
IndexIndex-8
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~TEXASINSTRUMENTSPrinted in U.S.A., June 19912558539-9761 revision ESPRU031B
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