Specman Based Verification Methodology for ... - CiteSeerX
Specman Based Verification Methodology for ... - CiteSeerX Specman Based Verification Methodology for ... - CiteSeerX
ClockOutputaccesstimeFig 5: Read Cycle‣ Coverage:Coverage acts as a feedback loop to improve the input stimulus. A cover plan isdeveloped defining the specific events when the memory signals are to be recorded. Tocover combination of signals cross coverage is used. Transition coverage is defined forClock to generate a coverage report for different Clock transitions (0->1, 0->X, 1->X,etc). A couple of coverage reports are shown below.Fig 6: Coverage report for combination of Address and Memory operation8
Fig 7: Coverage report for Clock transitionsLooking at these coverage reports, one can get an idea about the missing tests and can targetthose tests.Agent:All the above defined blocks are instantiated in the agent. Since for a memory model both thedriving of the stimulus and monitoring the output has to be done by the Memory-eVC the agenthas been declared as active.Env:Env forms the root unit of the Memory eVC. The agent is defined within the env. Whenintegrating different modules of a design, the env’s are combined to create a common env.Single-port env vs. Dual-port envThe only difference between eVCs of single-port and dual-port memories is in the env. In singleportenv only one agent is declared while for dual-port two agents are declared, the two agentsbeing differentiated using an agent_id. When the agent_id is having a value 1, port1 of thememory is accessed and port2 is accessed when agent_id is 2 (accessed here means signals ofthat port are driven and monitored by the eVC). The difference is depicted in the diagram below.9
- Page 4 and 5: 2. Memory eVCAny verification envir
- Page 6 and 7: ‣ Ambiguous testsAmbiguous tests
- Page 10 and 11: envConfig:agent_id = 2Config:agent_
- Page 12: Currently Specman Verification Meth
Fig 7: Coverage report <strong>for</strong> Clock transitionsLooking at these coverage reports, one can get an idea about the missing tests and can targetthose tests.Agent:All the above defined blocks are instantiated in the agent. Since <strong>for</strong> a memory model both thedriving of the stimulus and monitoring the output has to be done by the Memory-eVC the agenthas been declared as active.Env:Env <strong>for</strong>ms the root unit of the Memory eVC. The agent is defined within the env. Whenintegrating different modules of a design, the env’s are combined to create a common env.Single-port env vs. Dual-port envThe only difference between eVCs of single-port and dual-port memories is in the env. In singleportenv only one agent is declared while <strong>for</strong> dual-port two agents are declared, the two agentsbeing differentiated using an agent_id. When the agent_id is having a value 1, port1 of thememory is accessed and port2 is accessed when agent_id is 2 (accessed here means signals ofthat port are driven and monitored by the eVC). The difference is depicted in the diagram below.9
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