Specman Based Verification Methodology for ... - CiteSeerX

‣ Ambiguous testsAmbiguous tests involve testing of the behavior of the Memory when driven withunknowns (i.e., “X”) on inputs. “X” is a state in which the signal could either be “High”or “Low” but undecided.‣ Timing testsTiming tests can be further classified into constraint tests and path delay tests. Each ofthese has been briefly explained below.• Constraint TestsConstraint tests involve checking of the memory timing constraints such assetup/Hold, Pulse width, and Period checks.• Path Delay TestsThese tests are done to verify the access time of the memory.Based on the test plan sequence drivers are defined for each test scenario which generate inputstimulus. The generation of the stimulus is random, but constrained. Let’s take an example tounderstand this. Consider Address pin of the memory, the value for which is generatedrandomly. This might create a situation where all the addresses randomly generated may beoutside the memory range. This will lead to incomplete verification of the memory as it is testedonly for out of range address. So it is important to generate a valid address, which is done bytelling the tool to generate a random address alright, but keep it within the memory range.To generate the stimulus for test cases in which values generated has to be unknown, we haveused Multi Valued Logic (MVL) which is an enumerated data type in Specman. It is a list of ninevalues,[MVL_U, MVL_X, MVL_0, MVL_1, MVL_Z, MVL_W, MVL_L, MVL_H, MVL_N];Of these MVL_0, MVL_1 and MVL_X are used in our memory eVC. The generated stimulus isthen passed on to the Bus Functionality Module.Signal Map:It consists of the list of signals which the eVC has to access when it interacts with the memoryunder test.Bus Functionality Module (BFM):The stimulus generated by the sequence driver must be driven on to the memory inputs, which isdone by the BFM. It will collect the packets (stimulus to all inputs) generated by the sequencedriver and passes it on to the memory inputs one after the other.Monitor:It is a passive unit which records memory signals. It waits for specific events on the memorysignal (like positive edge of Clock) and monitors the memory input and output. Monitor alsodefines checkers and coverage points.6