Specman Based Verification Methodology for ... - CiteSeerX
Specman Based Verification Methodology for ... - CiteSeerX Specman Based Verification Methodology for ... - CiteSeerX
2. Memory eVCAny verification environment is expected to have the following componentsCoverageGenerationof stimulusDriverinputDUToutputCollectOutputTest planExpectedoutputCompareSpecificationResult:Pass/FailFig 1: Verification Environmente allows the creation of the verification environment as an independent, plug and play packagecalled eVC. Each eVC consists of complete set of above mentioned verification blocks. Theabove block diagram can now be simplified asinputDUToutputeVCSpecificationTest planFig 2: Verification environment with eVC4
These eVCs can themselves be used as a verification environment or can be integrated with alarger environment. To use these eVCs as plug and play devices Specman defines a methodologycalled e Reusable Methodology (eRM) which defines guidelines and best-known-methods foreVC development.We have followed the eRM to create a Memory eVC, the structure of which is as belowenvConfig:PassiveMonitorCheckerCoverageActiveSignal mapSequencedriverBFMagentOutputsInputsMemoryFig 3: Memory eVC architectureLet’s take a closer look at each of the above blocksSequence Driver:Sequence driver generates input stimulus that has to be applied to the memory. To generate theinput stimulus a test plan is created looking at the memory specification document. The test planconsists of test scenarios and the expected output for each case. The test scenarios can be broadlyclassified into the following groups‣ Functional testsFunctional tests include the tests that are done to verify the basic memory operations likeRead, Write and Bypass.5
- Page 6 and 7: ‣ Ambiguous testsAmbiguous tests
- Page 8 and 9: ClockOutputaccesstimeFig 5: Read Cy
- Page 10 and 11: envConfig:agent_id = 2Config:agent_
- Page 12: Currently Specman Verification Meth
2. Memory eVCAny verification environment is expected to have the following componentsCoverageGenerationof stimulusDriverinputDUToutputCollectOutputTest planExpectedoutputCompareSpecificationResult:Pass/FailFig 1: <strong>Verification</strong> Environmente allows the creation of the verification environment as an independent, plug and play packagecalled eVC. Each eVC consists of complete set of above mentioned verification blocks. Theabove block diagram can now be simplified asinputDUToutputeVCSpecificationTest planFig 2: <strong>Verification</strong> environment with eVC4
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