Specman Based Verification Methodology for ... - CiteSeerX

More documents

Recommendations

Info

envConfig:agent_id = 2Config:agent_id = 1PassiveMonitorCheckerCoverageSignal map mapActiveSequencedriverBFMagentagentOutputsInputsDual-port MemoryFig 8: Dual Port Memory eVC architectureThis shows the ease with which the eVC of Single-port can be converted to Dual-port.To convert it to a ROM-eVC, the Write enable signal declared in the eVC has to be removed.This saves the time spent on developing separate testbenches for Single-port, Dual-port andROM.3. Conclusion and Future workIn semiconductor industry, time to market and cost of non-quality plays a very important role indeciding the future of the company. Majority of the companies are mainly focused on these twoaspects. Also 60 to 70% of the chip area is occupied by memories. Hence any improvement inquality and turn around time of memories will have a huge impact. Implementation of Specmanbased verification methodology for memory models has helped in reducing the developmenttime. The graph below shows the relative comparison between the development time of Specmanverification environment and HDL testbench. The drastic decrease in development of Specmanverification environment for Dual-port and ROM is due to concept of reusability.10
Development TimeHDL TestbenchSpecman verification envSingle-port Dual-port ROMFig 9: Development Time of HDL Testbench vs SpecmanAlso quality of memory models has improved resulting in reduced cost of non-quality.Number of bugs found in memory modelCost ofNon-qualityTime toMarketHDL TestbenchSpecman verification envTimeFig 10: Benefits of Specman Verification Methodology11
Page 4 and 5: 2. Memory eVCAny verification envir
Page 6 and 7: ‣ Ambiguous testsAmbiguous tests
Page 8 and 9: ClockOutputaccesstimeFig 5: Read Cy
Page 12: Currently Specman Verification Meth

Specman Based Verification Methodology for ... - CiteSeerX

Create successful ePaper yourself

Delete template?

Save as template?