Specman Based Verification Methodology for ... - CiteSeerX

2. Memory eVCAny verification environment is expected to have the following componentsCoverageGenerationof stimulusDriverinputDUToutputCollectOutputTest planExpectedoutputCompareSpecificationResult:Pass/FailFig 1: Verification Environmente allows the creation of the verification environment as an independent, plug and play packagecalled eVC. Each eVC consists of complete set of above mentioned verification blocks. Theabove block diagram can now be simplified asinputDUToutputeVCSpecificationTest planFig 2: Verification environment with eVC4

These eVCs can themselves be used as a verification environment or can be integrated with alarger environment. To use these eVCs as plug and play devices Specman defines a methodologycalled e Reusable Methodology (eRM) which defines guidelines and best-known-methods foreVC development.We have followed the eRM to create a Memory eVC, the structure of which is as belowenvConfig:PassiveMonitorCheckerCoverageActiveSignal mapSequencedriverBFMagentOutputsInputsMemoryFig 3: Memory eVC architectureLet’s take a closer look at each of the above blocksSequence Driver:Sequence driver generates input stimulus that has to be applied to the memory. To generate theinput stimulus a test plan is created looking at the memory specification document. The test planconsists of test scenarios and the expected output for each case. The test scenarios can be broadlyclassified into the following groups‣ Functional testsFunctional tests include the tests that are done to verify the basic memory operations likeRead, Write and Bypass.5

‣ Ambiguous testsAmbiguous tests involve testing of the behavior of the Memory when driven withunknowns (i.e., “X”) on inputs. “X” is a state in which the signal could either be “High”or “Low” but undecided.‣ Timing testsTiming tests can be further classified into constraint tests and path delay tests. Each ofthese has been briefly explained below.• Constraint TestsConstraint tests involve checking of the memory timing constraints such assetup/Hold, Pulse width, and Period checks.• Path Delay TestsThese tests are done to verify the access time of the memory.Based on the test plan sequence drivers are defined for each test scenario which generate inputstimulus. The generation of the stimulus is random, but constrained. Let’s take an example tounderstand this. Consider Address pin of the memory, the value for which is generatedrandomly. This might create a situation where all the addresses randomly generated may beoutside the memory range. This will lead to incomplete verification of the memory as it is testedonly for out of range address. So it is important to generate a valid address, which is done bytelling the tool to generate a random address alright, but keep it within the memory range.To generate the stimulus for test cases in which values generated has to be unknown, we haveused Multi Valued Logic (MVL) which is an enumerated data type in Specman. It is a list of ninevalues,[MVL_U, MVL_X, MVL_0, MVL_1, MVL_Z, MVL_W, MVL_L, MVL_H, MVL_N];Of these MVL_0, MVL_1 and MVL_X are used in our memory eVC. The generated stimulus isthen passed on to the Bus Functionality Module.Signal Map:It consists of the list of signals which the eVC has to access when it interacts with the memoryunder test.Bus Functionality Module (BFM):The stimulus generated by the sequence driver must be driven on to the memory inputs, which isdone by the BFM. It will collect the packets (stimulus to all inputs) generated by the sequencedriver and passes it on to the memory inputs one after the other.Monitor:It is a passive unit which records memory signals. It waits for specific events on the memorysignal (like positive edge of Clock) and monitors the memory input and output. Monitor alsodefines checkers and coverage points.6

‣ Checkers:This unit performs data and temporal (timing) checks which are explained below indetail.• Data Check:To perform data checks the memory output needs to be compared with expectedoutput. The expected output is obtained using scoreboard technique.Scoreboarding is a common verification technique and not e-specific. Here wehave built a reference memory which behaves exactly as per the specification.Any operation performed on the memory under test, is performed on the referencememory also and the output of this reference memory is compared with thememory under test outputREFERNCEMEMORYoutputSeqDriverBFMCompareinputMEMORYUNDER TESToutputFig 4: Reference MemoryTo build a reference memory we need to allocate a static array, but this willconsume huge system memory. To avoid this we are using a dynamically createdkeyed list. When a write operation is performed on the memory under test, theaddress accessed is added to keyed list. When a particular address location iscorrupted due to, say a timing violation then that address location is removedfrom the list.• Temporal Check:These checks involve path delay checks. In the case of memory there are accesstime checks and handshake signal timing checks. To perform these checks thesame timing information which is present in the memory under test, is provided tothe eVC. The monitor is asked to emit an event when there is a change in any ofthe signals involved in these paths. The timings of these events are noted and thencompared with the expected timings.7

ClockOutputaccesstimeFig 5: Read Cycle‣ Coverage:Coverage acts as a feedback loop to improve the input stimulus. A cover plan isdeveloped defining the specific events when the memory signals are to be recorded. Tocover combination of signals cross coverage is used. Transition coverage is defined forClock to generate a coverage report for different Clock transitions (0->1, 0->X, 1->X,etc). A couple of coverage reports are shown below.Fig 6: Coverage report for combination of Address and Memory operation8

Fig 7: Coverage report for Clock transitionsLooking at these coverage reports, one can get an idea about the missing tests and can targetthose tests.Agent:All the above defined blocks are instantiated in the agent. Since for a memory model both thedriving of the stimulus and monitoring the output has to be done by the Memory-eVC the agenthas been declared as active.Env:Env forms the root unit of the Memory eVC. The agent is defined within the env. Whenintegrating different modules of a design, the env’s are combined to create a common env.Single-port env vs. Dual-port envThe only difference between eVCs of single-port and dual-port memories is in the env. In singleportenv only one agent is declared while for dual-port two agents are declared, the two agentsbeing differentiated using an agent_id. When the agent_id is having a value 1, port1 of thememory is accessed and port2 is accessed when agent_id is 2 (accessed here means signals ofthat port are driven and monitored by the eVC). The difference is depicted in the diagram below.9

envConfig:agent_id = 2Config:agent_id = 1PassiveMonitorCheckerCoverageSignal map mapActiveSequencedriverBFMagentagentOutputsInputsDual-port MemoryFig 8: Dual Port Memory eVC architectureThis shows the ease with which the eVC of Single-port can be converted to Dual-port.To convert it to a ROM-eVC, the Write enable signal declared in the eVC has to be removed.This saves the time spent on developing separate testbenches for Single-port, Dual-port andROM.3. Conclusion and Future workIn semiconductor industry, time to market and cost of non-quality plays a very important role indeciding the future of the company. Majority of the companies are mainly focused on these twoaspects. Also 60 to 70% of the chip area is occupied by memories. Hence any improvement inquality and turn around time of memories will have a huge impact. Implementation of Specmanbased verification methodology for memory models has helped in reducing the developmenttime. The graph below shows the relative comparison between the development time of Specmanverification environment and HDL testbench. The drastic decrease in development of Specmanverification environment for Dual-port and ROM is due to concept of reusability.10

Development TimeHDL TestbenchSpecman verification envSingle-port Dual-port ROMFig 9: Development Time of HDL Testbench vs SpecmanAlso quality of memory models has improved resulting in reduced cost of non-quality.Number of bugs found in memory modelCost ofNon-qualityTime toMarketHDL TestbenchSpecman verification envTimeFig 10: Benefits of Specman Verification Methodology11

Currently Specman Verification Methodology has been implemented for Single-port, Dual-portand ROM. Looking at the results now we are planning to extend it for verification of non-volatilememories also.4. AcknowledgementsSpecial thanks to Mr. Raghavendra Rao of Philips Semiconductors and Mr. HaridarshanTirumalai of Cadence Design Systems for their help during the work on this paper. I would alsolike to thank Mr. Navneet Khullar, Philips Semiconductors for his support.5. References[1] “Writing Testbenches” - Janick Bergeron[2] “Design Verification with e” – Samir Palnitkar[3] “e Language Reference”[4] “e Reuse Methodology (eRM) Developer Manual”12