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Signal Integrity and PCB layout considerations for DDR2-800 Mb/s ...

Signal Integrity and PCB layout considerations for DDR2-800 Mb/s ...

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<strong>DDR2</strong> <strong>and</strong> DDR3 NetsCDNLive 2007! Silicon Valley 2


<strong>PCB</strong> Layer Stackup <strong>and</strong> ImpedanceCDNLive 2007! Silicon Valley 4


Interconnect Topologies (ADDR/CMD/CNTRL)CDNLive 2007! Silicon Valley 5


Interconnect Topologies (ADDR/CMD/CNTRL)CDNLive 2007! Silicon Valley 6


DELAY MATCHINGTrombone traceStraight traceL 1 + L 2 + L 3 + L 4 + L 5≠L 1L 2L 3L 4L 5Via cross sectional viewStraight traceL 1≠L 2L 3L 1 + L 2 + L 3CDNLive 2007! Silicon Valley 7


TROMBONE DELAY SIMULATIONCDNLive 2007! Silicon Valley 8


VIA effect on DELAYCDNLive 2007! Silicon Valley 9


Cross talkCDNLive 2007! Silicon Valley 10


Power <strong>Integrity</strong>CDNLive 2007! Silicon Valley 11


TIMING1. Write Setup analysis DQ vs. DQS2. Write Hold analysis DQ vs. DQS3. Read Setup analysis DQ vs. DQS4. Read Hold analysis DQ vs. DQS5. Write Setup analysis DQS vs. CLK*6. Write Hold analysis DQS vs. CLK*7. Write Setup analysis Address/CMD/CNTRL vs. CLK8. Write Hold analysis Address/CMD/CNTRL vs. CLK* Write Leveling in DDR3 eliminates the need <strong>for</strong> 5 <strong>and</strong> 6CDNLive 2007! Silicon Valley 12


TIMING SummaryCDNLive 2007! Silicon Valley 13


<strong>PCB</strong> Layout1. Controller BGA Breakout2. Topology <strong>for</strong> ADDR/CMD/CNTRL3. Decoupling capacitor placement <strong>and</strong> low inductance foot print.CDNLive 2007! Silicon Valley 14


<strong>PCB</strong> Layout continued4. Fine tuning <strong>and</strong> ground viasCDNLive 2007! Silicon Valley 15


DDR3 LAYOUT ExampleCDNLive 2007! Silicon Valley 16


DDR3 Wave<strong>for</strong>ms (1600 <strong>Mb</strong>ps)CDNLive 2007! Silicon Valley 17


<strong>DDR2</strong> LayoutCDNLive 2007! Silicon Valley 18


<strong>DDR2</strong> Wave<strong>for</strong>ms (<strong>800</strong> <strong>Mb</strong>ps)CDNLive 2007! Silicon Valley 19


DDR3 – DIMM LAYOUTCDNLive 2007! Silicon Valley 20


DDR3 – DIMM Wave<strong>for</strong>ms (1600 <strong>Mb</strong>ps) at 8 th SDRAM on DIMMCDNLive 2007! Silicon Valley 21


Conclusion1. Main <strong>DDR2</strong>/DDR3 implementation details have been presented2. ALLEGRO CM usage eases Layout3. <strong>800</strong> <strong>Mb</strong>ps operation on a 4 layer <strong>PCB</strong> √4. 1600 <strong>Mb</strong>ps DDR3 on a 4 layer <strong>PCB</strong> ?For more in<strong>for</strong>mation:Syed Bokhari Tel: 613-828-0063 Ext: 377 Syed.Bokhari@fidus.caAbout Fidus:Fidus Systems Inc. develops electronic products <strong>for</strong> a wide range of industries including;telecommunications, aerospace <strong>and</strong> defence, video, transportation <strong>and</strong> automotiveapplications, storage <strong>and</strong> memory, consumer products, biomedical instrumentation <strong>and</strong>industrial controls. Fidus specializes in complete, turn-key product development, ortargeted design of architecture, hardware, FPGA, RF, software/firmware, circuit board<strong>layout</strong>, signal integrity <strong>and</strong> EMC analysis. Fidus has consulted on more than 500 rightfirst-timeprojects <strong>for</strong> customers across North America <strong>and</strong> Europe. For morein<strong>for</strong>mation, please visit www.fidus.comCDNLive 2007! Silicon Valley 22

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