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AADvance Safety Manual - Tuv-fs.com

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<strong>AADvance</strong> <strong>Safety</strong> <strong>Manual</strong>Test MethodEach function to be tested shall be placed within an application test harness using the<strong>AADvance</strong> tool set that exercises its capabilities. The implementation of this harnessshall be such that the function block is exercised automatically, so that the test isrepeatable.As a minimum each test harness shall include all of the following: The function block under test An alternative implementation of the function block A function generator, to generate the stimuli for the function under test Main and alternative <strong>com</strong>parison Pass/Fail Flag A test results register, that records the functionality of the function blockWhere practical, and with the exception of time, results of the test shall beautomatically recorded and should not require a human to count or record dynamicdata.The alternative implementation of the function being tested shall be performed usingfeatures of the tool set that are as diverse as possible from the actual function block.For example an Or gate can be simulated by counting the number of inputs set to alogical 1 and determining that the count is greater than or equal to 1.The function generator shall be as simple as possible and shall not contain the functionunder test.The results of the alternative implementation shall be <strong>com</strong>pared with the results of thefunction under test; discrepancies shall cause a 'main and alternative <strong>com</strong>parison failflag' to be set.The registration of test results should be as detailed as possible and use as manypredictable features as possible.ExampleA two-input logical Or gate stimulated by the two lower bits of a 16-bit counter willrecord 32768 logical high states if the counter is allowed to make one <strong>com</strong>plete upcount from 0 to 65536. The results register would count these states and present anumber to the human operator. In this case the results register should also record thatno two consecutive states of the counter caused a logical 1 at the output of the gate.5-28 Document number 553630 Issue 7: February 2010

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