HX8347-D - Mikrocontroller.net

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HX8347-D(T)240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver5.2 RGB InterfaceDATA SHEET Preliminary V01The HX8347-D uses RCM [1:0] =’10’ or ‘11’ hardware setting to select RGBinterface. After Power on Sequence, the RGB interface is activated. When RCM [1:0]=’10’ use VSYNC, HSYNC, DE, DOTCLK, DB17-0 parallel lines for the RGB interface(RGB mode 1). When RCM [1:0] =’11’ use VSYNC, HSYNC, DOTCLK, DB17-0 parallellines for the RGB interface (RGB mode 2)Pixel clock (DOTCLK) must be running all the time without stopping and it is used toentering VSYNC, HSYNC, DE and DB17-0 lines states when there is a rising edge ofthe DOTCLK.In RGB interface mode 1, the valid display data is inputted in pixel unit via DB17-0according to the high-level(‘H’) of DE signal, and display operations are executed insynchronization with the frame synchronizing signal (VSYNC), line synchronizing signal(HSYNC) and pixel clock (DOTCLK). In RGB interface mode 2, the valid display data isinputted in pixel unit via DB17-0 according to the HBP setting of HSYNC signal, and theVBP setting of VSYNC. In these two RGB interface modes, the input display data is notwritten to GRAM and is displayed directly.Vertical synchronization (VSYNC) signal is used to tell when there a new frame of thedisplay is received , and this is negative (‘-‘, ‘0’, low) active. Horizontal synchronizationsignal (HSYNC) is used to tell when a new line of the frame is received, and this isnegative (‘-‘, ‘0’, low) active. Data enable (DE) is used to tell when RGB information isreceived that should be transferred on the display, and this is positive (‘+’, ‘1’, high)active. DB17-0 are used to tell what the information of the image is, that is transferredon the display when DE=’H’.The pixel clock cycle is described in the following figure.DOTCLKVSYNCHSYNCDEDB17-0Figure 5.31 DOTCLK cycleHimax ConfidentialThis information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosedin whole or in part without prior written permission of Himax.-P.45-March, 2009
HX8347-D(T)240RGB x 320 dot, 262K color, TFT Mobile Single Chip DriverGeneral timing diagram in RGB interface is as follow.DATA SHEET Preliminary V01Vertical Sync.0 1VBPInvisible Image= Timing information what is not possible to see on the display= Blanking TimeDE = ‘0’ (Low)VPVDISPVisible Image= Image which can see on the display= ActiveDE = ‘1' (high)VFPHorizontal Sync.10HBP HDISP HFPHPFigure 5.32 RGB interface circuit input timing diagramThe image information is correct on the display when the timings are in range on theinterface. However, the image information will be incorrect on the display, when timingsare out of the range on the RGB interface and the correct image information will bedisplayed automatically (by the display module) on the next frame (vertical sync.), whenthere is returned from out of the range to in range RGB interface timings.Himax ConfidentialThis information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosedin whole or in part without prior written permission of Himax.-P.46-March, 2009
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