HX8347-D - Mikrocontroller.net

HX8347-D(T)240RGB x 320 dot, 262K color, TFT Mobile Single Chip DriverDATA SHEET Preliminary V01These commands (R02h~R09h) are used to define area of frame memory whereMCU can access. The values of SC[15:0], EC[15:0], SP[15:0] and EP[15:0] arereferred when RAMWR command comes. Each value of SC[15:0], EC[15:0]represents one column line in the Frame Memory. Each value of SP[15:0], EP[15:0]represents one page line in the Frame Memory.8.9 Partial area start row register (PAGE0 -0A~0Bh)R/WDNCRB7RB6 RB5 RB4 RB3 RB2 RB1 RB0W1PSL15PSL14PSL13PSL12PSL11PSL10PSL9PSL8R 1PSL15PSL14PSL13PSL12PSL11PSL10PSL9PSL8Figure 8.12 Partial area start row register upper byte (PAGE0 -0Ah)R/WDNCRB7RB6 RB5 RB4 RB3 RB2 RB1 RB0W1PSL7PSL6PSL5PSL4PSL3PSL2PSL1PSL0R 1PSL7PSL6PSL5PSL4PSL3PSL2PSL1Figure 8.13 Partial area start row register low byte (PAGE0 -0Bh)PSL08.10 Partial area end row register (PAGE0 -0C~0Dh)R/WDNCRB7RB6 RB5 RB4 RB3 RB2 RB1 RB0W1PEL15PEL14PEL13PEL12PEL11PEL10PEL9PEL8R 1PEL15PEL14PEL13PEL12PEL11PEL10PEL9PEL8Figure 8.14 Partial area end row register upper byte (PAGE0 -0Ch)R/WDNCRB7RB6 RB5 RB4 RB3 RB2 RB1 RB0W1PEL7PEL6PEL5PEL4PEL3PEL2PEL1PEL0Himax ConfidentialR 1PEL7PEL6This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosedin whole or in part without prior written permission of Himax.PEL5PEL4PEL3PEL2PEL1Figure 8.15 Partial area end row register low byte (PAGE0 -0Dh)PEL0-P.116-March, 2009