SystemC based Virtual SoC â an Integrated System Level and Block ...
SystemC based Virtual SoC â an Integrated System Level and Block ... SystemC based Virtual SoC â an Integrated System Level and Block ...
16 Nov 2004ST-CMG tech-article (v1.2)1- Introduction: Verification and validation challengesBecause of the increasing complexity of set-top-box chips, the Verification team decidedto follow SystemC/TLM (Transaction Level Modelling) methodology. This allowed SWteams to initiate their SW development early in the design flow and provide an advancedand fast co- simulation platform for s/w development. This included ISS models, runningat a minimum targeted rate of 1 MHz in the simulation environment without the use ofhardware accelerators. Figure 1 illustrates the SoC TLM flow compared to the old flow.Section 2 describes this Virtual SoC platform for 3 usages: SW development, HWverification and architecture exploration and analysis. Section 3 will present STverification process for RTL at block and platform levels for set-top-box chips.In order to complete full verification regression tests (with real image sizes), the VirtualSoC platform was extended to include simulation acceleration. This approach makes useof the Transaction Based Verification (TBV) methodology, which enables the ability tomix SystemC testbench with RTL emulated on the Palladium 2 H/W emulator. This willbe described in section 4. Section 5 will summarize the benefits of the Virtual SoCplatform and will comment the next steps of ST TLM methodology.Traditional FlowSOC platforms in the design flowSpec Archi Design Fab BoardSoftwaredevelopmentSystemIntegrationSystemValidationCurrent flowSoC TLMDesignFabBoardCo-designTLM/ISSSoftwaredevelopmentSystemValidationSystemValidationCo-verificationRTL/ISS/TLMGAINTimeFigure 1: Comparison between traditional and SystemC/TLM flow2 Cadence H/W accelerator & emulator.pg# 2 of 7
16 Nov 2004ST-CMG tech-article (v1.2)2- Virtual SoC TLM platformTransaction Level Modelling (TLM) was pushed by industry and research institutesthrough OSCI to respond to the following tasks:- Embedded software development- Functional verification- Architecture analysis and exploration- HW/SW co-verification, HW validationTLM infrastructure was developed to support modelling communication structures atthree abstraction levels: i.e. Programmer’s View (PV), Programmer’s View with Timing(PVT) and Cycle Accurate (CA), leaving it up to the user to compromise betweensimulation speed and accuracy. ST has played a major role in the OSCI-TLM workinggroup and deployed TLM methodology on multiple projects.The virtual SoC TLM platform was developed at the PV level from Specifications inorder to offer fast simulations for the next phases. This platform has been used asreference model and enabled concurrent SW and HW engineering and close co-operationin early phases of the project. This process lead to the detection of significant bugs earlyin the hardware specification. Because these bugs were found early, they were relativelycheap to fix, and contributed to save a re-spin of the chip.SW engineers could start development before having the board. As example, this wasdone on Graphic Engine blitter and MPEG2 projects; the driver was developed beforehaving a board, that lead to 6 months time gain in comparison with traditional flow (aspointed out in figure 1).HW verification group employed TLM platform because, though more abstract, itaccurately modelled the bit level behaviour of the SoC while running at 1 MHz (this wasachieved on MPEG4 decoder project). This will be fully described in the followingsection.Another domain of utility is architecture exploration and analysis. The SoC TLMplatform, when refined with timing information, can provide relevant information on busbandwidth, peripheral accesses, interrupt latencies, memory conflicts and latency to thearchitects. The SysProbe methodology was built at ST using the flexible transactionrecording, viewing and analysis capabilities of Cadence’s SimVision and TXE. SysProbecould record the transactions generated by proprietary architectural models. It was alsoused for functional and timed validation. By calibrating TLM with back-annotated data[1] it was also possible to record the same transactions generated by either TLM modelsor corresponding RTL models and to compare the results using the environment providedby Cadence’s TXE. This technique was used to verify the performance of the RTL.pg# 3 of 7
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16 Nov 2004ST-CMG tech-article (v1.2)1- Introduction: Verification <strong>an</strong>d validation challengesBecause of the increasing complexity of set-top-box chips, the Verification team decidedto follow <strong><strong>System</strong>C</strong>/TLM (Tr<strong>an</strong>saction <strong>Level</strong> Modelling) methodology. This allowed SWteams to initiate their SW development early in the design flow <strong>an</strong>d provide <strong>an</strong> adv<strong>an</strong>ced<strong>an</strong>d fast co- simulation platform for s/w development. This included ISS models, runningat a minimum targeted rate of 1 MHz in the simulation environment without the use ofhardware accelerators. Figure 1 illustrates the <strong>SoC</strong> TLM flow compared to the old flow.Section 2 describes this <strong>Virtual</strong> <strong>SoC</strong> platform for 3 usages: SW development, HWverification <strong>an</strong>d architecture exploration <strong>an</strong>d <strong>an</strong>alysis. Section 3 will present STverification process for RTL at block <strong>an</strong>d platform levels for set-top-box chips.In order to complete full verification regression tests (with real image sizes), the <strong>Virtual</strong><strong>SoC</strong> platform was extended to include simulation acceleration. This approach makes useof the Tr<strong>an</strong>saction Based Verification (TBV) methodology, which enables the ability tomix <strong><strong>System</strong>C</strong> testbench with RTL emulated on the Palladium 2 H/W emulator. This willbe described in section 4. Section 5 will summarize the benefits of the <strong>Virtual</strong> <strong>SoC</strong>platform <strong>an</strong>d will comment the next steps of ST TLM methodology.Traditional FlowSOC platforms in the design flowSpec Archi Design Fab BoardSoftwaredevelopment<strong>System</strong>Integration<strong>System</strong>ValidationCurrent flow<strong>SoC</strong> TLMDesignFabBoardCo-designTLM/ISSSoftwaredevelopment<strong>System</strong>Validation<strong>System</strong>ValidationCo-verificationRTL/ISS/TLMGAINTimeFigure 1: Comparison between traditional <strong>an</strong>d <strong><strong>System</strong>C</strong>/TLM flow2 Cadence H/W accelerator & emulator.pg# 2 of 7
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