Sequential Circuits Prophet-5 Service Manual - Audiofanzine

1 1for the 2 to 5-foot range. The clock speed influences cable performance, since datatransfered at higher speeds encounters nnore reactance (hence, degradation) in thecable.USART OPERATIONNormally U386 USART stands unused. But it is initialized to interrupt the CPU whenserial data is received. When the CPU is interrupted, it stops whatever it is doing andreads the USART data as if it were reading a memory device. The CPU can also outputa byte to the USART. As discussed in the section on programming, this data exchangeenables sequencing and remote keyboard control.In more detail, pin 21 RESET connects to the CPU -RESET through inverter-wiredU382-3. When power comes on, RESET clears the USART's internal registers and sets itto Idle. To operate, it must be initialized with the appropriate bytes sent to its controlregisters.The USART connects to the Address Bus. AO and Ai select, while A 15 actuallyprograms the reading and writing to or from the USART's receive, transmit, or controlregisters.While the Address Bus is used to program the USART, its data lines remain tri-stateduntil pin 11 -CS goes low. The CPU sends commands and output data to the USART overthe Data Bus. The USART sends input data and its own status bytes (as opposed tostatus bytes sent by the external sequencer) to the CPU.After resetting and initializing the USART, it is set-up to respond to data input asfollows. Through the Low-Voltage Ouput Port Decoder U319, the CPU sets pin 10-CSOL5 low. On Rev 3.0 this signal cleared the monophonic sequencer Interface toGATE 5. On Rev 3.2 this signal clears the Interrupt Flip-Flop U330-2 (see SD352), whileGATE 5 is controlled separately. (GATE 5 is now memory-mapped. It is enabled byU318-10, through inverter U3^3-6 and Flip-Flop U330-13.)Once the Flip-Flop is reset, U330-2 -INT is high. Notice U385-8, the AND gate(converted to negative logic by DeMorgan) connected to USART pin U RxRDY. -INTconnects to U385-9. Pin 10 ispulled high by R3153. Thus, with both inputs high, U385-8--which actually connects to the CPU—is high and the CPU runs normally.The CPU is interrupted either by the USART signalling that it has received a byte, orby a GATE occuring through the monophonic sequencer interface. In the first case, theUSART RxRDY pin goes low when the USART has received a serial data byte.Whenever the -INT occurs, the CPU first examines the USART to see if its receivingregister is holding data. If not, then the -INT must have arisen from the monophonicsequencer interface.In this second case, the high SEQ GATE IN (J3) is inverted by U33U^, delayed slightly,and re-inverted by U331-2 to clock the Interrupt Flip-Flop U330-2. Since pin 5 D is tiedhigh, pin 1 Q goes high, and pin 2 -Q goes low, generating the -INT.TM1000D.2 10/81 8-3