Sequential Circuits Prophet-5 Service Manual - Audiofanzine

NV RAM read and write operations are controlled by the gated A15 and the -NV CS which is only gatedthrough U309-4 if power is on. -NV CS causes the RAM to latch the address bus and place the addresseddata on the Data Bus. The CPU acknowledges receipt of the data by setting -NV CS high. For a memorywrite operation, -NV WR goes low to set "WRITE MODE," and the data is written when -NV CS returnsto a high state.ITwo 2114 1024 X 4-bit NMOS static RAMs comprise the Scratchpad RAM. The read and write logic for5PAD is similar to that for NV, with added gating ensuring -WR or -RD isappear at U310-8.low for the SPAD RAM -CS toU315 isan 8253 Programmable Interval Timer (PIT) used in the TUNE and A-440 circuits. For discussion,see paragraph 2-13.As mentioned above, the I/O Port Decoders issue chip selects which control input sources and outputdestinations. Table 2-0 shows how allCSs are specifically decoded. Eight of the fourteen Output -CS,undergo a voltage shift from 5-V to 15-V levels. The reason is that the analog switches for 10-V levelwaveforms in the synth must operate on +15V, therefore so must the latches which control the switchesand, likewise, the decoder which controls the latches. Seven bits of the Data Bus itself are also shiftedup. by U327, for compatibility with the high-voltage latches and DAC.Table 2-0CHIP SELECT DECODINGCS NAME FUNCTION -MREQ -lORQ --WR-A10-A12AO-AROMO ROMO XROM1 ROM 1 XROM 2 ROM 2 XNVXRAMI SPAD XTIMERXXXXXXXX1 X2 X3 X4 X6 XCSIOCSI1CSI2KBD/SWCASS/MISCADC111XX 02X 0401(H)CSOLOCSOL1CSOL2CSOL3CSOL4CSOL5LED DRVRLED SINKKBD/SW DRVRPOT MUX ADRCA5S/TUNECLEAR INTX 00X 08X 10X 18X 20X 28CSOHOPROG SWCSOH1 PROG SW 1CSOH2 PROG SW 2CSOH3CSOH4CSOH5CSOH6CSOH7S/H ABC/TUNES/HGATESDAC LSBDAC MSBX 30X 31X 32X 33X 38X 39XX3A3B1 = = DIGITAL HIGH== DIGITAL LOW(H) = =x = =HEXADECIMALDON'T CARE2-13