Z8018x Family MPU

Z8018x FamilyMPU User M anual19The Op Code on the data bus is latched at the rising edge of T3 and thebus cycle terminates at the end of T3.PhiA0–A19D0–D7T1 T2 T3 T1 T2WAITM1MREQRDFigure 9.Op Code Fetch (without Wait State) Timing DiagramFigure 10 illustrates the insertion of Wait States (TW) into the Op Codefetch cycle. Wait States (TW) are controlled by the external WAIT inputcombined with an on-chip programmable Wait State generator.At the falling edge of T2 the combined WAIT input is sampled. If WAITinput is asserted Low, a Wait State (TW) is inserted. The address bus,MREQ, RD and M1 are held stable during Wait States. When WAIT issampled inactive High at the falling edge of TW, the bus cycle enters T3and completes at the end of T3.UM005001-ZMP0400