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Z8018x Family MPU

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<strong>Z8018x</strong> <strong>Family</strong><strong>MPU</strong> User ManualxiFigure 49. TEND0 Output Timing Diagram . . . . . . . . . . . . . . . . . . .108Figure 50. DMA Interrupt Request Generation . . . . . . . . . . . . . . . . .114Figure 51. NMI and DMA Operation Timing Diagram . . . . . . . . . . .115Figure 52. ASCI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .117Figure 53. DCD0 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .139Figure 54. RTS0 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .140Figure 55. ASCI Interrupt Request Circuit Diagram . . . . . . . . . . . . .140Figure 56. ASCI Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141Figure 57. CSI/O Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .147Figure 58. CSI/O Interrupt Request Generation . . . . . . . . . . . . . . . . .151Figure 59. Transmit Timing Diagram–Internal Clock . . . . . . . . . . . .153Figure 60. Transmit Timing–External Clock . . . . . . . . . . . . . . . . . . .154Figure 61. CSI/O Receive Timing–Internal Clock . . . . . . . . . . . . . . .155Figure 62. CSI/O Receive Timing–External Clock . . . . . . . . . . . . . .156Figure 63. PRT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157Figure 64.Timer Initialization, Count Down, and ReloadTiming Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163Figure 65. Timer Output Timing Diagram . . . . . . . . . . . . . . . . . . . . .164Figure 66. PRT Interrupt Request Generation . . . . . . . . . . . . . . . . . .164Figure 67.E Clock Timing Diagram (During Read/Write Cycleand Interrupt Acknowledge Cycle . . . . . . . . . . . . . . . . . .167Figure 68. E Clock Timing in BUS RELEASE Mode . . . . . . . . . . . .167Figure 69.E Clock Timing in SLEEP Mode andSYSTEM STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .168Figure 70. External Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . .169Figure 71. Clock Generator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . .170Figure 72. Circuit Board Design Rules . . . . . . . . . . . . . . . . . . . . . . .170Figure 73. Example of Board Design . . . . . . . . . . . . . . . . . . . . . . . . .171UM005001-ZMP0400

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