PCF85163 Real-time clock and calendar - Digikey
PCF85163 Real-time clock and calendar - Digikey
PCF85163 Real-time clock and calendar - Digikey
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NXP Semiconductors<strong>PCF85163</strong><strong>Real</strong>-<strong>time</strong> <strong>clock</strong> <strong>and</strong> <strong>calendar</strong>13. Dynamic characteristicsTable 30. Dynamic characteristicsV DD = 1.8 V to 5.5 V; V SS =0V; T amb = −40 °C to +85 °C; f osc = 32.768 kHz; quartz R s =40kΩ; C L = 8 pF; unless otherwisespecified.Symbol Parameter Conditions Min Typ Max UnitOscillatorC OSCO capacitance on pin OSCO 15 25 35 pFΔf osc /f osc relative oscillator frequency variation ΔV DD =200mV; - 0.2 - ppmT amb =25°CQuartz crystal parameters (f = 32.768 kHz)R s series resistance - - 100 kΩC L load capacitance parallel[1]7 - 12.5 pFC trim trimmer capacitance external;5 - 25 pFon pin OSCICLKOUT outputδ CLKOUT duty cycle on pin CLKOUT[2]- 50 - %I 2 C-bus timing characteristics (see Figure 24) [3][4]f SCL SCL <strong>clock</strong> frequency[5]- - 400 kHzt HD;STA hold <strong>time</strong> (repeated) START condition 0.6 - - μst SU;STA set-up <strong>time</strong> for a repeated START condition 0.6 - - μst LOW LOW period of the SCL <strong>clock</strong> 1.3 - - μst HIGH HIGH period of the SCL <strong>clock</strong> 0.6 - - μst r rise <strong>time</strong> of both SDA <strong>and</strong> SCL signals - - 0.3 μst f fall <strong>time</strong> of both SDA <strong>and</strong> SCL signals - - 0.3 μsC b capacitive load for each bus line - - 400 pFt SU;DAT data set-up <strong>time</strong> 100 - - nst HD;DAT data hold <strong>time</strong> 0 - - nst SU;STO set-up <strong>time</strong> for STOP condition 0.6 - - μst w(spike) spike pulse width on bus - - 50 ns( C[1] C L is a calculation of C trim <strong>and</strong> C OSCO in series: C trim⋅ C OSCO)L= ----------------------------------------- .( C trim+ C OSCO)[2] Unspecified for f CLKOUT = 32.768 kHz.[3] All timing values are valid within the operating supply voltage at ambient temperature <strong>and</strong> referenced to V IL <strong>and</strong> V IH with an input voltageswing of V SS to V DD .[4] A detailed description of the I 2 C-bus specification is given in Ref. 12 “UM10204”.[5] I 2 C-bus access <strong>time</strong> between two STARTs or between a START <strong>and</strong> a STOP condition to this device must be less than one second.<strong>PCF85163</strong> All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.Product data sheet Rev. 2 — 28 July 2010 31 of 43
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