PCF85163 Real-time clock and calendar - Digikey
PCF85163 Real-time clock and calendar - Digikey
PCF85163 Real-time clock and calendar - Digikey
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NXP Semiconductors<strong>PCF85163</strong><strong>Real</strong>-<strong>time</strong> <strong>clock</strong> <strong>and</strong> <strong>calendar</strong>9. Characteristics of the I 2 C-busThe I 2 C-bus is for bidirectional, two-line communication between different ICs or modules.The two lines are a Serial DAta line (SDA) <strong>and</strong> a Serial Clock Line (SCL). Both lines mustbe connected to a positive supply via a pull-up resistor. Data transfer may be initiated onlywhen the bus is not busy.9.1 Bit transferOne data bit is transferred during each <strong>clock</strong> pulse. The data on the SDA line must remainstable during the HIGH period of the <strong>clock</strong> pulse, as changes in the data line at this <strong>time</strong>will be interpreted as a control signal (see Figure 12).SDASCLdata linestable;data validchangeof dataallowedmbc621Fig 12.Bit transfer9.2 START <strong>and</strong> STOP conditionsBoth data <strong>and</strong> <strong>clock</strong> lines remain HIGH when the bus is not busy.A HIGH-to-LOW transition of the data line while the <strong>clock</strong> is HIGH is defined as the STARTcondition - S.A LOW-to-HIGH transition of the data line while the <strong>clock</strong> is HIGH is defined as the STOPcondition - P (see Figure 13).SDASDASCLSPSCLSTART conditionSTOP conditionmbc622Fig 13.Definition of START <strong>and</strong> STOP conditions9.3 System configurationA device generating a message is a transmitter; a device receiving a message is areceiver. The device that controls the message is the master; <strong>and</strong> the devices which arecontrolled by the master are the slaves (see Figure 14).<strong>PCF85163</strong> All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.Product data sheet Rev. 2 — 28 July 2010 21 of 43