PCF85163 Real-time clock and calendar - Digikey

NXP SemiconductorsPCF85163Real-time clock and calendar9. Characteristics of the I 2 C-busThe I 2 C-bus is for bidirectional, two-line communication between different ICs or modules.The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines mustbe connected to a positive supply via a pull-up resistor. Data transfer may be initiated onlywhen the bus is not busy.9.1 Bit transferOne data bit is transferred during each clock pulse. The data on the SDA line must remainstable during the HIGH period of the clock pulse, as changes in the data line at this timewill be interpreted as a control signal (see Figure 12).SDASCLdata linestable;data validchangeof dataallowedmbc621Fig 12.Bit transfer9.2 START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy.A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the STARTcondition - S.A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOPcondition - P (see Figure 13).SDASDASCLSPSCLSTART conditionSTOP conditionmbc622Fig 13.Definition of START and STOP conditions9.3 System configurationA device generating a message is a transmitter; a device receiving a message is areceiver. The device that controls the message is the master; and the devices which arecontrolled by the master are the slaves (see Figure 14).PCF85163 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.Product data sheet Rev. 2 — 28 July 2010 21 of 43