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PCF85163 Real-time clock and calendar - Digikey

PCF85163 Real-time clock and calendar - Digikey

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NXP Semiconductors<strong>PCF85163</strong><strong>Real</strong>-<strong>time</strong> <strong>clock</strong> <strong>and</strong> <strong>calendar</strong>Table 26. First increment of <strong>time</strong> circuits after STOP bit releaseBit Prescaler bits[1]1Hz tick Time CommentSTOP F 0 F 1 -F 2 to F 14 hh:mm:ssClock is running normally0 01-0 0001 1101 0100 12:45:12 prescaler counting normallySTOP bit is activated by user. F 0 F 1 are not reset <strong>and</strong> values cannot be predicted externally1 XX-0 0000 0000 0000 12:45:12 prescaler is reset; <strong>time</strong> circuits are frozenNew <strong>time</strong> is set by user1 XX-0 0000 0000 0000 08:00:00 prescaler is reset; <strong>time</strong> circuits are frozenSTOP bit is released by user0 XX-0 0000 0000 0000 08:00:00 prescaler is now running0.507813 to 0.507935 sXX-1 0000 0000 0000 08:00:00 -XX-0 1000 0000 0000 08:00:00 -XX-1 1000 0000 0000 08:00:00 -: : :11-1 1111 1111 1110 08:00:00 -00-0 0000 0000 0001 08:00:01 0 to 1 transition of F 14 increments the <strong>time</strong> circuits10-0 0000 0000 0001 08:00:01 -: : :1.000000 s11-1 1111 1111 1111 08:00:01 -00-0 0000 0000 0000 08:00:01 -10-0 0000 0000 0000 08:00:01 -: : :11-1 1111 1111 1110 08:00:01 -00-0 0000 0000 0001 08:00:02 0 to 1 transition of F 14 increments the <strong>time</strong> circuits013aaa076[1] F 0 is <strong>clock</strong>ed at 32.768 kHz.The first increment of the <strong>time</strong> circuits is between 0.507813 s <strong>and</strong> 0.507935 s after STOPbit is released. The uncertainty is caused by the prescaler bits F 0 <strong>and</strong> F 1 not being reset(see Table 26) <strong>and</strong> the unknown state of the 32 kHz <strong>clock</strong>.8.11 ResetThe <strong>PCF85163</strong> includes an internal reset circuit which is active whenever the oscillator isstopped. In the reset state the I 2 C-bus logic is initialized including the address pointer <strong>and</strong>all registers are set according to Table 27. I 2 C-bus communication is not possible duringreset.<strong>PCF85163</strong> All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.Product data sheet Rev. 2 — 28 July 2010 19 of 43

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