10 1-WIRE BUS MASTER

1-WIRE BUS MASTERHAMCOP MICROPROCESSOR COMPANION CHIPTRANSMITTING/RECEIVING BUFFER REGISTERData sent and received from 1-Wire master passes through the transmit/receive buffer. The 1-Wire master isacatually double buffered with separate transmit and receive buffers. Writing to this address connects the TransmitBuffer to the data bus while reading connects the Receive Buffer to the data bus.Register Offset Addr R/W Description Reset ValueOWTBR 0x0006804 W TX Buffer Register 0xXXOWRBR 0x0006804 R RX Buffer Register 0xXXData Buffer Bit Description Initial StateTransmit/Receive data[7:0] When writing, data to be transmitted.When reading, received data.0xXX10-6

HAMCOP MICROPROCESSOR COMPANION CHIP 1-WIRE BUS MASTERCOMMAND REGISTERThe 1-Wire Master can generates two special commands on the bus in addition to reading and writing. The first isa 1-Wire reset, which must precede any commands given on the bus. Secondly, the 1-Wire Master can be placedinto Search ROM Accelerator mode to prevent the host from having to perform single bit manipulations of the busduring a Search ROM operation(0xF0h). For details on the reset or Search ROM command see [1]. In addition tothese two functions, the Command Register contains two bits to bypass the 1-Wire Master features and control the1-wire bus directly.Register Offset Addr R/W Description Reset ValueOWCMND 0x0006800 R/W Command register 0x00OWCMND Bit Description Initial StateReserved [7:4] 0000DQI [3] DQ inputThis bit is read-only and reflects the present state of 1-wirebus. It should be used together with DQO bit whencontrolling the bus directly. The state of this bit does notaffect any other functions of the 1-Wire Master. Operation ofthis bit is unaffected by the state of DQOE.0DQO [2] DQ outputThis bit can be used to bypass 1-Wire Master operation anddrive the bus directly if needed. Setting this bit high will drivethe bus low until it is cleared or the 1-Wire Master reset.While the 1-Wire bus is held low no other 1-Wire Masteroperations will function. By controlling the length of time thisbit is set and point when the line is sampled, see DQI below,any 1-Wire communication can be generated by the hostcontroller. To prevent accidental writes to the bus, theDQOE bit in the interrupt enable register mist set to 1 beforethe DQO bit will function. This bit is cleared to 0 on power-upor master reset.SRA [1] Search ROM AcceleratorWhen this bit is set, the 1-Wire Master will switch to SearchROM Accelerator mode.1WR [0] 1-Wire ResetIf this bit is set, a reset will be generated on the 1-Wire bus.Setting this bit automatically clears the SRA bit. This bit willbe automatically cleared as soon as the 1-Wire resetcompletes.00010-7

HAMCOP MICROPROCESSOR COMPANION CHIP 1-WIRE BUS MASTERINTERRUPT CONFIGURATION REGISTERThe Interrupt Configuration Register allows the system programmer to specify the source of interrupts which willcause the interrupt request signal to be active, and to define the active state for the interrupt request signal. Whena Master reset is received all bits in this register are cleared to 0 disabling all interrupt source.Register Offset Addr R/W Description Reset ValueOWIER 0x000680C R/W Interrupt Configuration register 0x00OWIER Bit Description Initial StateReserved [7:6] 00ERSRF [5] Enable Receive Shift Register Full Interrupt0 = disable 1 = enableERBF [4] Enable Receive Buffer Full Interrupt.0 = disable 1 = enableETMT [3] Enable Transmit Shift Register Empty Interrupt0 = disable 1 = enableETBE [2] Enable Transmit Buffer Empty Interrupt0 = disable 1 = enable0000Reserved [1] 0EPD [0] Enable Presence Detect Interrupt0 = disable 1 = enable010-9