TFDU6103 Datasheet - Vishay
TFDU6103 Datasheet - Vishay TFDU6103 Datasheet - Vishay
www.vishay.comNot for New DesignsTFDU6103Vishay SemiconductorsRECOMMENDED CIRCUIT DIAGRAMVishay Semiconductors transceivers integrate a sensitivereceiver and a built-in power driver. The combination of bothneeds a careful circuit board layout. The use of thin, long,resistive and inductive wiring should be avoided. The inputs(TXD, SD) and the output RXD should be directly (DC)coupled to the I/O circuit.Vcc2Vcc1GNDSDTXDRXD19789R2C1R1C3IRED AnodeFig. 1 - Recommended Application CircuitThe capacitor C1 is buffering the supply voltage andreduces the influence of the inductance of the power supplyline. This one should be a Tantalum or other fast capacitorto guarantee the fast rise time of the IRED current. Theresistor R1 is only necessary for higher operating voltagesC2VccGroundSDTXDRXDIRED Cathodeand elevated temperatures, see derating curve in figure 6, toavoid too high internal power dissipation.The capacitors C2 and C3 combined with the resistor R2 (asthe low pass filter) is smoothing the supply voltage V CC1 . R2,C1, C2, and C3 are optional and dependent on the quality ofthe supply voltages V CC1 and V CC2 and injected noise. Anunstable power supply with dropping voltage duringtransmission may reduce sensitivity (and transmissionrange) of the transceiver. The placement of these parts iscritical. It is strongly recommended to position C2 and C3 asclose as possible to the transceiver power supply pins. Antantalum capacitor should be used for C1 and C3 while aceramic capacitor is used for C2.In addition, when connecting the described circuit to thepower supply, low impedance wiring should be used.When extended wiring is used the inductance of the powersupply can cause dynamically a voltage drop at V CC2 . Oftensome power supplies are not able to follow the fast currentrise time. In that case another 4.7 μF (type, see table underC1) at V CC2 will be helpful.Keep in mind that basic RF-design rules for circuit designshould be taken into account. Especially longer signal linesshould not be used without termination. See e.g. “The Art ofElectronics” Paul Horowitz, Wienfield Hill, 1989, CambridgeUniversity Press, ISBN: 0521370957.TABLE 1 - RECOMMENDED APPLICATION CIRCUIT COMPONENTSCOMPONENT RECOMMENDED VALUE VISHAY PART NUMBERC1, C3 4.7 μF, 16 V 293D 475X9 016BC2 0.1 μF, ceramic VJ 1206 Y 104 J XXMTR13.3 V supply voltage: no resistors necessary, the internalcontroller is able to control the currente.g. 2 x CRCW-1206-1R0-F-RT1R2 10 , 0.125 W CRCW-1206-10R0-F-RT1I/O AND SOFTWAREIn the description, already different I/Os are mentioned.Different combinations are tested and the function verifiedwith the special drivers available from the I/O suppliers. Inspecial cases refer to the I/O manual, the Vishay applicationnotes, or contact directly Vishay Sales, Marketing orApplication.MODE SWITCHINGThe TFDU6103 is in the SIR mode after power on as adefault mode, therefore the FIR data transfer rate has to beset by a programming sequence using the TXD and SDinputs as described below. The low frequency mode coversspeeds up to 115.2 kbit/s. Signals with higher data ratesshould be detected in the high frequency mode. Lowerfrequency data can also be received in the high frequencymode but with reduced sensitivity.To switch the transceivers from low frequency mode to thehigh frequency mode and vice versa, the programmingsequences described below are required.(0.576 Mbit/s to 4 Mbit/s)1. Set SD input to logic “high”.(2)Set TXD input to logic “high”. Wait t s 200 ns.(3)Set SD to logic “low” (this negative edge latches state ofTXD, which determines speed setting).(4)After waiting t h 200 ns TXD can be set to logic “low”.The hold time of TXD is limited by the maximum allowedpulse length.After that TXD is enabled as normal TXD input and thetransceiver is set for the high bandwidth (576 kbit/s to4 Mbit/s) mode.SETTING TO THE HIGH BANDWIDTH MODERev. 1.5, 06-Sep-13 6 Document Number: 81211For technical questions, contact: irdasupportAM@vishay.comTHIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.comNot for New DesignsTFDU6103Vishay SemiconductorsSETTING TO THE LOWER BANDWIDTH MODE(2.4 kbit/s to 115.2 kbit/s)1. Set SD input to logic “high”.(2)Set TXD input to logic “low”. Wait t s 200 ns.(3)Set SD to logic “low” (this negative edge latches state ofTXD, which determines speed setting).(4)TXD must be held for t h 200 ns.After that TXD is enabled as normal TXD input and thetransceiver is set for the lower bandwidth (9.6 kbit/s to115.2 kbit/s) mode.NoteWhen applying this sequence to the device already in the lowerbandwidth mode, the SD pulse is interpreted as shutdown. In thiscase the RXD output of the transceiver may react with a single pulse(going active low) for a duration less than 2 μs. The operatingsoftware should take care for this condition.In case the applied SD pulse is longer than 4 μs, no RXD pulse is tobe expected but the receiver startup time is to be taken into accountbefore the device is in receive condition.SD50 %TXDt s t hHigh: FIR50 %50 %Low: SIRFig. 2 - Mode Switching Timing Diagram14873TABLE 2 - TRUTH TABLEINPUTSOUTPUTSSD TXD OPTICAL INPUT IRRADIANCE mW/m 2 RXD TRANSMITTERHigh x x Weakly pulled (500 k) to V CC1 0LowHigh x Low (active) I eHigh > 150 μs x High 0Low < 4 High 0Low> min. irradiance E e< max. irradiance E eLow (active) 0Low > max. irradiance E e x 0RECOMMENDED SOLDER PROFILESSolder Profile for Sn/Pb SolderingTemperature (°C)260240240 °C max.10 s max. at 230 °C2202002 to 4 °C/s180160160 °C max.140120120 to180 s90 s max.10080 2 to 4 °C/s60402000 50 100 150 200 250 300 35019535Time/sFig. 1 - Recommended Solder Profile for Sn/Pb solderingLead (Pb)-free, Recommended Solder ProfileThe TFDU6103 is a lead (Pb)-free transceiver and qualifiedfor lead (Pb)-free processing. For lead (Pb)-free solder pastelike Sn (3.0 - 4.0) Ag (0.5 - 0.9) Cu, there are two standard reflowprofiles: Ramp-Soak-Spike (RSS) and Ramp-To-Spike(RTS). The Ramp-Soak-Spike profile was developedprimarily for reflow ovens heated by infrared radiation. Withwidespread use of forced convection reflow ovens theRamp-To-Spike profile is used increasingly. Shown infigure 4 and 5 are Vishay's recommended profiles for usewith the TFDU6103 transceivers. For more details pleaserefer to the application note “SMD Assembly Instructions”.A ramp-up rate less than 0.9 °C/s is not recommended.Ramp-up rates faster than 1.3 °C/s could damage an opticalpart because the thermal conductivity is less than comparedto a standard IC.Wave SolderingFor TFDUxxxx and TFBSxxxx transceiver devices wavesoldering is not recommended.Manual SolderingManual soldering is the standard method for lab use.However, for a production process it cannot berecommended because the risk of damage is highlydependent on the experience of the operator. Nevertheless,we added a chapter to the above mentioned applicationnote, describing manual soldering and desoldering.Rev. 1.5, 06-Sep-13 7 Document Number: 81211For technical questions, contact: irdasupportAM@vishay.comTHIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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www.vishay.comNot for New Designs<strong>TFDU6103</strong><strong>Vishay</strong> SemiconductorsRECOMMENDED CIRCUIT DIAGRAM<strong>Vishay</strong> Semiconductors transceivers integrate a sensitivereceiver and a built-in power driver. The combination of bothneeds a careful circuit board layout. The use of thin, long,resistive and inductive wiring should be avoided. The inputs(TXD, SD) and the output RXD should be directly (DC)coupled to the I/O circuit.Vcc2Vcc1GNDSDTXDRXD19789R2C1R1C3IRED AnodeFig. 1 - Recommended Application CircuitThe capacitor C1 is buffering the supply voltage andreduces the influence of the inductance of the power supplyline. This one should be a Tantalum or other fast capacitorto guarantee the fast rise time of the IRED current. Theresistor R1 is only necessary for higher operating voltagesC2VccGroundSDTXDRXDIRED Cathodeand elevated temperatures, see derating curve in figure 6, toavoid too high internal power dissipation.The capacitors C2 and C3 combined with the resistor R2 (asthe low pass filter) is smoothing the supply voltage V CC1 . R2,C1, C2, and C3 are optional and dependent on the quality ofthe supply voltages V CC1 and V CC2 and injected noise. Anunstable power supply with dropping voltage duringtransmission may reduce sensitivity (and transmissionrange) of the transceiver. The placement of these parts iscritical. It is strongly recommended to position C2 and C3 asclose as possible to the transceiver power supply pins. Antantalum capacitor should be used for C1 and C3 while aceramic capacitor is used for C2.In addition, when connecting the described circuit to thepower supply, low impedance wiring should be used.When extended wiring is used the inductance of the powersupply can cause dynamically a voltage drop at V CC2 . Oftensome power supplies are not able to follow the fast currentrise time. In that case another 4.7 μF (type, see table underC1) at V CC2 will be helpful.Keep in mind that basic RF-design rules for circuit designshould be taken into account. Especially longer signal linesshould not be used without termination. See e.g. “The Art ofElectronics” Paul Horowitz, Wienfield Hill, 1989, CambridgeUniversity Press, ISBN: 0521370957.TABLE 1 - RECOMMENDED APPLICATION CIRCUIT COMPONENTSCOMPONENT RECOMMENDED VALUE VISHAY PART NUMBERC1, C3 4.7 μF, 16 V 293D 475X9 016BC2 0.1 μF, ceramic VJ 1206 Y 104 J XXMTR13.3 V supply voltage: no resistors necessary, the internalcontroller is able to control the currente.g. 2 x CRCW-1206-1R0-F-RT1R2 10 , 0.125 W CRCW-1206-10R0-F-RT1I/O AND SOFTWAREIn the description, already different I/Os are mentioned.Different combinations are tested and the function verifiedwith the special drivers available from the I/O suppliers. Inspecial cases refer to the I/O manual, the <strong>Vishay</strong> applicationnotes, or contact directly <strong>Vishay</strong> Sales, Marketing orApplication.MODE SWITCHINGThe <strong>TFDU6103</strong> is in the SIR mode after power on as adefault mode, therefore the FIR data transfer rate has to beset by a programming sequence using the TXD and SDinputs as described below. The low frequency mode coversspeeds up to 115.2 kbit/s. Signals with higher data ratesshould be detected in the high frequency mode. Lowerfrequency data can also be received in the high frequencymode but with reduced sensitivity.To switch the transceivers from low frequency mode to thehigh frequency mode and vice versa, the programmingsequences described below are required.(0.576 Mbit/s to 4 Mbit/s)1. Set SD input to logic “high”.(2)Set TXD input to logic “high”. Wait t s 200 ns.(3)Set SD to logic “low” (this negative edge latches state ofTXD, which determines speed setting).(4)After waiting t h 200 ns TXD can be set to logic “low”.The hold time of TXD is limited by the maximum allowedpulse length.After that TXD is enabled as normal TXD input and thetransceiver is set for the high bandwidth (576 kbit/s to4 Mbit/s) mode.SETTING TO THE HIGH BANDWIDTH MODERev. 1.5, 06-Sep-13 6 Document Number: 81211For technical questions, contact: irdasupportAM@vishay.comTHIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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