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ABOV SEMICONDUCTOR Co., Ltd.Universal AsynchronousReceiver/Transmitter with FIFOsMC16C550User’s Manual (Ver. 1.06)

MC16C550REVISION HISTORY ( I )VERSION 1.06 (May 23, 2008) add package type in featuresVERSION 1.05 (May 19, 2008) change AC characteristicsVERSION 1.04 (May 15, 2008) remove wrong feature(TTL characteristics) and fix baud rate descriptionVERSION 1.03 (May 14, 2008) modify pin name, change package picture and fix mistaken characterVERSION 1.02 (May 9, 2008) change AC characteristicVERSION 1.01 (April 28, 2008) change datasheet styleVERSION 1.0 (April 2, 2008)Version 1.06Published by FAE Team2008 ABOV Semiconductor Co., Ltd. All rights reserved.Additional information of this manual may be served by ABOV Semiconductor offices in Korea orDistributors.ABOV Semiconductor reserves the right to make changes to any information here in at any time withoutnotice.The information, diagrams and other data in this manual are correct and reliable; however, ABOVSemiconductor is in no way responsible for any violations of patents or other rights of the third partygenerated by the use of this manual.May 23, 2008 Ver. 1.06 2

MC16C550Table of Contents1. OVERVIEW ......................................................................................................................................... 41.1 Description ................................................................................................................................................... 41.2 Features ........................................................................................................................................................ 52. BLOCK DIAGRAM .............................................................................................................................. 63. PIN ASSIGNMENT ............................................................................................................................. 74. PACKAGE DIAGRAM ......................................................................................................................... 85. PIN FUNCTION ................................................................................................................................. 106. Electrical CHARACTERISTICS ........................................................................................................ 137. TIMING WAVEFOMS (All timings are referenced to valid 0 and valid 1) ......................................... 168. REGISTERS ..................................................................................................................................... 228.1 LINE CONTROL REGISTER................................................................................................................... 228.2 TYPICAL CLOCK CIRCUITS ................................................................................................................. 228.3 PROGRAMMABLE BAUD GENERATOR ............................................................................................ 248.4 LINE STATUS REGISTER ...................................................................................................................... 248.5 FIFO CONTROL REGISTER ................................................................................................................... 258.6 INTERRUPT IDENTIFICATION REGISTER ......................................................................................... 258.7 INTERRUPT ENABLE REGISTER ......................................................................................................... 268.8 MODEM CONTROL REGISTER ............................................................................................................ 268.9 MODEM STATUS REGISTER ................................................................................................................ 268.10 SCRATCHPAD REGISTER ................................................................................................................... 278.11 FIFO INTERRUPT MODE OPERATION .............................................................................................. 278.12 FIFO POLLED MODE OPERATION .................................................................................................... 289. TYPICAL APPLICATIONS ................................................................................................................ 29May 23, 2008 Ver. 1.06 3

MC16C550MC16C550Universal AsynchronousReceiver/Transmitter with FIFOs1. OVERVIEW1.1 DescriptionThe MC16C550 is an improved version of the original 16450 Universal Asynchronous Receiver/Transmitter(UART). Functionally identical to the 16450 on power up (CHARACTER mode)* the MC16C550 can be putinto an alternate mode (FIFO mode) to relieve the CPU of excessive software overhead.In this mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the RCVRFIFO) to be stored in both receive and transmit modes. All the logic is on chip to minimize system overhead andmaximize system efficiency. Two pin functions have been changed to allow signaling of DMA transfers.The UART performs serial-to-parallel conversion on data characters received from a peripheral device or aMODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read thecomplete status of the UART at any time during the functional operation. Status information reported includesthe type and condition of the transfer operations being performed by the UART, as well as any error conditions(parity, overrun, framing, or break interrupt). The UART includes a programmable baud rate generator that iscapable of dividing the timing reference clock input by divisors of 1 to (2 16 -1), and producing a 16 × clock fordriving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiverlogic. The UART has complete MODEM-control capability, and a processor-interrupt system. Interrupts can beprogrammed to the user's requirements, minimizing the computing required to handle the communications link.*Can also be reset to 16450 Mode under software control.May 23, 2008 Ver. 1.06 4

MC16C5501.2 Features• 3.3 to 5V operation• Capable of running all existing 16450 software.• Pin for pin compatible with the existing 16450except for CSOUT (24) and NC (29). Theformer CSOUT and NC pins are nTXRDY andnRXRDY, respectively.• After reset, all registers are identical to the16450 register set.• In the FIFO mode transmitter and receiver areeach buffered with 16 byte FIFO's to reduce thenumber of interrupts presented to the CPU.• Adds or deletes standard asynchronouscommunication bits (start, stop and parity) to orfrom the serial data.• Holding and shift registers in the 16450 Modeeliminate the need for precise synchronizationbetween the CPU and serial data.• Independently controlled transmit, receive, linestatus, and data set interrupts.• Programmable baud generator divides any inputclock by 1 to (2 16 − 1) and generates the 16 ×clock.• Independent receiver clock input.• MODEM control functions (CTS, RTS, DSR,DTR, RI, and DCD).• Fully programmable serial-interfacecharacteristics:― 5-, 6-, 7-, or 8-bit characters― Even, odd, or no-parity bit generation anddetection― 1-, 1 1 2-, or 2-stop bit generation― Baud generation (DC to 256K baud).• False start bit detection.• Complete status reporting capabilities.• Line break generation and detection.• Internal diagnostic capabilities:― Loopback controls for communicationslink fault isolation― Break, parity, overrun, framing errorsimulation.• Full prioritized interrupt system controls.Ordering InformationDevice nameMC16C550BMC16C550PPackage40 DIP44 PLCCMC16C550L48 LQFPMay 23, 2008 Ver. 1.06 5

MC16C5502. BLOCK DIAGRAMMay 23, 2008 Ver. 1.06 6

MC16C5503. PIN ASSIGNMENTPIN 40 DIP 44 PLCC 48 LQFP1 D0 NC NC2 D1 D0 D53 D2 D1 D64 D3 D2 D75 D4 D3 RCLK6 D5 D4 NC7 D6 D5 SIN8 D7 D6 SOUT9 RCLK D7 CS010 SIN RCLK CS111 SOUT SIN nCS212 CS0 NC nBAUDOUT13 CS1 SOUT NC14 nCS2 CS0 XTALIN15 nBAUDOUT CS1 XTALOUT16 XTALIN nCS2 nIOW17 XTALOUT nBAUDOUT IOW18 nIOW XTALIN VSS19 IOW XTALOUT nIOR20 VSS nIOW IOR21 nIOR IOW NC22 IOR VSS nDDIS23 nDDIS NC nTXRDY24 nTXRDY nIOR nAS25 nAS IOR NC26 A2 nDDIS A227 A1 nTXRDY A128 A0 nAS A029 nRXRDY A2 nRXRDY30 INTR A1 INTR31 nOUT2 A0 nOUT232 nRTS nRXRDY nRTS33 nDTR INTR nDTR34 nOUT1 NC nOUT135 MRESET nOUT2 MRESET36 nCTS nRTS NC37 nDSR nDTR NC38 nDCD nOUT1 nCTS39 nRI MRESET nDSR40 VDD nCTS nDCD41 nDSR nRI42 nDCD VDD43 nRI D044 VDD D145 D246 D347 D448 NCMay 23, 2008 Ver. 1.06 7

MC16C5504. PACKAGE DIAGRAMMay 23, 2008 Ver. 1.06 8

MC16C550May 23, 2008 Ver. 1.06 9

5. PIN FUNCTIONThe following describes the function of allUART pins. Some of these descriptions referenceinternal circuits.In the following descriptions, a low represents alogic and a high represents a logic 1.A0, A1, A2, Register Select: Address signalsconnected to these 3 inputs select a UART registerfor the CPU to read from or write to during datatransfer. A table of registers and their addresses isshown below. Note that the state of the DivisorLatch Access Bit (DLAB), which is the mostsignificant bit of the Line Control Register, affectsthe selection of certain UART registers. The DLABmust be set high by the system software to accessthe Baud Generator Divisor Latches.Register AddressDLAB A 2 A 1 A 0 Register0 0 0 0 Receiver Buffer(read)Transmitter HoldingRegister (Write)0 0 0 1 Interrupt Enablex 0 1 0 InterruptIdentification(read)x 0 1 0 FIFO Controlx 0 1 1 Line Controlx 1 0 0 MODEM Controlx 1 0 1 Line Statusx 1 1 MODEM Statusx 1 1 1 Scratch1 0 0 0 Divisor Latch(least significant byte)1 0 0 1 Divisor Latch(most significant byte)nAS, Address Strobe: The positive edge of anactive Address Strobe (nAS) signal latches theRegister Select (A0, A1, A2) and Chip Select (CS0,CS1, nCS2) signals.Note: An active nAS input is required when the Register Select(A0, A1, A2) and Chip Select (CS0, CS1, nCS2) signalsare not stable for the duration of a read or write operation.If not required, tie the nAS input permanently low.nBAUDOUT, Baud Out: This is the 16 × clocksignal from the transmitter section of the UART.The clock rate is equal to the main referenceoscillator frequency divided by the specifieddivisor in the Baud Generator Divisor Latches. ThenBAUDOUT may also be used for the receiversection by tying this output to the RCLK input ofthe chip.CS0, CS1, nCS2, Chip Select: When CS0 and CS1are high and nCS2 is low, the chip is selected. Thisenables communication between the UART and theCPU. The positive edge of an active AddressStrobe signal latches the decoded chip selectsignals, completing chip selection. If nAS is alwayslow, valid chip selects should stabilize according tothe t CSW parameter.nCTS, Clear to Send: When low, this indicates thatthe MODEM or data set is ready to exchange data.MC16C550The nCTS signal is a MODEM status input whoseconditions can be tested by the CPU reading bit 4(CTS) of the MODEM Status Register. Bit 4 is thecomplement of the nCTS signal. Bit 0 (DCTS) ofthe MODEM Status Register indicates whether thenCTS input has changed state since the previousreading of the MODEM Status Register. nCTS hasno effect on the Transmitter.Note: Whenever the CTS bit of the MODEM Status Registerchanges state, an interrupt is generated if the MODEMStatus Interrupt is enabled.D7-D0, Data Bus: This bus comprises eightTRISTATE input/output lines. The bus providesbidirectional communications between the UARTand the CPU. Data, control words, and statusinformation are transferred via the D7-D0 Data Bus.nDCD, Data Carrier Detect: When low, indicatesthat the data carrier has been detected by theMODEM or data set. The nDCD signal is aMODEM status input whose condition can betested by the CPU reading bit 7 (DCD) of theMODEM Status Register. Bit 7 is the complementof the nDCD signal. Bit 3 (DDCD) of the MODEMStatus Register indicates whether the nDCD inputhas changed state since the previous reading of theMODEM Status Register. nDCD has no effect onthe receiver.Note: Whenever the DCD bit of the MODEM Status Registerchanges state, an interrupt is generated if the MODEMStatus Interrupt is enabled.nDDIS, Driver Disable: This goes low Wheneverthe CPU is reading data from the UART.It can disable or control the direction of a data bustransceiver between the CPU and the UART.nDSR, Data Set Ready: When low, this indicatesthat the MODEM or data set is ready to establishthe communications link with the UART. ThenDSR signal is a MODEM status input whosecondition can be tested by the CPU reading bit 5(DSR) of the MODEM Status Register. Bit 5 is thecomplement of the nDSR signal. Bit 1 (DDSR) ofthe MODEM Status Register indicates whether thenDSR input has changed state since the previousreading of the MODEM Status Register.Note: Whenever the DDSR bit of the MODEM Status Registerchanges state, an interrupt is generated if the MODEMStatus Interrupt is enabled.nDTR, Data Terminal Ready: When low, thisinforms the MODEM or data set that the UART isready to establish a communications link.The nDTR output signal can be set to an active lowby programming bit 0 (DTR) of the MODEMControl Register to a high level. A Master Resetoperation sets this signal to its inactive (high) state.Loop mode operation holds this signal in itsinactive state.INTR, Interrupt: This pin goes high whenever anyone of the following interrupt types has an activehigh condition and is enabled via the IER: ReceiverError Flag; Received Data Available: timeout(FIFO Mode only); Transmitter Holding RegisterEmpty; and MODEM Status. The INTR signal isMay 23, 2008 Ver. 1.06 10

MC16C550reset low upon the appropriate interrupt service or aMaster Reset operation.MRESET, Master Reset: When this input is high,it clears all the registers (except the ReceiverBuffer, Transmitter Holding, and Divisor Latches),and the control logic of the UART. The states ofvarious output signals (SOUT, INTR, nOUT 1,nOUT 2, nRTS, nDTR) are affected by an activeMRESET input (Refer to Table I.) This input isbuffered with a CMOS compatible Schmitt Triggerwith 0.5V typical hysteresis.nOUT 1, Output 1: This user-designated outputcan be set to an active low by programming bit 2(OUT 1) of the MODEM Control Register to a highlevel. A Master Reset operation sets this signal toits inactive (high) state. Loop mode operation holdsthis signal in its inactive state.nOUT 2, Output 2: This user-designated outputthat can be set to an active low by programming bit3 (OUT 2) of the MODEM Control Register to ahigh level. A Master Reset operation sets thissignal to its inactive (high) state.Loop mode operation holds this signal in itsinactive state.RCLK, Receiver Clock: This input is the 16 ×baud rate clock for the receiver section of the chip.IOR, nIOR, Read: When IOR is high or nIOR islow while the chip is selected, the CPU can readstatus information or data from the selected UARTregister.Note: Only an active IOR or nIOR input is required to transferdata from the UART during a read operation. Therefore,tie either the IOR input permanently low or the nIORinput permanently high, when it is not usednRI, Ring Indicator: When low, this indicates thata telephone ringing signal has been received by theMODEM or data set. The nRI signal is a MODEMstatus input whose condition can be tested by theCPU reading bit 6 (RI) of the MODEM StatusRegister. Bit 6 is the complement of the nRI signal.Bit 2 (TERI) of the MODEM Status Registerindicates whether the nRI input signal has changedfrom a low to a high state since the previousreading of the MODEM Status Register.Note: Whenever the RI bit of the MODEM Status Registerchanges from a high to a low state, an interrupt isgenerated if the MODEM Status Interrupt is enabled.nRTS, Request to Send: When low, this informsthe MODEM or data set that the UART is ready toexchange data. The nRTS output signal can be setto an active low by programming bit 1 (RTS) of theMODEM Control Register. A Master Resetoperation sets this signal to its inactive (high) state.Loop mode operation holds this signal in itsinactive state.SIN, Serial Input: Serial data input from theCommunications link (peripheral device, MODEM,or data set).SOUT, Serial Output: Composite serial data outputto the communications link (peripheral, MODEMor data set). The SOUT signal is set to the Marking(logic 1) state upon a Master Reset operation.nTXRDY, nRXRDY: Transmitter and ReceiverDMA signaling is available through two pins.When operating in the FIFO mode, one of twotypes of DMA signaling per pin can be selected viaFCR3. When operating as in the 16450 Mode, onlyDMA mode 0 is allowed. Mode 0 supports singletransfer DMA where a transfer is made betweenCPU bus cycles. Mode 1 supports multi transferDMA where multiple transfers are madecontinuously until the RCVR FIFO has beenemptied or the XMIT FIFO has been filled.RXRDY, Mode 0: When in the 16450 Mode(FCR0=0) or in the FIFO Mode (FCR0=1, FCR3=0)and there is at least 1 character in the RCVR FIFOor RCVR holding register, the RXRDY pin (29)will be low active. Once it is activated the RXRDYpin will go inactive when there are no morecharacters in the FIFO or holding register.RXRDY, Mode 1: In the FIFO Mode (FCR0=1)when the FCR3=1 and the trigger level or thetimeout has been reached, the RXRDY pin will golow active. Once it is activated it will go inactivewhen there are no more characters in the FIFO orholding register.TXRDY, Mode 0: In the 16450 Mode (FCR0=0)or in the FIFO Mode (FCR0=1, FCR3=0) and thereare no characters in the XMIT FIFO or XMITholding register, the TXRDY pin (24) will be lowactive. Once it is activated the TXRDY pin will goinactive after the first character is loaded into theXMIT FIFO or holding register.TXRDY, Mode 1: In the FIFO Mode (FCR0=1)when FCR3=1 and there are no characters in theXMIT FIFO, the TXRDY pin will go low active.This pin will become inactive when the XMITFIFO is completely full.VDD: +3.3V or 5V supply.VSS: Ground (0V) reference.IOW, nIOW, Write: When IOW is high or nIOWis low while the chip is selected, the CPU can writecontrol words or data into the selected UARTregister.Note: Only an active IOW or nIOW input is required to transferdata to the UART during a write operation. Therefore, tieeither the IOW input permanently low or the nIOW inputpermanently high, when it is not used.XTALIN (External Crystal Input): This signalinput is used in conjunction with XTALOUT toform a feedback circuit for the baud rate generator'soscillator. If a clock signal will be generated offchip,then it should drive the baud rate generatorthrough this pin.XTALOUT (External Crystal Output): This signaloutput is used in conjunction with XTALIN toform a feedback circuit for the baud rate generator'soscillator. If the clock signal will be generated offchip,then this pin is unused.May 23, 2008 Ver. 1.06 11

MC16C550TABLE Ⅰ. UART Reset ConfigurationRegister/Signal Reset Control Reset StateInterrupt Enable Register Master Reset 0000 0000 (Note 1)Interrupt Identification Register Master Reset 0000 0001FIFO Control Master Reset 0000 0000Line Control Register Master Reset 0000 0000MODEM Control Register Master Reset 0000 0000Line Status Register Master Reset 0110 0000MODEM Status Register Master Reset XXXX 0000 (Note 2)SOUT Master Reset HighINTR (RCVR Errs) Read LSR/MR LowINTR (RCVR Data Ready) Read RBR/MR LowINTR (THRE) Read IIR/Write THR/MR LowINTR (Modem Status Changes) Read MSR/MR LownOUT 2 Master Reset HighnRTS Master Reset HighnDTR Master Reset HighnOUT 1 Master Reset HighRCVR FIFO MR/FCR1•FCR0/∆FCR0 All Bits LowXMIT FIFO MR/FCR1•FCR0/∆FCR0 All Bits LowNote 1: Boldface bits are permanently low.Note 2: Bits 7-4 are driven by the input signals.May 23, 2008 Ver. 1.06 12

MC16C5506. Electrical CHARACTERISTICS6.1 Absolute Maximum RatingsTemperature Under Bias 0°C to +70°CStorage Temperature -65°C to +150°CAll Input or Output Voltageswith Respect to GND -0.5V to +7.0VPower Dissipation500mWNote: Maximum ratings indicate limits beyondwhich permanent damage may occur.Continuous operation at these limits is notintended and should be limited to thoseconditions specified under DC electricalcharacteristics.6.2. DC Electrical CharacteristicsT A = 0°C to +70°C , V DD =3.3V or 5V ± 10% , V SS = 0V unless otherwise specifiedSymbolV ILXV IHXV ILV IHV OLV OHI CC (AV)ParameterClock InputLow VoltageClock InputHigh VoltageInput LowVoltageInput HighVoltageOutput LowVoltageOutput HighVoltageAverage PowerSupplyCurrent (V DD )3.3V 5VMin Max Min MaxUnits-0.3 0.3 V DD -0.3 0.3 V DD V0.7 V DD V DD +0.3 0.7 V DD V DD +0.3 V-0.3 0.3 V DD -0.3 0.3 V DD V0.7 V DD V DD +0.3 0.7 V DD V DD +0.3 VConditions- 0.4 - 0.4 V I OL = 1.6 mA on all, Note 1V DD -0.4 - V DD -0.4 - V I OH = -1.0 mA , Note 1-4.5(Note 2)-10(Note 2)mAV DD = V DD max , No loads onoutput SIN, DSR, DCD, CTS(Note 3)I IL Input Leakage - ± 1 - ± 1 μA V DD = V DD max , V SS = 0VAll other pins floatingI CL Clock Leakage - ± 1 - ± 1 μAV ILMR MR Schmitt V IL - 0.2 V DD - 0.2 V DD VV IHMR MR Schmitt V IH 0.8 V DD - 0.8 V DD - VV IN = 0V, V DD max(Note 3)Note 1.Does not apply to XTALOUT.Note 2. T A = 25°CNote 3. V DD max = 3.6V (V DD =3.3V) or 5.5V (V DD =5.0V)Capacitance T A = 25°C , V DD = V SS = 0VSymbol Parameter Min Typ Max Units ConditionsC XIN Clock input Capacitance 15 20 pF f C = 1MHzC OUT Clock output Capacitance 20 30 pF Unmeasured pinsC IN Input Capacitance 6 10 pF Returned to V SSC OUT Output Capacitance 10 20 pFMay 23, 2008 Ver. 1.06 13

6.3. AC Characteristics T A = 0°C to +70°C, V DD = 3.3V or 5V ± 10%MC16C550Symbol Parameter Min Max Units Conditionst ADS Address Strobe Width 60 nst AH Address Hold Time 0 nst AR IOR, nIOR Delay from Address 30 ns Note 1t AS Address Setup Time 60 nst AW nIOW, IOW Delay from Address 30 ns Note 1t CH Chip Select Hold Time 0 nst CS Chip Select Setup Time 60 nst CSR nIOR, IOR Delay from Chip Select 30 ns Note 1t CSW nIOW, IOW Delay from Select 30 ns Note 1t DH Data Hold Time 30 nst DS Data Setup Time 30 nst HZ nIOR, IOR to Floating Data Delay 0 100 ns 100 pF loading, Note 3t MR Master Reset Pulse Width 20 nst RA Address Hold Time from nIOR, IOR 20 ns Note 1t RC Read Cycle Delay 125 nst RCS Chip Select Hold Time from nIOR, IOR 20 ns Note 1t RD nIOR. IOR Strobe Width 125 nst RDD nIOR, IOR to Driver Enable/Disable 60 ns 100 pF loading, Note 3t RVD Delay from nIOR, IOR to Data 125 ns 100 pF loadingt WA Address Hold Time from nIOW, IOW 20 ns Note 1t WC Write Cycle Delay 150 nst WCA Chip Select Hold Time from nIOW, IOW 20 ns Note 1t WR nIOW, IOW Strobe Width 100 nst XH Duration of Clock High Pulse 55 ns External Clock(8.0 MHz Max)t XL Duration of Clock Low Pulse 55 ns External Clock(8.0 MHz Max)RC Read Cycle = t AR + t RD + t RC 280 ns Note 4WC Write Cycle = t AW + t WR + t WC 280 nsBaud GeneratorN Baud Divisor 1 2 16 -1t BHD Baud Output Positive Edge Delay 175 ns 100 pF loadt BLD Baud Output Negative Edge Delay 175 ns 100 pF loadt HW Baud Output Up Time 75 ns f x = 8.0MHz, ÷2, 100 pF loadt LW Baud Output Down Time 100 ns f x = 8.0MHz, ÷2, 100 pF loadReceivert RINT Delay from nIOR, IOR ( RD RBR/ or RD1 μs 100 pF loadLSR) to Reset interruptt SCD Delay form RCLK to sample Time 2 μst SINT Delay from Stop to Set Interrupt 1 RCLKCyclesNote 2TransmitterSymbol Parameter Min Max Units Conditionst HR Delay from IOW, nIOW (WR THR)To Reset Interrupt 175 ns 100 pF loadt IR Delay from IOR, nIOR (RD IIR)To Reset Interrupt (THRE) 250 ns 100 pF loadt IRS Delay from Initial INTR Reset to TransmitBaudoutStart 8 24 Cyclest SI Delay from Initial Write to InterruptBaudout16 24 Cycles Note 5t STI Delay from Stop to Interrupt (THRE)Baudout8 8 Cycles Note 5t SXA Delay from Start to TXRDY activeBaudout8 Cycles 100 pF loadt WXI Delay from Write to TXRDY inactive 195 ns 100 pF loadMay 23, 2008 Ver. 1.06 14

MC16C550Modem Controlt MDO Delay from IOW, nIOW (WR MCR) toOutput 200 ns 100 pF loadt RIM Delay to Reset Interrupt from IOR, nIOR(RD MSR) 250 ns 100 pF loadt SIM Delay to Set Interrupt from MIDEMInput 250 ns 100 pF loadNotes1. Applicable only when nAS is tied low.2. In the FIFO mode (FCR0 = 1) the trigger level interrupts, the receiver data available indication, theactive RXRDY indication and the overrun error indication will be delayed 3 RCLKs. Status indicators(PE, FE, BI) will be delayed 3 RCLKs after the first byte has been received. For subsequently receivedbytes these indicators will be updated immediately after RDRBR goes inactive. Timeout interrupt isdelayed 8 RCLKs.3. Change and discharge time determined by V OL , V OH and the external loading.4. In FIFO mode RC = 425 ns (minimum) between reads of the receiver FIFO and the status registers(interrupt identification register or line status register).5. This delay will be lengthened by 1 character time, minus the last stop bit time if the transmitterinterrupt delay circuit is active (See FIFO interrupt Mode Operation)May 23, 2008 Ver. 1.06 15

MC16C5507. TIMING WAVEFOMS (All timings are referenced to valid 0 and valid 1)External Clock input (8.0 MHz Max)2.4VXIN0.4 VAT Test Points2.4 V2.2 V(Note 1) (Note 2)0.8 V0.4 Vt XTNote 1: The 2.4V and 0.4V levels are the voltages that the inputs are driven to during AC testing.Note 2: The 2.2V and 0.8V levels are the voltages at which the timing tests are made.BAUDOUT TimingXTALINt BHDNnBAUDOUT(÷ 1)t BLDt HWt BHD t LWt BLD t LWnBAUDOUT(÷ 2)t HWnnBAUDOUT(÷ 3)t BLDt BHDnBAUDOUT(÷ N.N > 3)t BLDt BHDt HWt LWt HW = (N -2) XINCYCLESt LW = 2 XINCYCLESMay 23, 2008 Ver. 1.06 16

MC16C550Write CyclenASt ADSA2, A1, A0t ASVALIDt AHt CS tCH t WA *nCS2, CS1, CS0VALIDt SCW *t AWWCt CSW *t WRt WCnIOW, IOWnIOR, IORDATAD0 – D7ACTIVEACTIVEACTIVEVALID DATAt DS t DHORRead CyclenASA2, A1, A0t ADSt AS t AHVALIDt CS tCH t RA *nCS2, CS1, CS0VALIDt CSR *t ARRCt RCS *t RDt RCnIOW, IOWnIOR, IORnDDISDATAD0 – D7ACTIVEACTIVEORt RDD t RDDt RVD tHZVALID DATAACTIVEMay 23, 2008 Ver. 1.06 17

MC16C550Receiver TimingRCLKSAMPLE CLKGM16C450 MODE:SINSTARTDATA (5 ~ 8)PARITYSTOPSAMPLE CLOCKRDR INTERRUPTLSI INTERRUPTnIOR, IOR (RDRBR)nIOR, IOR (RDLSR)Transmitter TimingSERIAL OUT (SOUT)INTERRUPT (THRE)t IRSSTRAT DATA (5 ~ 8) PARITY STOP (1 -2)t HRt SIt HRt IRSTRATt STInIOW, IOW (WTHR)NOTE 1*nIOR, IOR (RDIIR)NOTE 2*MODEM Control TimingnIOW, IOW (WRMCR)NOTE 1*nRTS, nDTR, nOUT1, nOUT2t MDOt MDOnCTS, nDSR, nDCDINTERRUTnIOR, IOR (RDMSR)NOTE 2*nRIt SIMt RIM tSIM t RIMt SIMNote 1: See Write Cycle TimingNote 2: See Read Cycle TimingMay 23, 2008 Ver. 1.06 18

MC16C550RCVR FIFO First Byte (This Sets RDR)SINSAMPLE CLOCKTRIGGER LEVEL INTERRUT(FCR 6,7 = 0,0)LSI INTERRUPT(FIFO AT ORABOVE TRIGGER LEVEL)(FIFO BELOWTRIGGER LEVEL)nIOR, IOR (RDLSR)nIOR, IOR (RDRBR)RCVR FIFO Bytes Other Than the First Byte (RDR Is Already Set)SINSAMPLE CLOCKTIMEOUT OR TRIGGERLEVEL INTERRUTLSI INTERRUPT(FIFO AT ORABOVE TRIGGER LEVEL)(FIFO BELOWTRIGGER LEVEL)nIOR, IOR (RDLSR)nIOR, IOR (RDRBR)PREVIOUS BYTEREAD FORM FIFOReceiver Ready FCR0=0 or FCR0=1 and FCR3=0 (Mode 0)nIOR, IOR (RDRBR)SIN(FIRST BYTE)SAMPLE CLOCKnRXRDYNote 1: This is the reading of the last byte in the FIFOsNote 2: If FCR0 = 1, then t SINT = 3 RCLKs. For a timeout interrupt, t SINT = 8 RCLKsMay 23, 2008 Ver. 1.06 19

MC16C550Receiver Ready FCR0 = 1 and FCR3 = 1 (Mode 1)nIOR, IOR (RDRBR)SIN(FIRST BYTE THATREACHES THETRIGGER LEVEL)SAMPLE CLKnRXRDYNote 1: This is the reading of the last byte in the FIFO.Note 2: If FCR0 = 1, t SINT = 3 RCLKs.Transmitter Ready FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)nIOW, IOW (WTHR)SOUTnTXRDYTransmitter Ready FCR0 = 1 and FCR3 = 1 (Mode 1)nIOW, IOW (WTHR)SOUTnTXRDYMay 23, 2008 Ver. 1.06 20

MC16C550May 23, 2008 Ver. 1.06 21

MC16C5508. REGISTERSThe system programmer may access any of theUART registers summarized in Table II via theCPU. These registers control UART operationsincluding transmission and reception of data. Eachregister bit in Table II has its name and reset stateshown.8.1 LINE CONTROL REGISTERThe system programmer specifies the format ofthe asynchronous data communications exchangeand set the Divisor Latch Access bit via the LineControl Register (LCR). The programmer can alsoread the contents of the Line Control Register. Theread capability simplifies system programming andeliminates the need for separate storage in systemmemory of the line characteristics. Table II showsthe contents of the LCR. Details on each bit follow:Bits 0 and 1: These two bits specify the number ofbits in each transmitted or received serial character.The encoding of bits 0 and 1 is as follows:Bit 1 Bit 0 Character Length0 0 5 Bits0 1 6 Bits1 0 7 Bits1 1 8 Bitsand 5 are logic 1 the Parity bit is transmitted andchecked as a logic 0. If bits 3 and 5 are 1 and bit 4is a logic 0 then the Parity bit is transmitted andchecked as a logic 1. If bit 5 is a logic 0 StickParity is disabled.Bit 6: This bit is the Break Control bit. It causes abreak condition to be transmitted to the receivingUART. When it is set to a logic 1, the serial output(SOUT) is forced to the Spacing (logic 0) state.The break is disabled by setting bit 6 to a logic 0.The Break Control bit acts only on SOUT and hasno effect on the transmitter logic.Note: This feature enables the CPU to alert a terminal in acomputer communications system. If the followingsequence is followed, no erroneous or extraneouscharacters will be transmitted because of the break.1. Load an all 0s, pad character, in response to THRE.2. Set break after the next THRE.3. Wait for the transmitter to be idle, (TEMT=1), and clear breakwhen normal transmission has to be restored.During the break, the Transmitter can be used as a charactertimer to accurately establish the break duration..Bit 7: This bit is the Divisor Latch Access Bit(DLAB). It must be set high (logic 1) to access theDivisor Latches of the Baud Generator during aRead or Write operation. It must be set low (logic 0)to access the Receiver Buffer, the TransmitterHolding Register, or the Interrupt Enable Register.8.2 TYPICAL CLOCK CIRCUITSBit 2: This bit specifies the number of Stop bitstransmitted and received in each serial character. Ifbit 2 is a logic 0, one Stop bit is generated in thetransmitted data. If bit 2 is a logic 1 when a 5-bitword length is selected via bits 0 and 1, one and ahalf Stop bits are generated. If bit 2 is a logic 1when either a 6-, 7-, or 8-bit word length is selected,two Stop bits are generated. The Receiver checksthe first Stop bit only, regardless of the number ofStop bits selected.Bit 3: This bit is the Parity Enable bit. When bit 3is a logic 1, a Parity bit is generated (transmit data)or checked (receive data) between the last dataword bit and Stop bit of the serial data. (The Paritybit is used to produce an even or odd number of 1swhen the data word bits and the Parity bit aresummed.)Bit 4: This bit is the Even Parity Select bit. Whenbit 3 is a logic 1 and bit 4 is a logic 0, an oddnumber of logic 1s is transmitted or checked in thedata word bits and Parity bit. When bit 3 is a logic1 and bit 4 is a logic 1, an even number of logic 1sis transmitted or checked.Bit 5: This bit is the Stick Parity bit. When bits 3, 4May 23, 2008 Ver. 1.06 22

MC16C550Typical Crystal Oscillator Network (Note)CRYSTAL Rp R X2 C 1 C 23.1MHz 1MΩ 1.5k 10-30 pF 40-60 pF1.8MHz 1MΩ 1.5k 10-30 pF 40-60 pFNote: These R and C values are approximate and may vary 2x depending on the crystal characteristics. Allcrystal circuits should be designed specifically for the system.TABLE III. Baud Rates, Divisors and Crystals1.8432MHz Crystal 3.072MHz Crystal 8.0MHz CrystalDecimal DivisorDecimal DivisorDecimal DivisorPercent ErrorPercent ErrorBaud Rate For 16XclockFor 16XclockFor 16XclockPercent Error50 2304 - 3840 - 10000 -75 1536 - 2560 - 6667 0.005110 1047 0.026 1745 0.026 4545 0.010134.5 857 0.058 1428 0.034 3717 0.013150 768 - 1280 - 3333 0.010300 384 - 640 - 1667 0.020600 192 - 320 - 833 0.0401200 96 - 160 - 417 0.0801800 64 - 107 0.312 277 0.0802000 58 0.69 96 - 250 -2400 48 - 80 - 208 0.1603600 32 - 53 0.628 139 0.0804800 24 - 40 - 104 0.1607200 16 - 27 1.23 69 0.6449600 12 - 20 - 52 0.16019200 6 - 10 - 26 0.16038400 3 - 5 - 13 0.16056000 2 2.86 - - 9 0.790128000 - - - - 4 2.344256000 - - - - 2 2.344May 23, 2008 Ver. 1.06 23

8.3 PROGRAMMABLE BAUDGENERATORThe UART contains a programmable BaudGenerator that is capable of taking any clock inputfrom DC to 24 MHz and dividing it by any divisorfrom 2 to 2 16 -1. The output frequency of the BaudGenerator is 16 × the Baud [divisor #=(frequency input) ÷ (baud rate × 16)]. Two 8-bitlatches store the divisor in a 16-bit binary format.These Divisor Latches must be loaded duringinitialization to ensure proper operation of the BaudGenerator. Upon loading either of the DivisorLatches, a 16-bit Baud counter is immediatelyloaded.Table III provides decimal divisors to use withcrystal frequencies of 1.8432 MHz, 3.072 MHz and8.0 MHz, respectively. For baud rates of 38400 andbelow, the error obtained is minimal. The accuracyof the desired baud rate is dependent on the crystalfrequency chosen. Using a divisor of zero is notrecommended.8.4 LINE STATUS REGISTERThis register provides status information to theCPU concerning the data transfer. Table II showsthe contents of the Line Status Register. Details oneach bit follow.Bit 0: This bit is the receiver Data Ready (DR)indicator. Bit 0 is set to a logic 1 whenever acomplete incoming character has been received andtransferred into the Receiver Buffer Register or theFIFO. Bit 0 is reset to a logic 0 by reading all of thedata in the Receiver Buffer Register or the FIFO.Bit 1: This bit is the Overrun Error (OE) indicator.Bit 1 indicates that data in the Receiver BufferRegister was not read by the CPU before the nextcharacter was transferred into the Receiver BufferRegister, thereby destroying the previous character.The OE indicator is set to a logic 1 upon detectionof an overrun condition and reset whenever theCPU reads the contents of the Line Status Register.If the FIFO mode data continues to fill the FIFObeyond the trigger level, an overrun error willoccur only after the FIFO is full and the nextcharacter has been completely received in the shiftregister. OE is indicated to the CPU as soon as ithappens. The character in the shift register isoverwritten, but it is not transferred to the FIFO.Bit 2: This bit is the Parity Error (PE) indicator. Bit2 indicates that the received data character does nothave the correct even or odd parity, as selected bythe even-parity select bit. The PE bit is set to alogic 1 upon detection of a parity error and is resetto a logic 0 whenever the CPU reads the contentsof the Line Status Register. In the FIFO mode thisMC16C550error is associated with the particular character inthe FIFO it applies to. This error is revealed to theCPU when its associated character is at the top ofthe FIFO.Bit 3: This bit is the Framing Error (FE) indicator.Bit 3 indicates that the received character did nothave a valid Stop bit. Bit 3 is set to a logic 1whenever the Stop bit following the last data bit orparity bit is detected as a logic 0 bit (Spacing level).The FE indicator is reset whenever the CPU readsthe contents of the Line Status Register. In theFIFO mode this error is associated with theparticular character in the FIFO it applies to. Thiserror is revealed to the CPU when its associatedcharacter is at the top of the FIFO. The UART willtry to resynchronize after a framing error. To dothis it assumes that the framing error was due to thenext start bit, so it samples this ``start'' bit twiceand then takes in the ``data''.Bit 4: This bit is the Break Interrupt (BI) indicator.Bit 4 is set to a logic 1 whenever the received datainput is held in the Spacing (logic 0) state forlonger than a full word transmission time (that is,the total time of Start bit + data bits + Parity + Stopbits). The BI indicator is reset whenever the CPUreads the contents of the Line Status Register. Inthe FIFO mode this error is associated with theparticular character in the FIFO it applies to. Thiserror is revealed to the CPU when its associatedcharacter is at the top of the FIFO. When breakoccurs only one zero character is loaded into theFIFO. The next character transfer is enabled afterSIN goes to the marking state and receives the nextvalid start bit.Note: Bits 1 through 4 are the error conditions that produce aReceiver Line Status interrupt whenever any of thecorresponding conditions are detected and the interrupt isenabled.Bit 5: This bit is the Transmitter Holding RegisterEmpty (THRE) indicator. Bit 5 indicates that theUART is ready to accept a new character fortransmission. In addition, this bit causes the UARTto issue an interrupt to the CPU when the TransmitHolding Register Empty Interrupt enable is set high.The THRE bit is set to a logic 1 when a character istransferred from the Transmitter Holding Registerinto the Transmitter Shift Register. The bit is resetto logic 0 concurrently with the loading of theTransmitter Holding Register by the CPU. In theFIFO mode this bit is set when the XMIT FIFO isempty; it is cleared when at least 1 byte is writtento the XMIT FIFO.Bit 6: This bit is the Transmitter Empty (TEMT)indicator. Bit 6 is set to a logic 1 whenever theTransmitter Holding Register (THR) and theTransmitter Shift Register (TSR) are both empty. Itis reset to a logic 0 whenever either the THR orTSR contains a data character. In the FIFO modethis bit is set to one whenever the transmitter FIFOand shift register are both empty.May 23, 2008 Ver. 1.06 24

MC16C550Bit 7: In the 16450 Mode this is a 0. In the FIFOmode LSR7 is set when there is at least one parityerror, framing error or break indication in the FIFO.LSR7 is cleared when the CPU reads the LSR, ifthere are no subsequent errors in the FIFO.Note: The Line Status Register is intended for read operationsonly. Writing to this register is not recommended as thisoperation is only used for factory testing. In the FIFOmode the software must load a data byte in the Rx FIFOvia Loopback Mode in order to write to LSR2-LSR4.LSR0 and LSR7 can't be written to in FIFO mode.8.5 FIFO CONTROL REGISTERThis is a write only register at the same locationas the IIR (the IIR is a read only register). Thisregister is used to enable the FIFOs, clear theFIFOs, set the RCVR FIFO trigger level, and selectthe type of DMA signaling.Bit 0: Writing a 1 to FCR0 enables both the XMITand RCVR FIFOs. Resetting FCR0 will clear allbytes in both FIFOs. When changing from theFIFO Mode to the 16450 Mode and vice versa, datais automatically cleared from the FIFOs. This bitmust be a 1 when other FCR bits are written to orthey will not be programmed.Bit 1: Writing a 1 to FCR1 clears all bytes in theRCVR FIFO and resets its counter logic to 0. Theshift register is not cleared. The 1 that is written tothis bit position is self-clearing.Bit 2: Writing a 1 to FCR2 clears all bytes in theXMIT FIFO and resets its counter logic to 0. Theshift register is not cleared. The 1 that is written tot his bit position is self-clearing.Bit 3: Setting FCR3 to a 1 will cause the RXRDYand TXRDY pins to change from mode 0 to mode1 if FCR0=1(see description of RXRDY andTXRDY pins).Bit 4, 5: FCR4 to FCR5 are reserved for future use.Bit 6, 7: FCR6 and FCR7 are used to set the triggerlevel for the RCVR FIFO interrupt.7 6RCVR FIFOTrigger Level (Bytes )0 0 010 1 041 0 081 1 148.6 INTERRUPT IDENTIFICATIONREGISTERIn order to provide minimum software overheadduring data character transfers, the UARTprioritizes interrupts into four levels and recordsthese in the interrupt Identification Register. Thefour levels of interrupt conditions in order ofpriority are Receiver Line Status; Received DataReady; Transmitter Holding Register Empty; andMODEM Status. When the CPU accesses the IIR,the UART freezes all interrupts and indicates thehighest priority pending interrupt to the CPU.While this CPU access is occurring, the UARTrecords new interrupts, but does not change itscurrent indication until the access is complete.May 23, 2008 Ver. 1.06 25

MC16C550Table II shows the contents of the IIR. Details oneach bit follow:Bit 0: This bit can be used in a prioritized interruptenvironment to indicate whether an interrupt ispending. When bit 0 is a logic 0, an interrupt ispending and the IIR contents may be used as apointer to the appropriate interrupt service routine.When bit 0 is a logic 1, no interrupt is pending.Bits 1 and 2: These two bits of the IIR are used toidentify the highest priority interrupt pending asindicated in Table IV.Bit 3: In the 16450 Mode this bit is 0. In the FIFOmode this bit is set along with bit 2 when a timeoutinterrupt is pending.Bits 4 and 5: These two bits of the IIR are alwayslogic 0.Bits 6 and 7: These two bits are set when FCR0=1.8.7 INTERRUPT ENABLE REGISTERThis register enables the five types of UARTinterrupts. Each interrupt can individually activatethe interrupt (INTR) output signal. It is possible tototally disable the interrupt system by resetting bits0 through 3 of the Interrupt Enable Register (IER).Similarly, setting bits of the IER register to a logic1, enables the selected interrupt(s). Disabling aninterrupt prevents it from being indicated as activein the IIR and from activating the INTR outputsignal. All other system functions operate in theirnormal manner, including the setting of the LineStatus and MODEM Status Registers. Table IIshows the contents of the IER. Details on each bitfollow.Bit 0: This bit enables the Received Data AvailableInterrupt (and timeout interrupts in the FIFO mode)when set to logic 1.Bit 1: This bit enables the Transmitter HoldingRegister Empty Interrupt when set to logic 1.Bit 2: This bit enables the Receiver Line StatusInterrupt when set to logic 1.Bit 3: This bit enables the MODEM StatusInterrupt when set to logic 1.Bits 4 through 7: These four bits are always logic0.8.8 MODEM CONTROL REGISTERThis register controls the interface with theMODEM or data set (or a peripheral deviceemulating a MODEM). The contents of theMODEM Control Register are indicated in Table IIand are described below.Bit 0: This bit controls the Data Terminal Ready(nDTR) output. When bit 0 is set to a logic 1, thenDTR output is forced to a logic 0. When bit 0 isreset to a logic 0, the nDTR output is forced to alogic 1.Note: The nDTR output of the UART may be applied to an EIAinverting line driver to obtain the proper polarity input atthe succeeding MODEM or data set.Bit 1: This bit controls the Request to Send (nRTS)output. Bit 1 affects the nRTS output in a manneridentical to that described above for bit 0.Bit 2: This bit controls the Output 1 (nOUT 1)signal, which is an auxiliary user-designated output.Bit 2 affects the nOUT 1 output in a manneridentical to that described above for bit 0.Bit 3: This bit controls the Output 2 (nOUT 2)signal, which is an auxiliary user-designated output.Bit 3 affects the nOUT 2 output in a manneridentical to that described above for bit 0.Bit 4: This bit provides a local loopback feature fordiagnostic testing of the UART. When bit 4 is setto logic 1, the following occur: the transmitterSerial Output (SOUT) is set to the Marking (logic 1)state; the receiver Serial Input (SIN) isdisconnected; the output of the Transmitter ShiftRegister is ``looped back'' into the Receiver ShiftRegister input; the four MODEM Control inputs(nDSR, nCTS, RI, and nDCD) are disconnected;and the four MODEM Control outputs n(DTR,nRTS, nOUT 1, and nOUT 2) are internallyconnected to the four MODEM Control inputs, andthe MODEM Control output pins are forced to theirinactive state (high). In the loopback mode, datathat is transmitted is immediately received. Thisfeature allows the processor to verify the transmitandreceived-data paths of the UART. In theloopback mode, the receiver and transmitterinterrupts are fully operational. Their sources areexternal to the part. The MODEM ControlInterrupts are also operational, but the interrupts'sources are now the lower four bits of the MODEMControl Register instead of the four MODEMControl inputs. The interrupts are still controlled bythe Interrupt Enable Register.Bits 5 through 7: These bits are permanently set tologic 0.8.9 MODEM STATUS REGISTERThis register provides the current state of thecontrol lines from the MODEM (or peripheraldevice) to the CPU. In addition to this current-stateinformation, four bits of the MODEM StatusRegister provide change information. These bits areset to a logic 1 whenever a control input from theMay 23, 2008 Ver. 1.06 26

MODEM changes state. They are reset to logic 0whenever the CPU reads the MODEM StatusRegister. The contents of the MODEM StatusRegister are indicated in Table II and describedbelow.Bit 0: This bit is the Delta Clear to Send (DCTS)indicator. Bit 0 indicates that the nCTS input to thechip has changed state since the last time it wasread by the CPU.Bit 1: This bit is the Delta Data Set Ready (DDSR)indicator. Bit 1 indicates that the nDSR input to thechip has changed state since the last time it wasread by the CPU.Bit 2: This bit is the Trailing Edge of RingIndicator (TERI) detector. Bit 2 indicates that thenRI input to the chip has changed from a low to ahigh state.Bit 3: This bit is the Delta Data Carrier Detect(DDCD) indicator. Bit 3 indicates that the nDCDinput to the chip has changed state.Note: Whenever bit 0, 1, 2, or 3 is set to logic 1, a MODEMStatus Interrupt is generated.Bit 4: This bit is the complement of the Clear toSend (nCTS) input. If bit 4 (loop) of the MCR isset to a 1, this bit is equivalent to RTS in the MCR.Bit 5: This bit is the complement of the Data SetReady (nDSR) input. If bit 4 of the MCR is set to a1, this bit is equivalent to DTR in the MCR.Bit 6: This bit is the complement of the RingIndicator (nRI) input. If bit 4 of the MCR is set to a1, this bit is equivalent to OUT 1 in the MCR.Bit 7: This bit is the complement of the DataCarrier Detect (nDCD) input. If bit 4 of the MCR isset to a 1, this bit is equivalent to OUT 2 in theMCR.8.10 SCRATCHPAD REGISTERThis 8-bit Read/Write Register does not controlthe UART in anyway. It is intended as a scratchpadregister to be used by the programmer to hold datatemporarily.8.11 FIFO INTERRUPT MODEOPERATIONWhen the RCVR FIFO and receiver interruptsare enabled (FCR0=1, IER0=1) RCVR interruptswill occur as follows:A. The receive data available interrupt will beissued to the CPU when the FIFO has reached itsprogrammed trigger level; it will be cleared assoon as the FIFO drops below its programmedtrigger level.MC16C550B. The IIR receive data available indication alsooccurs when the FIFO trigger level is reached,and like the interrupt it is cleared when the FIFOdrops below the trigger level.C. The receiver line status interrupt (IIR=06), asbefore, has higher priority than the received dataavailable (IIR=04) interrupt.D. The data ready bit (LSR0) is set as soon as acharacter is transferred from the shift register tothe RCVR FIFO. It is reset when the FIFO isempty.When RCVR FIFO and receiver interrupts areenabled, RCVR FIFO timeout interrupts will occuras follows:A. A FIFO timeout interrupt will occur, if thefollowing conditions exist:- at least one character is in the FIFO- the most recent serial character receivedwas longer than 4 continuous charactertimes ago (if 2stop bits are programmed thesecond one is included in this time delay).- the most recent CPU read of the FIFO waslonger than 4 continuous character timesago.The maximum time between a received characterand a timeout interrupt will be 160 ms at 300baud with a 12-bit receive character (i.e., 1 Start,8 Data, 1 Parity and 2 Stop Bits).B. Character times are calculated by using theRCLK input for a clock signal (this makes thedelay proportional to the baud rate).C. When a timeout interrupt has occurred it iscleared and the timer reset when the CPU readsone character from the RCVR FIFO.D. When a timeout interrupt has not occurred thetimeout timer is reset after a new character isreceived or after the CPU reads the RCVR FIFO.When the XMIT FIFO and transmitter interruptsare enabled (FCR0=1, IER1=1), XMIT interruptswill occur as follows:A. The transmitter holding register interrupt (02)occurs when the XMIT FIFO is empty; it iscleared as soon as the transmitter holdingregister is written to (1 to 16 characters may bewritten to the XMIT FIFO while servicing thisinterrupt) or the IIR is read.B. The transmitter FIFO empty indications will bedelayed 1 character time minus the last stop bittime whenever the following occurs: THRE=1 andthere have not been at least two bytes at the sametime in the transmit FIFO, since the last THRE=1.The first transmitter interrupt after changing FCR0will be immediate, if it is enabled.Character timeout and RCVR FIFO triggerlevel interrupts have the same priority as thecurrent received data available interrupt; XMITFIFO empty has the same priority as the currenttransmitter holding register empty interrupt.May 23, 2008 Ver. 1.06 27

MC16C5508.12 FIFO POLLED MODE OPERATIONWith FCR0=1 resetting IER0, IER1, IER2, IER3or all to zero puts the UART in the FIFO PolledMode of operation. Since the RCVR andXMITTER are controlled separately either one orboth can be in the polled mode of operation. In thismode the user's program will check RCVR andXMITTER status via the LSR. As stated previously:LSR0 will be set as long as there is one byte inthe RCVR FIFO.LSR1 to LSR4 will specify which error(s) hasoccurred. Character error status is handled thesame way as when in the interrupt mode, theIIR is not affected since IER2=0.LSR5 will indicate when the XMIT FIFO isempty.LSR6 will indicate that both the XMIT FIFOand shift register are empty.LSR7 will indicate whether there are any errorsin the RCVR FIFO.There is no trigger level reached or timeoutcondition indicated in the FIFO Polled Mode,however, the RCVR and XMIT FIFOs are stillfully capable of holding characters.May 23, 2008 Ver. 1.06 28

MC16C5509. TYPICAL APPLICATIONSThis shows the basic connections of an MC16C550 to an 8088 CPUMay 23, 2008 Ver. 1.06 29