ATmega32A Datasheet - Sunrom Technologies

ATmega32A14.6.1 Compare Output Mode and Waveform GenerationThe Waveform Generator uses the COM0[1:0] bits differently in normal, CTC, and PWM modes.For all modes, setting the COM0[1:0] = 0 tells the waveform generator that no action on the OC0Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 14-3 on page 85. For fast PWM mode, refer to Table 14-4 on page85, and for phase correct PWM refer to Table 14-5 on page 86.A change of the COM0[1:0] bits state will have effect at the first compare match after the bits arewritten. For non-PWM modes, the action can be forced to have immediate effect by using theFOC0 strobe bits.14.7 Modes of OperationThe mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins,is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Outputmode (COM0[1:0]) bits. The Compare Output mode bits do not affect the countingsequence, while the Waveform Generation mode bits do. The COM0[1:0] bits control whetherthe PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM0[1:0] bits control whether the output should be set, cleared, or toggled ata compare match (See “Compare Match Output Unit” on page 77.).For detailed timing information refer to Figure 14-8, Figure 14-9, Figure 14-10 and Figure 14-11in “Timer/Counter Timing Diagrams” on page 82.14.7.1 Normal ModeThe simplest mode of operation is the normal mode (WGM01:0 = 0). In this mode the countingdirection is always up (incrementing), and no counter clear is performed. The counter simplyoverruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom(0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the sametimer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninthbit, except that it is only set, not cleared. However, combined with the timer overflow interruptthat automatically clears the TOV0 Flag, the timer resolution can be increased by software.There are no special cases to consider in the normal mode, a new counter value can be writtenanytime.The output compare unit can be used to generate interrupts at some given time. Using the outputcompare to generate waveforms in Normal mode is not recommended, since this will occupytoo much of the CPU time.14.7.2 Clear Timer on Compare Match (CTC) ModeIn Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0 Register is used to manipulatethe counter resolution. In CTC mode the counter is cleared to zero when the counter value(TCNT0) matches the OCR0. The OCR0 defines the top value for the counter, hence also itsresolution. This mode allows greater control of the compare match output frequency. It also simplifiesthe operation of counting external events.The timing diagram for the CTC mode is shown in Figure 14-5. The counter value (TCNT0)increases until a compare match occurs between TCNT0 and OCR0, and then counter (TCNT0)is cleared.8155C–AVR–02/1178