ATmega32A Datasheet - Sunrom Technologies

ATmega32A• MOSI – Port B, Bit 5MOSI: SPI Master Data output, Slave Data input for SPI. When the SPI is enabled as a Slave,this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled asa Master, the data direction of this pin is controlled by DDB5. When the pin is forced by the SPIto be an input, the pull-up can still be controlled by the PORTB5 bit.• SS – Port B, Bit 4SS: Slave Select input. When the SPI is enabled as a Slave, this pin is configured as an inputregardless of the setting of DDB4. As a Slave, the SPI is activated when this pin is driven low.When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB4. Whenthe pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB4 bit.• AIN1/OC0 – Port B, Bit 3AIN1, Analog Comparator Negative Input. Configure the port pin as input with the internal pull-upswitched off to avoid the digital port function from interfering with the function of the analogcomparator.OC0, Output Compare Match output: The PB3 pin can serve as an external output for theTimer/Counter0 Compare Match. The PB3 pin has to be configured as an output (DDB3 set(one)) to serve this function. The OC0 pin is also the output pin for the PWM mode timerfunction.• AIN0/INT2 – Port B, Bit 2AIN0, Analog Comparator Positive input. Configure the port pin as input with the internal pull-upswitched off to avoid the digital port function from interfering with the function of the AnalogComparator.INT2, External Interrupt Source 2: The PB2 pin can serve as an external interrupt source to theMCU.• T1 – Port B, Bit 1T1, Timer/Counter1 Counter Source.• T0/XCK – Port B, Bit 0T0, Timer/Counter0 Counter Source.XCK, USART External Clock. The Data Direction Register (DDB0) controls whether the clock isoutput (DDB0 set) or input (DDB0 cleared). The XCK pin is active only when the USART operatesin Synchronous mode.Table 12-7 and Table 12-8 relate the alternate functions of Port B to the overriding signalsshown in Figure 12-5 on page 56. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute theMISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.8155C–AVR–02/1160