ATmega32A Datasheet - Sunrom Technologies

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<strong>ATmega32A</strong>Mnemonics Operands Description Operation Flags #ClocksBRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1 / 2BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1 / 2BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1 / 2BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1 / 2BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1 / 2DATA TRANSFER INSTRUCTIONSMOV Rd, Rr Move Between Registers Rd ← Rr None 1MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1LDI Rd, K Load Immediate Rd ← K None 1LD Rd, X Load Indirect Rd ← (X) None 2LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2LD Rd, Y Load Indirect Rd ← (Y) None 2LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2LD Rd, Z Load Indirect Rd ← (Z) None 2LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2LDS Rd, k Load Direct from SRAM Rd ← (k) None 2ST X, Rr Store Indirect (X) ← Rr None 2ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2ST Y, Rr Store Indirect (Y) ← Rr None 2ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2ST Z, Rr Store Indirect (Z) ← Rr None 2ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2STS k, Rr Store Direct to SRAM (k) ← Rr None 2LPM Load Program Memory R0 ← (Z) None 3LPM Rd, Z Load Program Memory Rd ← (Z) None 3LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3SPM Store Program Memory (Z) ← R1:R0 None -IN Rd, P In Port Rd ← P None 1OUT P, Rr Out Port P ← Rr None 1PUSH Rr Push Register on Stack Stack ← Rr None 2POP Rd Pop Register from Stack Rd ← Stack None 2BIT AND BIT-TEST INSTRUCTIONSSBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0:6 Z,C,N,V 1SWAP Rd Swap Nibbles Rd(3:0)←Rd(7:4),Rd(7:4)←Rd(3:0) None 1BSET s Flag Set SREG(s) ← 1 SREG(s) 1BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1BST Rr, b Bit Store from Register to T T ← Rr(b) T 1BLD Rd, b Bit load from T to Register Rd(b) ← T None 1SEC Set Carry C ← 1 C 1CLC Clear Carry C ← 0 C 1SEN Set Negative Flag N ← 1 N 1CLN Clear Negative Flag N ← 0 N 1SEZ Set Zero Flag Z ← 1 Z 1CLZ Clear Zero Flag Z ← 0 Z 1SEI Global Interrupt Enable I ← 1 I 1CLI Global Interrupt Disable I ← 0 I 1SES Set Signed Test Flag S ← 1 S 1CLS Clear Signed Test Flag S ← 0 S 1SEV Set Twos Complement Overflow. V ← 1 V 1CLV Clear Twos Complement Overflow V ← 0 V 18155C–AVR–02/11338
<strong>ATmega32A</strong>Mnemonics Operands Description Operation Flags #ClocksSET Set T in SREG T ← 1 T 1CLT Clear T in SREG T ← 0 T 1SEH Set Half Carry Flag in SREG H ← 1 H 1CLH Clear Half Carry Flag in SREG H ← 0 H 1MCU CONTROL INSTRUCTIONSNOP No Operation None 1SLEEP Sleep (see specific descr. for Sleep function) None 1WDR Watchdog Reset (see specific descr. for WDR/timer) None 1BREAK Break For On-Chip Debug Only None N/A8155C–AVR–02/11339
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ATmega32A2. OverviewThe Atmel ® AV
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ATmega32Ametrical drive characteris
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ATmega32A6.3.1 SREG - AVR Status Re
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ATmega32A6.4.1 The X-register, Y-re
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ATmega32AFigure 6-5.Single Cycle AL
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ATmega32AA return from an interrupt
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ATmega32AFigure 7-2.Data Memory Map
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ATmega32AEEPROM data corruption can
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ATmega32ASupport - Read-While-Write
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ATmega32AThe next code examples sho
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ATmega32A8.1.3 Flash Clock - clk FL
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ATmega32AThe CKSEL0 Fuse together w
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ATmega32A8.7 Calibrated Internal RC
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ATmega32A8.10 Register Description8
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ATmega32Aface, Timer/Counters, Watc
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ATmega32A9.8.4 Internal Voltage Ref
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ATmega32A10. System Control and Res
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ATmega32AFigure 10-3.MCU Start-up,
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ATmega32AADC is used. To reduce pow
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ATmega32AThe WDP2, WDP1, and WDP0 b
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ATmega32Athe case if the Reset Vect
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ATmega32A$382D out SPL,r16$382E sei
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ATmega32A12. I/O Ports12.1 Overview
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ATmega32AIf PORTxn is written logic
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ATmega32AThe following code example
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ATmega32AFigure 12-5. Alternate Por
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ATmega32ATable 12-3.Table 12-4 and
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ATmega32A• MOSI - Port B, Bit 5MO
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ATmega32A12.3.3 Alternate Functions
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ATmega32ATable 12-11. Overriding Si
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ATmega32A12.4.13 PIND - Port D Inpu
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ATmega32Alow level interrupt is sel
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ATmega32A14. 8-bit Timer/Counter0 w
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ATmega32ASignal description (intern
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ATmega32Athe OCR0 value, the compar
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ATmega32AFigure 14-5.CTC Mode, Timi
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ATmega32AThe PWM resolution for the
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ATmega32AFigure 14-9. Timer/Counter
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ATmega32ATable 14-2. Waveform Gener
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ATmega32AThe Output Compare Registe
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ATmega32AFigure 15-1.T1/T0 Pin Samp
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ATmega32A16. 16-bit Timer/Counter11
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ATmega32Aput Compare Units” on pa
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ATmega32Athe main code and the inte
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ATmega32A16.5 Counter UnitThe main
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ATmega32AThe ICR1 Register can only
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ATmega32ARegister to either TOP or
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ATmega32AA change of the COM1x1:0 b
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ATmega32AThe PWM resolution for the
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ATmega32AUsing the ICR1 Register fo
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ATmega32ATable 16-3 shows the COM1x
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ATmega32A• Bit 7 - ICNC1: Input C
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ATmega32AThe Input Capture is updat
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ATmega32A17. 8-bit Timer/Counter2 w
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ATmega32AFigure 17-2.DATA BUSCounte
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ATmega32AThe setup of the OC2 shoul
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ATmega32AFigure 17-5.CTC Mode, Timi
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ATmega32A17.7.4 Phase Correct PWM M
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ATmega32AFigure 17-9. Timer/Counter
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ATmega32A• If Timer/Counter2 is u
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ATmega32AA FOC2 strobe will not gen
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ATmega32A17.11.2 TCNT2 - Timer/Coun
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ATmega32A17.11.7 SFIOR - Special Fu
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ATmega32Acommunication cycle when p
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ATmega32AAssembly Code Example (1)S
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ATmega32A18.3 SS Pin Functionality1
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ATmega32A18.3.4 SPSR - SPI Status R
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ATmega32A19. USART19.1 Features19.2
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ATmega32A19.2.1 AVR USART vs. AVR U
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ATmega32ATable 19-1.Operating ModeA
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ATmega32AThe frame format used by t
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ATmega32AThe Transmit Complete (TXC
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ATmega32AAssembly Code Example (1)U
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ATmega32AThe PE bit is set if the n
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ATmega32AFigure 19-7.Stop Bit Sampl
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ATmega32AIf the receiver is set up
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ATmega32A• Bit 0 - MPCM: Multi-pr
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ATmega32ATable 19-6.USBS Bit Settin
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ATmega32ATable 19-9.BaudRate(bps)Ex
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ATmega32ATable 19-11.BaudRate(bps)E
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ATmega32A20. Two-wire Serial Interf
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ATmega32Acondition is issued betwee
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ATmega32AFigure 20-6.Typical Data T
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ATmega32AFigure 20-9.Overview of th
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ATmega32A20.6 Using the TWIThe AVR
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ATmega32AAssembly code example C ex
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ATmega32ATable 20-2.Status Code(TWS
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ATmega32AFigure 20-12. Formats and
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ATmega32AThe upper seven bits are t
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ATmega32AFigure 20-16. Formats and
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ATmega32A4. The transfer must be fi
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ATmega32A20.9.2 TWCR - TWI Control
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ATmega32A20.9.5 TWAR - TWI (Slave)
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ATmega32A22. Analog to Digital Conv
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ATmega32AIf differential channels a
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ATmega32Ain ADCSRA. The prescaler k
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ATmega32ATable 22-1.ConditionADC Co
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ATmega32AIf the user has a fixed vo
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ATmega32AFigure 22-9.ADC Power Conn
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INLATmega32AFigure 22-12. Integral
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ATmega32ATable 22-2.Correlation bet
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ATmega32ATable 22-4.MUX4:011010 ADC
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ATmega32A22.9.4 SFIOR - Special Fun
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ATmega32A• TMS: Test Mode Select.
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ATmega32AThe TMS input must be held
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ATmega32A23.8 Using the JTAG Progra
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ATmega32A24.3.1 Bypass RegisterThe
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ATmega32AThe active states are:•
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ATmega32AFigure 24-4. General Port
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ATmega32AFigure 24-7.Boundary-scan
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ATmega32ATable 24-4.SignalNameBound
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ATmega32ATable 24-5.SignalNameBound
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ATmega32ATable 24-6.Algorithm for U
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ATmega32ATable 24-7. ATmega32A Boun
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ATmega32ATable 24-7. ATmega32A Boun
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ATmega32A25. Boot Loader Support -
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ATmega32AFigure 25-1.Read-While-Wri
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ATmega32Amemory by SPM instruction.
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ATmega32ANotes: 1. The different va
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ATmega32A25.8.8 EEPROM Write Preven
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ATmega32Asbiw loophi:looplo, 2brne
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ATmega32A26. Memory Programming26.1
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ATmega32ATable 26-4.Fuse Low ByteFu
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ATmega32ATable 26-7.Signal Name inP
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ATmega32Achanged. A Chip Erase must
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ATmega32AFigure 26-3. Programming t
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ATmega32A3. Set BS1 to “0” and
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ATmega32A26.7.14 Parallel Programmi
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ATmega32A26.9 SPI Serial Programmin
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ATmega32Awithout chip erasing the d
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ATmega32A26.9.4 SPI Serial Programm
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Page 289 and 290: ATmega32AFigure 26-14. Programming
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Page 303 and 304: ATmega32ATable 27-3. SPI Timing Par
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Page 309 and 310: ATmega32AFigure 28-4.Active Supply
Page 311 and 312: ATmega32AFigure 28-8.Idle Supply Cu
Page 313 and 314: ATmega32AFigure 28-12. Idle Supply
Page 315 and 316: ATmega32A28.5 Standby Supply Curren
Page 317 and 318: ATmega32AFigure 28-20. Reset Pull-u
Page 319 and 320: ATmega32AFigure 28-24. I/O Pin Sink
Page 321 and 322: ATmega32AFigure 28-28. Reset Input
Page 323 and 324: ATmega32AFigure 28-32. BOD Threshol
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Page 331 and 332: ATmega32AFigure 28-48. ADC Current
Page 333 and 334: ATmega32A28.12 Current Consumption
Page 335 and 336: ATmega32A29. Register SummaryAddres
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Page 341 and 342: ATmega32A32. Packaging Information3
Page 343 and 344: ATmega32A32.3 44M1DMarked Pin# 1 ID
Page 345 and 346: ATmega32A34. Datasheet Revision His
Page 347 and 348: ATmega32A8.9 Timer/Counter Oscillat
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Page 351 and 352: ATmega32A26 Memory Programming ....
Page 353: Atmel Corporation2325 Orchard Parkw
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ATmega32A Datasheet - Sunrom Technologies

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