ATmega32A Datasheet - Sunrom Technologies

ATmega32ATable 27-2.t SU;STOt BUFTwo-wire Serial Bus Requirements (Continued)Symbol Parameter Condition Min Max UnitsSetup time for STOP conditionBus free time between a STOP and STARTconditionf SCL ≤ 100kHz 4.0 – µsf SCL > 100kHz 0.6 – µsf SCL ≤ 100kHz 4.7 – µsf SCL > 100kHz 1.3 – µsNotes: 1. In ATmega32A, this parameter is characterized and not 100% tested.2. Required only for f SCL > 100kHz.3. C b = capacitance of one bus line in pF.4. f CK = CPU clock frequency5. This requirement applies to all ATmega32A Two-wire Serial Interface operation. Other devices connected to the Two-wireSerial Bus need only obey the general f SCL requirement.Figure 27-5.Two-wire Serial Bus Timingt oft rSCLt SU;STAt LOWt HIGHt LOWt HD;STA t HD;DAT tSU;DATt SU;STOt BUFSDA27.7 SPI Timing CharacteristicsSee Figure 27-6 and Figure 27-7 for details.Table 27-3. SPI Timing ParametersDescription Mode Min Typ Max1 SCK period Master See Table 18-42 SCK high/low Master 50% duty cycle3 Rise/Fall time Master 3.64 Setup Master 105 Hold Master 106 Out to SCK Master 0.5 • t SCK7 SCK to out Master 108 SCK to out high Master 109 SS low to out Slave 15ns10 SCK period Slave 4 • t ck11 SCK high/low Slave 2 • t ck12 Rise/Fall time Slave 1.6 µs8155C–AVR–02/11302