ATmega32A Datasheet - Sunrom Technologies

ATmega32ANote: 1. The timing requirements shown in Figure 26-7 (that is, t DVXH , t XHXL , and t XLDX ) also apply toreading operation.Table 26-11. Parallel Programming Characteristics, V CC = 5V ±10%Symbol Parameter Min Typ Max UnitsV PP Programming Enable Voltage 11.5 12.5 VI PP Programming Enable Current 250 μAt DVXH Data and Control Valid before XTAL1 High 67 nst XLXH XTAL1 Low to XTAL1 High 200 nst XHXL XTAL1 Pulse Width High 150 nst XLDX Data and Control Hold after XTAL1 Low 67 nst XLWL XTAL1 Low to WR Low 0 nst XLPH XTAL1 Low to PAGEL high 0 nst PLXH PAGEL low to XTAL1 high 150 nst BVPH BS1 Valid before PAGEL High 67 nst PHPL PAGEL Pulse Width High 150 nst PLBX BS1 Hold after PAGEL Low 67 nst WLBX BS2/1 Hold after WR Low 67 nst PLWL PAGEL Low to WR Low 67 nst BVWL BS1 Valid to WR Low 67 nst WLWH WR Pulse Width Low 150 nst WLRL WR Low to RDY/BSY Low 0 1 μst WLRH WR Low to RDY/BSY High (1) 3.7 4.5 mst WLRH_CE WR Low to RDY/BSY High for Chip Erase (2) 7.5 9 mst XLOL XTAL1 Low to OE Low 0 nst BVDV BS1 Valid to DATA valid 0 250 nst OLDV OE Low to DATA Valid 250 nst OHDZ OE High to DATA Tri-stated 250 nsNotes: 1. t WLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bitscommands.2. t WLRH_CE is valid for the Chip Erase command.26.8 SPI Serial DownloadingBoth the Flash and EEPROM memory arrays can be programmed using the serial SPI bus whileRESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input), and MISO(output). After RESET is set low, the Programming Enable instruction needs to be executed firstbefore program/erase operations can be executed. NOTE, in Table 26-12 on page 280, the pinmapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internalSPI interface.8155C–AVR–02/11280