ATmega32A Datasheet - Sunrom Technologies

ATmega32A25.9 Register Description25.9.1 SPMCR – Store Program Memory Control RegisterThe Store Program Memory Control Register contains the control bits needed to control the BootLoader operations.Bit 7 6 5 4 3 2 1 0SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN SPMCRRead/Write R/W R R R/W R/W R/W R/W R/WInitial value 0 0 0 0 0 0 0 0• Bit 7 – SPMIE: SPM Interrupt EnableWhen the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPMready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMENbit in the SPMCR Register is cleared.• Bit 6 – RWWSB: Read-While-Write Section BusyWhen a self-programming (Page Erase or Page Write) operation to the RWW section is initiated,the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannotbe accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after aSelf-Programming operation is completed. Alternatively the RWWSB bit will automatically becleared if a page load operation is initiated.• Bit 5 – Reserved BitThis bit is a reserved bit in the ATmega32A and always read as zero.• Bit 4 – RWWSRE: Read-While-Write Section Read EnableWhen programming (Page Erase or Page Write) to the RWW section, the RWW section isblocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, theuser software must wait until the programming is completed (SPMEN will be cleared). Then, ifthe RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction withinfour clock cycles re-enables the RWW section. The RWW section cannot be re-enabled whilethe Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is writtenwhile the Flash is being loaded, the Flash load operation will abort and the data loaded willbe lost.• Bit 3 – BLBSET: Boot Lock Bit SetIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clockcycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z-pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the Lockbit set, or if no SPM instruction is executed within four clock cycles.An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR Register,will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into thedestination register. See “Reading the Fuse and Lock Bits from Software” on page 260 fordetails.• Bit 2 – PGWRT: Page WriteIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clockcycles executes Page Write, with the data stored in the temporary buffer. The page address istaken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit8155C–AVR–02/11265