ATmega32A Datasheet - Sunrom Technologies

ATmega32ATable 24-6.Algorithm for Using the ADCStep Actions ADCEN DAC MUXEN HOLD PRECH1 SAMPLE_PRELOADUsing this algorithm, the timing constraint on the HOLD signal constrains the TCK clock frequency.As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be atleast five times the number of scan bits divided by the maximum hold time, t hold,max .24.6 ATmega32A Boundary-scan OrderTable 24-7 shows the scan order between TDI and TDO when the Boundary-scan chain isselected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. Thescan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned inthe opposite bit order of the other ports. Exceptions from the rules are the Scan chains for theanalog circuits, which constitute the most significant bits of the scan chain regardless of whichphysical pin they are connected to. In Figure 24-3, PXn. Data corresponds to FF0, PXn. Controlcorresponds to FF1, and PXn. Pullup_enable corresponds to FF2. Bit 2, 3, 4, and 5 of Port C isnot in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled.PA3.DataPA3.ControlPA3.Pullup_Enable1 0x200 0x08 1 1 0 0 02 EXTEST 1 0x200 0x08 0 1 0 0 03 1 0x200 0x08 1 1 0 0 04 1 0x123 0x08 1 1 0 0 05 1 0x123 0x08 1 0 0 0 06 Verify theCOMP bitscannedout to be 01 0x200 0x08 1 1 0 0 07 1 0x200 0x08 0 1 0 0 08 1 0x200 0x08 1 1 0 0 09 1 0x143 0x08 1 1 0 0 010 1 0x143 0x08 1 0 0 0 011 Verify theCOMP bitscannedout to be 1Table 24-7.1 0x200 0x08 1 1 0 0 0ATmega32A Boundary-scan OrderBit Number Signal Name Module140 AC_IDLE Comparator139 ACO138 ACME137 ACBG8155C–AVR–02/11247