ATmega32A Datasheet - Sunrom Technologies

ATmega32AFigure 24-7.Boundary-scan Cells for Oscillators and Clock OptionsXTAL1/TOSC1XTAL2/TOSC2From Digital LogicShiftDR01ToNextCellD Q D QGEXTEST01ENABLEOscillatorOUTPUTShiftDR01DFF1QToNextCellTo System LogicFromPreviousCellClockDRUpdateDRFromPreviousCellClockDRTable 24-3 summaries the scan registers for the external clock pin XTAL1, Oscillators withXTAL1/XTAL2 connections as well as 32kHz Timer Oscillator.Table 24-3. Scan Signals for the Oscillators (1)(2)(3)Enable Signal Scanned Clock Line Clock OptionScanned Clock Linewhen not UsedEXTCLKEN EXTCLK (XTAL1) External Clock 0OSCON OSCCK External CrystalExternal CeramicResonatorRCOSCEN RCCK External RC 1OSC32EN OSC32CK Low Freq. External Crystal 0TOSKON TOSCK 32kHz Timer Oscillator 0Notes: 1. Do not enable more than one clock source as main clock at a time.2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift betweenthe Internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock ispreferred.3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clockconfiguration is considered fixed for a given application. The user is advised to scan the sameclock option as to be used in the final system. The enable signals are supported in the scanchain because the system logic can disable clock options in sleep modes, thereby disconnectingthe Oscillator pins from the scan path if not provided. The INTCAP fuses are not supportedin the scan-chain, so the boundary scan chain can not make a XTAL Oscillator requiring internalcapacitors to run unless the fuse is correctly programmed.24.5.5 Scanning the Analog ComparatorThe relevant Comparator signals regarding Boundary-scan are shown in Figure 24-8. TheBoundary-scan cell from Figure 24-9 is attached to each of these signals. The signals aredescribed in Table 24-4.08155C–AVR–02/11241