ATmega32A Datasheet - Sunrom Technologies
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ATmega32A Datasheet - Sunrom Technologies

ATmega32A Datasheet - Sunrom Technologies ATmega32A Datasheet - Sunrom Technologies

sunrom.com
12.07.2015 Views

ATmega32A• 2 single Program Memory Break Points + 2 single Data Memory Break Points• 2 single Program Memory Break Points + 1 Program Memory Break Point with mask (“rangeBreak Point”)• 2 single Program Memory Break Points + 1 Data Memory Break Point with mask (“rangeBreak Point”)A debugger, like the AVR Studio, may however use one or more of these resources for its internalpurpose, leaving less flexibility to the end-user.A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAGInstructions” on page 231.The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, theOCDEN Fuse must be programmed and no Lock bits must be set for the On-chip Debug systemto work. As a security feature, the On-chip Debug system is disabled when any Lock bits are set.Otherwise, the On-chip Debug system would have provided a back-door into a secured device.The AVR JTAG ICE from Atmel is a powerful development tool for On-chip Debugging of allAVR 8-bit RISC Microcontrollers with IEEE 1149.1 compliant JTAG interface. The JTAG ICEand the AVR Studio user interface give the user complete control of the internal resources of themicrocontroller, helping to reduce development time by making debugging easier. The JTAGICE performs real-time emulation of the micrcontroller while it is running in a target system.Please refer to the Support Tools section on the AVR pages on www.atmel.com for a fulldescription of the AVR JTEG ICE. AVR Studio can be downloaded free from Software sectionon the same web site.All necessary execution commands are available in AVR Studio, both on source level and ondisassembly level. The user can execute the program, single step through the code either bytracing into or stepping over functions, step out of functions, place the cursor on a statement andexecute until the statement is reached, stop the execution, and reset the execution target. Inaddition, the user can have an unlimited number of code breakpoints (using the BREAK instruction)and up to two data memory breakpoints, alternatively combined as a mask (range) BreakPoint.23.7 On-chip Debug Specific JTAG InstructionsThe On-chip Debug support is considered being private JTAG instructions, and distributed withinATMEL and to selected third party vendors only. Instruction opcodes are listed for reference.23.7.1 PRIVATE0; $823.7.2 PRIVATE1; $923.7.3 PRIVATE2; $APrivate JTAG instruction for accessing On-chip Debug system.Private JTAG instruction for accessing On-chip Debug system.Private JTAG instruction for accessing On-chip Debug system.23.7.4 PRIVATE3; $BPrivate JTAG instruction for accessing On-chip Debug system.8155C–AVR–02/11232

ATmega32A23.8 Using the JTAG Programming CapabilitiesProgramming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI andTDO. These are the only pins that need to be controlled/observed to perform JTAG programming(in addition to power pins). It is not required to apply 12V externally. The JTAGEN fusemust be programmed and the JTD bit in the MCUSR Register must be cleared to enable theJTAG Test Access Port.23.9 Register Description23.9.1 OCDR – On-chip Debug RegisterThe JTAG programming capability supports:• Flash programming and verifying• EEPROM programming and verifying• Fuse programming and verifying• Lock bit programming and verifyingThe Lock bit security is exactly as in Parallel Programming mode. If the Lock bits LB1 or LB2 areprogrammed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is asecurity feature that ensures no back-door exists for reading out the content of a secureddevice.The details on programming through the JTAG interface and programming specific JTAGinstructions are given in the section “Programming via the JTAG Interface” on page 284.Bit 7 6 5 4 3 2 1 0MSB/IDRD LSB OCDRRead/Write R/W R/W R/W R/W R/W R/W R/W R/WInitial Value 0 0 0 0 0 0 0 0The OCDR Register provides a communication channel from the running program in the microcontrollerto the debugger. The CPU can transfer a byte to the debugger by writing to thislocation. At the same time, an Internal Flag; I/O Debug Register Dirty – IDRD – is set to indicateto the debugger that the register has been written. When the CPU reads the OCDR Register the7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears theIDRD bit when it has read the information.In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDRRegister can only be accessed if the OCDEN Fuse is programmed, and the debugger enablesaccess to the OCDR Register. In all other cases, the standard I/O location is accessed.Refer to the debugger documentation for further information on how to use this register.23.10 BibliographyFor more information about general Boundary-scan, the following literature can be consulted:• IEEE: IEEE Std 1149.1-1990. IEEE Standard Test Access Port and Boundary-scanArchitecture, IEEE, 1993• Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley,19928155C–AVR–02/11233

<strong>ATmega32A</strong>23.8 Using the JTAG Programming CapabilitiesProgramming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI andTDO. These are the only pins that need to be controlled/observed to perform JTAG programming(in addition to power pins). It is not required to apply 12V externally. The JTAGEN fusemust be programmed and the JTD bit in the MCUSR Register must be cleared to enable theJTAG Test Access Port.23.9 Register Description23.9.1 OCDR – On-chip Debug RegisterThe JTAG programming capability supports:• Flash programming and verifying• EEPROM programming and verifying• Fuse programming and verifying• Lock bit programming and verifyingThe Lock bit security is exactly as in Parallel Programming mode. If the Lock bits LB1 or LB2 areprogrammed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is asecurity feature that ensures no back-door exists for reading out the content of a secureddevice.The details on programming through the JTAG interface and programming specific JTAGinstructions are given in the section “Programming via the JTAG Interface” on page 284.Bit 7 6 5 4 3 2 1 0MSB/IDRD LSB OCDRRead/Write R/W R/W R/W R/W R/W R/W R/W R/WInitial Value 0 0 0 0 0 0 0 0The OCDR Register provides a communication channel from the running program in the microcontrollerto the debugger. The CPU can transfer a byte to the debugger by writing to thislocation. At the same time, an Internal Flag; I/O Debug Register Dirty – IDRD – is set to indicateto the debugger that the register has been written. When the CPU reads the OCDR Register the7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears theIDRD bit when it has read the information.In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDRRegister can only be accessed if the OCDEN Fuse is programmed, and the debugger enablesaccess to the OCDR Register. In all other cases, the standard I/O location is accessed.Refer to the debugger documentation for further information on how to use this register.23.10 BibliographyFor more information about general Boundary-scan, the following literature can be consulted:• IEEE: IEEE Std 1149.1-1990. IEEE Standard Test Access Port and Boundary-scanArchitecture, IEEE, 1993• Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley,19928155C–AVR–02/11233

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