ATmega32A Datasheet - Sunrom Technologies

ATmega32AFigure 20-9.Overview of the TWI ModuleSCLSDASlew-rateControlSpikeFilterSlew-rateControlSpikeFilterBus Interface UnitBit Rate GeneratorSTART / STOPControlSpike SuppressionPrescalerArbitration detectionAddress/Data ShiftRegister (TWDR)AckBit Rate Register(TWBR)Address Match UnitControl UnitAddress Register(TWAR)Address ComparatorStatus Register(TWSR)State Machine andStatus controlControl Register(TWCR)TWI Unit20.5.1 SCL and SDA PinsThese pins interface the AVR TWI with the rest of the MCU system. The output drivers contain aslew-rate limiter in order to conform to the TWI specification. The input stages contain a spikesuppression unit removing spikes shorter than 50 ns. Note that the internal pullups in the AVRpads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, asexplained in the I/O Port section. The internal pull-ups can in some systems eliminate the needfor external ones.20.5.2 Bit Rate Generator UnitThis unit controls the period of SCL when operating in a Master mode. The SCL period is controlledby settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI StatusRegister (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but theCPU clock frequency in the slave must be at least 16 times higher than the SCL frequency. Notethat slaves may prolong the SCL low period, thereby reducing the average TWI bus clockperiod. The SCL frequency is generated according to the following equation:SCL frequencyCPU Clock frequency= ----------------------------------------------------------16 + 2(TWBR) ⋅ 4 TWPS• TWBR = Value of the TWI Bit Rate Register• TWPS = Value of the prescaler bits in the TWI Status RegisterNote: Pull-up resistor values should be selected according to the SCL frequency and the capacitive busline load. See Table 27-2 on page 300 for value of pull-up resistor.8155C–AVR–02/11183